CN110518106A - 一种垂直结构芯片制备方法 - Google Patents
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- 239000010409 thin film Substances 0.000 title claims abstract description 15
- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- 239000010408 film Substances 0.000 claims abstract description 20
- 238000002161 passivation Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 15
- 238000005520 cutting process Methods 0.000 claims abstract description 8
- 238000009966 trimming Methods 0.000 claims abstract description 8
- 230000008020 evaporation Effects 0.000 claims abstract description 4
- 238000001704 evaporation Methods 0.000 claims abstract description 4
- 230000000694 effects Effects 0.000 abstract description 5
- 230000002411 adverse Effects 0.000 abstract description 3
- 238000003698 laser cutting Methods 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000003776 cleavage reaction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 230000007017 scission Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
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Abstract
本发明提供了一种垂直结构芯片制备方法,包括:S1在生长衬底依次生长GaN结构,包括N型GaN层、量子阱层及P型GaN层;S2对GaN结构的周边进行蚀刻直至露出PN结;S3在GaN结构和PN结表面覆盖钝化膜层;S4在钝化膜层表面蒸发邦定金属层,并通过该邦定金属层与支撑衬底邦定露出GaN结构;S5对GaN结构进行去边并制作出用于切割的沟槽,沿沟槽进行切割得到单颗LED芯片。在N面去边后PN结仍然被钝化膜层和邦定金属覆盖,埋藏在芯片内侧,大大降低了刀片切割正崩带来的漏电影响、激光切割能量传导带来的漏电影响及成品在高温高湿等恶劣环境中使用带来的漏电风险,提高了芯片及成品的可靠性。
Description
技术领域
本发明涉及LED技术领域,尤其是一种垂直结构芯片制备方法。
背景技术
在垂直结构芯片制备的过程中,一般在邦定后的N面GaN表面钝化,采用SiO2或SiNx等绝缘膜覆盖芯片边缘、GaN侧面的PN结,从芯片沟槽处可看到PN结。
如图1所示,GaN结构(包括P型GaN层3和4-N型GaN层4)通过邦定金属层2邦定在支撑衬底1表面,钝化膜层5覆盖在GaN结构和沟槽表面。但是,由于PN结8外露在GaN侧面且表面仅钝化一层SiO2或SiNx覆盖,比较薄弱,在后段的刀片切割或激光划片(对应刀片或激光切割位6)中钝化层或GaN PN结组分容易受到影响造成漏电,从而影响LED芯片的良率和可靠性。在LED产品的使用中同样易受高温或高湿等外界环境的影响导致漏电,影响产品的可靠性。
发明内容
为了克服以上不足,本发明提供了一种垂直结构芯片制备方法,有效解决了现有垂直结构芯片易受外界环境影响造成漏电的情况。
本发明提供的技术方案为:
一种垂直结构芯片制备方法,包括:
S1在生长衬底依次生长GaN结构,包括N型GaN层、量子阱层及P型GaN层;
S2对所述GaN结构的周边进行蚀刻直至露出PN结;
S3在所述GaN结构和PN结表面覆盖钝化膜层;
S4在所述钝化膜层表面蒸发邦定金属层,通过该邦定金属层与支撑衬底邦定露出GaN结构并去除生长衬底;
S5对GaN结构进行去边并制作出用于切割的沟槽,沿沟槽进行切割得到单颗LED芯片。
在使用本发明提供的制备方法制备得到的垂直结构芯片中,在N面去边后PN结仍然被钝化膜层和邦定金属覆盖,埋藏在芯片内侧,大大降低了刀片切割正崩带来的漏电影响、激光切割能量传导带来的漏电影响及成品在高温高湿等恶劣环境中使用带来的漏电风险,提高了芯片及成品的可靠性。
附图说明
图1为现有技术中垂直结构芯片切割时的剖面示意图;
图2-8为本发明中垂直结构芯片制备方法流程示意图。
附图标记:
支撑衬底,2-邦定金属层,3-P型GaN层,4-N型GaN层,5-钝化膜层,6-刀片或激光切割位,7-沟槽,8-PN结;
11-生长衬底,12-GaN结构,13-PN结,14-钝化膜层,15-邦定金属层,16-支撑衬底,17-沟槽。
具体实施方式
为了更清楚地说明本发明实施案例或现有技术中的技术方案,下面将对照附图说明本发明的具体实施方式。显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图,并获得其他的实施方式。
针对现有垂直结构芯片在制备过程中存在的问题,本发明提供了一种新的垂直结构芯片制备方法,包括:
S1在生长衬底11依次生长GaN结构12,包括N型GaN层、量子阱层及P型GaN层,如图2所示。在该步骤中,生长衬底11可以为硅、蓝宝石、SiC等,根据情况进行选定。对于GaN结构12仅示例性的给出其基本结构,在实际应用中可以根据具体情况进行调整。
S2对GaN结构12的周边进行蚀刻直至露出PN结13,具体,蚀刻的深度为0.5~1.2μm(微米)。在该步骤中,采用ICP干法刻蚀对GaN结构12的周边进行蚀刻。
S3在GaN结构12和PN结13表面覆盖钝化膜层14,厚度为0.1~1μm,如图4所示。如图5所示为俯视示意图,其中,图5(a)为钝化膜层14全包蚀刻区域(GaN结构12外圈)示意图;图5(b)为钝化膜层14未全包蚀刻区域示意图,即,在实际应用中,可以根据实际应用需求选定钝化膜层14覆盖的范围。钝化膜层的材料可以为SiO2或SiNx等绝缘材料。
S4在钝化膜层14表面蒸发邦定金属层15,如图6所示;通过该邦定金属层与支撑衬底邦定露出GaN结构,如图7所示;之后去除生长衬底。其中,支撑衬底16可以为硅衬底等,这里不做限定。邦定金属层的材料可以为Au、AuSn、Sn等。
S5对GaN结构12进行去边并制作出用于切割的沟槽17(去边后GaN结构12边缘距离蚀刻表面3~10μm),如图8所示,沿沟槽17进行切割得到单颗LED芯片。从图中可以看出,PN结13在GaN内侧并被多层薄膜(包括钝化膜层14和邦定金属层15)包裹保护,隐藏在内侧,从而降低了刀片切割正崩带来的漏电影响、激光切割能量传导带来的漏电影响及成品在高温高湿等恶劣环境中使用带来的漏电风险,大大提高了芯片及成品的可靠性。
要特别指出的是,本申请中仅涉单颗芯片周边GaN处理的过程,对于芯片P电极与N电极的制作涉及,在实际应用中,可以采用现有的任意方法对芯片的P电极与N电极进行制作。
应当说明的是,上述实施例均可根据需要自由组合。以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。
Claims (3)
1.一种垂直结构芯片制备方法,其特征在于,包括:
S1在衬底上依次生长GaN结构,包括N型GaN层、量子阱层及P型GaN层;
S2对所述GaN结构的周边进行蚀刻直至露出PN结;
S3在所述GaN结构和PN结表面覆盖钝化膜层;
S4在所述钝化膜层表面蒸发邦定金属层,通过该邦定金属层与支撑衬底邦定露出GaN结构并去除生长衬底;
S5对GaN结构进行去边并制作出用于切割的沟槽,沿沟槽进行切割得到单颗LED芯片。
2.如权利要求1所述的垂直结构芯片制备方法,其特征在于,步骤S2中蚀刻的深度为0.5~1.2μm,且蚀刻表面距离步骤S5中去边后的GaN结构边缘3~10μm。
3.如权利要求1所述的垂直结构芯片制备方法,其特征在于,在步骤S3中,钝化膜层的厚度为0.1~1μm。
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Citations (2)
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CN101847675A (zh) * | 2009-10-30 | 2010-09-29 | 武汉华灿光电有限公司 | 垂直结构发光二极管芯片结构及其制造方法 |
CN108847438A (zh) * | 2018-03-30 | 2018-11-20 | 映瑞光电科技(上海)有限公司 | 一种led芯片及其制造方法 |
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CN101847675A (zh) * | 2009-10-30 | 2010-09-29 | 武汉华灿光电有限公司 | 垂直结构发光二极管芯片结构及其制造方法 |
CN108847438A (zh) * | 2018-03-30 | 2018-11-20 | 映瑞光电科技(上海)有限公司 | 一种led芯片及其制造方法 |
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