CN110504000A - The method that wafer-level test identifies probe card information with test machine - Google Patents
The method that wafer-level test identifies probe card information with test machine Download PDFInfo
- Publication number
- CN110504000A CN110504000A CN201910788131.3A CN201910788131A CN110504000A CN 110504000 A CN110504000 A CN 110504000A CN 201910788131 A CN201910788131 A CN 201910788131A CN 110504000 A CN110504000 A CN 110504000A
- Authority
- CN
- China
- Prior art keywords
- probe card
- card information
- storage chip
- test machine
- test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
Abstract
The invention discloses a kind of method that wafer-level test identifies probe card information with test machine, step 1 designs and produces one piece of probe card, and one piece is arranged in the probe card for storing the storage chip of probe card information；Step 2 inputs correct probe card information to the storage chip using write-in algorithm and verifies completion；Step 3 judges whether it is matched probe card using the probe card information in readout algorithm identification storage chip.The present invention can be reduced to change to the maximum extent and be lost brought by wrong probe card, and test machine can obtain the correct information in probe card storage chip automatically.
Description
Technical field
The present invention relates to semiconductor integrated circuit fields, identify probe more particularly to a kind of wafer-level test test machine
The method of card information.
Background technique
In IC chip test field, the method that wafer stage chip power of test is established on test machine is for a kind of core
Piece customizes one piece of probe card, is connected by hard contact with test machine load board above test machine probe card, underrun
Probe is connected with chip pin, becomes the bridge connected between test machine signal path and chip under test pin, in turn
Preliminary surveying is carried out to chip electric property applied to before chip package, the encapsulation after filtering out bad chip, then after carrying out
Engineering.So when testing different chips, it is necessary to change corresponding probe card and be tested, then the replaced probe card of identification
Correctness with regard to particularly important.
In wafer stage chip test, in order to ensure probe card used and institute's test item exactly match, so needing one kind
Simple and reliable method identifies probe card information.
But in present wafer stage chip test, identify that the mode of probe card is by pasting on scanning probe card case
Bar code, the bar code information of typing is obtained from probe card management system, and then probe card information input to test machine
In.After probe card of the operator because of operation error replacement mistake, the test of chip even damages spy after necessarily will affect
Needle card drags slow project process.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of wafer-level test sides of test machine identification probe card information
Method can be reduced to change to the maximum extent and be lost brought by wrong probe card, and test machine can obtain automatically in probe card storage chip
Correct information.
In order to solve the above technical problems, the method that wafer-level test of the invention identifies probe card information with test machine, is
Adopt the following technical scheme that realization:
Step 1 designs and produces one piece of probe card, and one piece is arranged in the probe card for storing the storage of probe card information
Chip；
Step 2 inputs correct probe card information to the storage chip using write-in algorithm and verifies completion；
Step 3 judges whether it is matched probe card using the probe card information in readout algorithm identification storage chip.
Using method of the invention, in probe card production phase, design increases by one piece of storage chip on the probe card
For storing probe card information, by the cooperation with testing algorithm, so that test machine is obtained identification probe card information automatically, substantially subtract
It is small because operator replaces wrong probe card bring risk, minimize the wrong probe card bring probe card damage of replacement
The risks such as waste, delay project process when bad, machine.
Method of the invention can save the operating time of operator, and weight manually is not needed between each product test project
New typing probe card information.
Detailed description of the invention
Present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:
Fig. 1 is storage chip design principle schematic diagram；
Fig. 2 is testing process schematic diagram.
Specific embodiment
The method that the wafer-level test identifies probe card information with test machine, it is contemplated that because of operator in wafer-level test
After member's fault is put into the probe card of mistake, test even damage probe card is influenced, slow project process is dragged, so in probe card designs
Stage one piece of storage chip of more increases in probe card, the effect of the storage chip are to store the information of probe card.
The method that the wafer-level test identifies probe card information with test machine, is embodied in the following embodiments
Process is as follows:
Step 1 designs and produces one piece of probe card, and one piece is arranged in the probe card for storing the storage of probe card information
Chip.
Step 2, exploitation and the matched probe card Card read/write algorithm (i.e. testing algorithm) of probe card.
Step 3 inputs correct probe card information to the storage chip using write-in algorithm and verifies completion.
Step 4 identifies the probe card information in storage chip using readout algorithm, judges whether it is matched probe card.
Fig. 1 is the design principle schematic diagram of the storage chip, and storage chip A0 (address of devices signal), (power supply is defeated by VCC
Entering) pin connects power supply and draws high, and A1 and A2 (address of devices signal), WP (write-protect), VSS (power ground) pin ground connection drag down, and deposit
Storage chip SCL (clock signal chip) pin is connected with test machine load board CSCL (test machine clock lane) signal path,
Storage chip SDA (chip data transmission signal) pin and test machine load board CSDA (test machine data transmission channel) signal are logical
Road is connected, and can be written and read to storage chip by test machine.The black dot of Fig. 1 is the identification in chip direction
Point.
Test machine is first responsible for the probe card information character data of input to pass through ASCII (U.S. information exchange when write-in
Standard code) code is converted into binary data, subsequent test machine toward storage chip transmission chip address and probe card information two into
Data processed, final storage chip store probe card information in destination address.Test machine is toward storage chip transmission chip when reading
Location data, storage chip return to test machine after destination address reads binary data, and test machine passes through ASCII (U.S. information
Exchange standard code) code is converted into character data.Finally by the character data of reading compared with the probe card information of write-in,
Judge whether it is matched probe card.
When using probe card, it is necessary first to be stored in correct probe into storage chip by the way that algorithm is written testing the card stage
Card information, operator only needs to read and identified in storage chip automatically by specified readout algorithm in later use
Probe card information to determine whether be matched probe card, just will do it follow-up test when being judged as correct.Testing process shows
Be intended to carry out proper testing as shown in Fig. 2, pass through if probe card is identified, if probe card is identified do not pass through if be mistake
Probe card needs to change probe card and re-starts identification.Therefore, the wafer-level test test machine identifies setting for probe card information
Meter method, it is only necessary to increase by one piece of storage chip cooperation testing algorithm (i.e. " write-in algorithm " and " readout algorithm ") on the probe card
It can achieve the purpose that test machine obtains identification probe card information automatically.
Above by specific embodiment, invention is explained in detail, but these are not constituted to of the invention
Limitation.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these
It should be regarded as protection scope of the present invention.
Claims (6)
1. a kind of method that wafer-level test identifies probe card information with test machine, which comprises the steps of:
Step 1 designs and produces one piece of probe card, and one piece is arranged in the probe card for storing the storage core of probe card information
Piece；
Step 2 inputs correct probe card information to the storage chip using write-in algorithm and verifies completion；
Step 3 identifies the probe card information in storage chip using readout algorithm, judges whether it is matched probe card.
2. the method as described in claim 1, it is characterised in that: pass through if probe card is identified, carry out proper testing, if visiting
Needle card is identified not by being then wrong probe card, needs to change probe card and re-starts identification.
3. the method as described in claim 1, it is characterised in that: the storage chip A0, VCC pin meet power supply, A1, A2, WP
It is grounded with VSS pin, SCL pin is connected with the CSCL signal path of test machine load board, SDA pin and test machine load board
CSDA signal path is connected, and is written and read by test machine to storage chip.
4. method as claimed in claim 1 or 3, it is characterised in that: test machine is first by the probe card information of input when write-in
Character data is converted into binary data by ASCII character, and subsequent test machine is toward storage chip transmission chip address and probe card
Information binary data, final storage chip store probe card information in destination address.
5. method as claimed in claim 1 or 3, it is characterised in that: test machine is toward storage chip transmission chip address when reading
Data, storage chip return to test machine after destination address reads binary data, and test machine is converted into character by ASCII character
Data judge whether it is matched probe card finally by the character data of reading compared with the probe card information of write-in.
6. the method as described in claim 1, it is characterised in that: when using probe card, it is necessary first to test the card stage by writing
Enter algorithm and be stored in correct probe card information into storage chip, only needs in later use through specified readout algorithm
The automatic probe card information for reading and identifying in storage chip is judged as correct Shi Caihui to determine whether for matched probe card
Carry out follow-up test.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910788131.3A CN110504000B (en) | 2019-08-26 | 2019-08-26 | Method for identifying probe card information of wafer-level test tester |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910788131.3A CN110504000B (en) | 2019-08-26 | 2019-08-26 | Method for identifying probe card information of wafer-level test tester |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110504000A true CN110504000A (en) | 2019-11-26 |
| CN110504000B CN110504000B (en) | 2021-04-13 |
Family
ID=68589363
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910788131.3A Active CN110504000B (en) | 2019-08-26 | 2019-08-26 | Method for identifying probe card information of wafer-level test tester |
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| Country | Link |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112798998A (en) * | 2020-12-31 | 2021-05-14 | 杭州广立微电子股份有限公司 | Method for processing abnormal state of wafer test probe card |
| CN113447791A (en) * | 2020-03-25 | 2021-09-28 | 北京确安科技股份有限公司 | Method and device for detecting resource sharing structure test load board and electronic equipment |
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| CN101501512A (en) * | 2006-06-13 | 2009-08-05 | 佛姆法克特股份有限公司 | Method of designing an application specific probe card test system |
| CN103018650A (en) * | 2012-12-04 | 2013-04-03 | 无锡圆方半导体测试有限公司 | Wafer detection system |
| CN103199041A (en) * | 2013-03-14 | 2013-07-10 | 上海华力微电子有限公司 | Management system of wafer acceptable test procedure and application method thereof |
| CN103336257A (en) * | 2013-06-26 | 2013-10-02 | 上海华力微电子有限公司 | WAT testing system and method |
| CN103439643A (en) * | 2013-08-02 | 2013-12-11 | 上海华力微电子有限公司 | Intelligent test system and test method for improving probe card test abnormality |
| CN103823089A (en) * | 2013-11-26 | 2014-05-28 | 上海华力微电子有限公司 | Probe card |
| CN105097597A (en) * | 2015-07-30 | 2015-11-25 | 上海华力微电子有限公司 | System and method for automatically releasing WAT PM probe card |
| CN108519550A (en) * | 2018-03-28 | 2018-09-11 | 上海华岭集成电路技术股份有限公司 | IC wafers test optimization method |
| CN209000871U (en) * | 2018-12-07 | 2019-06-18 | 紫光同芯微电子有限公司 | A kind of wafer test system |
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2019
- 2019-08-26 CN CN201910788131.3A patent/CN110504000B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101501512A (en) * | 2006-06-13 | 2009-08-05 | 佛姆法克特股份有限公司 | Method of designing an application specific probe card test system |
| CN103018650A (en) * | 2012-12-04 | 2013-04-03 | 无锡圆方半导体测试有限公司 | Wafer detection system |
| CN103199041A (en) * | 2013-03-14 | 2013-07-10 | 上海华力微电子有限公司 | Management system of wafer acceptable test procedure and application method thereof |
| CN103336257A (en) * | 2013-06-26 | 2013-10-02 | 上海华力微电子有限公司 | WAT testing system and method |
| CN103439643A (en) * | 2013-08-02 | 2013-12-11 | 上海华力微电子有限公司 | Intelligent test system and test method for improving probe card test abnormality |
| CN103823089A (en) * | 2013-11-26 | 2014-05-28 | 上海华力微电子有限公司 | Probe card |
| CN105097597A (en) * | 2015-07-30 | 2015-11-25 | 上海华力微电子有限公司 | System and method for automatically releasing WAT PM probe card |
| CN108519550A (en) * | 2018-03-28 | 2018-09-11 | 上海华岭集成电路技术股份有限公司 | IC wafers test optimization method |
| CN209000871U (en) * | 2018-12-07 | 2019-06-18 | 紫光同芯微电子有限公司 | A kind of wafer test system |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113447791A (en) * | 2020-03-25 | 2021-09-28 | 北京确安科技股份有限公司 | Method and device for detecting resource sharing structure test load board and electronic equipment |
| CN112798998A (en) * | 2020-12-31 | 2021-05-14 | 杭州广立微电子股份有限公司 | Method for processing abnormal state of wafer test probe card |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110504000B (en) | 2021-04-13 |
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