CN110489359A - A kind of data transfer control method and system - Google Patents
A kind of data transfer control method and system Download PDFInfo
- Publication number
- CN110489359A CN110489359A CN201910779842.4A CN201910779842A CN110489359A CN 110489359 A CN110489359 A CN 110489359A CN 201910779842 A CN201910779842 A CN 201910779842A CN 110489359 A CN110489359 A CN 110489359A
- Authority
- CN
- China
- Prior art keywords
- data
- order
- master controller
- sent
- master
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
- G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Communication Control (AREA)
- Bus Control (AREA)
- Storage Device Security (AREA)
Abstract
This application discloses a kind of data transfer control methods, including receiving the order of the main transmission of SD and the order being sent to CPU, so that the CPU is based on the order and configures SD master controller；When it is described order for write data command when, receive the data of the main transmission of the SD and the data be sent to the SD master controller, with by the SD master controller by the data write-in SD from；When the order is reads data command, the data that the received SD master controller is sent are read in into the SD master.The data transfer control method realizes that data are transmitted from controller and the cooperation of SD master controller using the SD in system on chip, can effectively improve message transmission rate.Disclosed herein as well is a kind of data transfer control systems, equally have above-mentioned technique effect.
Description
Technical field
This application involves field of computer technology, in particular to a kind of data transfer control method；Further relate to a kind of data
Transmission control system.
Background technique
Currently, data transfer mode be controlled using CPU and realize forms data block transmission, cause data transmission compared with
Slowly.And for improve data transfer speed, system need to work in higher frequency, will cause biggish power consumption in this way.And work as
The things of CPU processing is more, and treatment effeciency can reduce, to influence the reliability of system.Therefore, how improve data transfer
Rate has become those skilled in the art's technical problem urgently to be resolved.
Summary of the invention
The purpose of the application is to provide a kind of data transfer control method and system, can effectively improve data transmission speed
Rate.
In order to solve the above technical problems, this application provides a kind of data transfer control methods, comprising:
It receives the order of the main transmission of SD and the order is sent to CPU, so that the CPU is based on the order and configures SD
Master controller；
When the order is writes data command, receives the data of the main transmission of the SD and be sent to the data described
SD master controller, with by the SD master controller by the data be written SD from；
When the order is reads data command, the data that the received SD master controller is sent are read in into the SD
It is main.
Optionally, described when the order is writes data command, receive the data of the main transmission of the SD and by the number
According to being sent to the SD master controller, comprising:
If the order receives the data of the main transmission of the SD simultaneously to write data command and transmission mode is direct mode operation
The data are directly sent to SD master controller；
If the order is writes data command and transmission mode is encryption mode, the data for receiving the main transmission of the SD will
The data are sent to the SD master controller by SRAM and DMA encryption and decryption equipment.
Optionally, the data that when the order is reads data command, the received SD master controller is sent
Read in the SD master, comprising:
If the order is reading data command and transmission mode is direct mode operation, the SD master controller hair is directly received
The data sent, and the data are read in into the SD master；
If the order is reading data command and transmission mode is encryption mode, receives the SD master controller and pass through institute
The data of SRAM and DMA encryption and decryption equipment transmission are stated, and the data are read in into the SD master.
Optionally, further includes:
Judge whether to receive and cease and desist order；
It ceases and desist order if receiving, terminates data read-write operation.
In order to solve the above technical problems, present invention also provides a kind of data transfer control systems, comprising:
SD is from controller, SD master controller and CPU；
The SD is used to receive the order of the main transmission of SD from controller and the order is sent to CPU, so that the CPU
SD master controller is configured based on the order；When the order is writes data command, the data of the main transmission of the SD are received simultaneously
The data are sent to the SD master controller, with by the SD master controller by the data be written SD from；When described
When order is reads data command, the data that the received SD master controller is sent are read in into the SD master.
Optionally, if the SD writes data command specifically for the order from controller and transmission mode is straight-through mould
Formula then receives the data of the main transmission of the SD and the data is directly sent to SD master controller；If the order is to write number
It is encryption mode according to order and transmission mode, then the data for receiving the main transmission of the SD add the data by SRAM and DMA
Decryption device is sent to the SD master controller.
Optionally, if the SD is specifically used for from controller, the order is reading data command and transmission mode is straight-through mould
Formula then directly receives the data that the SD master controller is sent, and the data is read in the SD master；If the order is reading
Data command and transmission mode are encryption mode, then receive the SD master controller and pass through the SRAM and the DMA encryption and decryption
The data that equipment is sent, and the data are read in into the SD master.
Optionally, the SD master controller is also used to judge whether to receive to cease and desist order；It ceases and desist order if receiving,
Terminate data read-write operation.
Data transfer control method provided herein, including receiving the order of the main transmission of SD and sending the order
To CPU, so that the CPU is based on the order and configures SD master controller；When the order is writes data command, described in reception
The data are simultaneously sent to the SD master controller by the data of the main transmission of SD, with by the SD master controller by the data
Be written SD from；When the order is reads data command, the data that the received SD master controller is sent are read in into the SD
It is main.
As it can be seen that data transfer control method provided herein, when writing data, SD receives the hair of SD master from controller
This data is simultaneously sent to SD master controller by the data sent, with by SD master controller further write data into SD from；Work as reading
When data, SD receives the data that SD master controller is sent from controller, and data are read in SD master.The data transfer control method
It realizes that data are transmitted from controller and the cooperation of SD master controller using the SD in system on chip, data transmission speed can be effectively improved
Rate.
Data transfer control system provided herein equally has above-mentioned technique effect.
Detailed description of the invention
It in order to more clearly explain the technical solutions in the embodiments of the present application, below will be to institute in the prior art and embodiment
Attached drawing to be used is needed to be briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations of the application
Example, for those of ordinary skill in the art, without creative efforts, can also obtain according to these attached drawings
Obtain other attached drawings.
Fig. 1 is a kind of flow diagram of data transfer control method provided by the embodiment of the present application；
Fig. 2 is a kind of schematic diagram of data transfer control system provided by the embodiment of the present application.
Specific embodiment
The core of the application is to provide a kind of data transfer control method and system, can effectively improve data transmission speed
Rate.
To keep the purposes, technical schemes and advantages of the embodiment of the present application clearer, below in conjunction with the embodiment of the present application
In attached drawing, the technical scheme in the embodiment of the application is clearly and completely described, it is clear that described embodiment is
Some embodiments of the present application, instead of all the embodiments.Based on the embodiment in the application, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall in the protection scope of this application.
Referring to FIG. 1, Fig. 1 is a kind of flow diagram of data transfer control method provided by the embodiment of the present application；
Refering to what is shown in Fig. 1, data transfer control method includes:
S101: receiving the order of the main transmission of SD and send commands to CPU, so that CPU is based on order configuration SD main control
Device；
Specifically, CPU enables SD after controller and SD master controller, SD from controller and SD master controller just into
Enter preliminary transmission state.SD after entering preliminary transmission state is after the order that controller receives the main transmission of SD, and SD is from control
This is ordered and informs CPU by device processed, so that CPU configures SD master controller, specifically i.e. when order is writes data command,
The data address of CPU configuration SD master controller is SD from the buffer area of controller and makes SD master controller to SD from sending most evidences
Block write order；When order is reads data command, the destination address of CPU configuration SD master controller is that SD from controller and makes SD master
Controller is to SD from majority is sent according to read command.
S102: when order is writes data command, receiving the data of the main transmission of SD and send data to SD master controller,
With by SD master controller write data into SD from；
Specifically, on the basis of CPU completes the configuration to SD master controller, when the order of the main transmission of SD is to write data life
When enabling, SD receives the data of the main transmission of SD from controller and this data is further sent to SD master controller, to pass through SD master
Controller by this data be written SD from.
Wherein, above-mentioned when order is writes data command in a kind of specific embodiment, receive the number of the main transmission of SD
According to and if to send data to SD master controller may include: order to write data command and transmission mode is direct mode operation,
It receives the data of the main transmission of SD and directly sends data to SD master controller；If order is writes data command and transmission mode is
Data are passed through SRAM (Staric Random Access Memory, static state by encryption mode, the then data for receiving the main transmission of SD
Random access memory) with DMA (Direct Memory Access, direct memory access (DMA)) encryption and decryption equipment be sent to SD master
Controller.
Specifically, for different transmission modes, Data Transmission Controlling mode when writing data is different in the present embodiment.
If transmission mode is direct mode operation, SD receives the data of the main transmission of SD from controller and directly sends data to SD main control
Device so that SD master controller further write data into SD from.If transmission mode is encryption and decryption mode, the main transmission of SD is received
Data are sent to SD master controller by SRAM and DMA encryption and decryption equipment by data.Specifically, SD receives SD master from controller
The data of transmission and the buffer area that data deposit is built-in, and sent and requested to DMA encryption and decryption equipment according to the state of buffer area,
To write data into a piece of address space in SRAM by DMA encryption and decryption equipment.DMA built in SD master controller waits SRAM
In batch of data be ready to after send it to SD from.SD can receive next lot number of the main transmission of SD from controller at the same time
According to, and write data by DMA encryption and decryption equipment another address space in SRAM.In this way, several addresses in SRAM
Space receives data in turn, the DMA built in SD master controller by the address space of data accepted data be written SD from.
S103: when order is reads data command, the data that received SD master controller is sent read in SD master.
Specifically, on the basis of CPU completes the configuration to SD master controller, when the order of the main transmission of SD is to read data life
When enabling, SD receives the SD that SD master controller is sent from controller and reads in SD from the data for reading in SD master controller, and by this data
It is main.
Wherein, above-mentioned when order is reads data command in a kind of specific embodiment, by received SD main control
If device send data read in SD master may include: order be reading data command and transmission mode be direct mode operation, directly connect
The data that SD master controller is sent are received, and data are read in into SD master；If order is reading data command and transmission mode is encryption mould
Formula then receives the data that SD master controller is sent by SRAM and DMA encryption and decryption equipment, and data is read in SD master.
Specifically, being directed to different transmission modes, Data Transmission Controlling side when two kinds of reading data is present embodiments provided
Formula.If transmission mode be direct mode operation, SD is directly received from controller SD master controller send from SD from data, i.e.,
SD master controller and SD directly carry out data transmission from controller, and received data are further read in SD master.If transmitting mould
Formula is encryption and decryption mode, then SD receives SD master controller from controller and comes from SD by what SRAM and DMA encryption and decryption equipment were sent
From data.Specifically, SD master controller receive from SD from data, and by the batch of data received by built in it
DMA write enters a piece of address space in SRAM.After SRAM is written in the batch data, DMA encryption and decryption equipment further will be in SRAM
The buffer area built in SD from controller is constantly written in data, and then data are read in SD master again from controller by SD.
Further, it can also judge whether to receive from controller including SD and cease and desist order；It ceases and desist order if receiving,
Terminate data read-write operation.Specifically, SD is carrying out data reading operation or write operation described in above-described embodiment from controller
During can also real-time judge whether receive ceasing and desisting order for the main transmission of SD, if receiving, equally this is ceased and desisted order
It is sent to CPU, so that CPU configuration SD master controller is ceased and desisted order to SD from transmission, terminates current read operation or write operation.
In conclusion data transfer control method provided herein, when writing data, SD receives SD master from controller
Transmission data and this data is sent to SD master controller, with by SD master controller further write data into SD from；
When data are read, SD receives the data that SD master controller is sent from controller, and data are read in SD master.The Data Transmission Controlling
Method realizes that data are transmitted from controller and the cooperation of SD master controller using the SD in system on chip, can effectively improve data biography
Defeated rate.
Present invention also provides a kind of data transfer control system, the system described below can be with above-described side
Method corresponds to each other reference.Please refer to shown in Fig. 2, the data transfer control system include SD from controller, SD master controller and
CPU；
SD is used to receive the order of the main transmission of SD from controller and sends commands to CPU, so that CPU is based on order configuration
SD master controller；When order is writes data command, receives the data of the main transmission of SD and send data to SD master controller, with
By SD master controller write data into SD from；When order is reads data command, by the number of received SD master controller transmission
According to reading SD master.
On the basis of the above embodiments, as a kind of specific embodiment, if SD is specifically used for order from controller
To write data command and transmission mode is direct mode operation, then receives the data of the main transmission of SD and directly send data to SD master control
Device processed；If order is writes data command and transmission mode is encryption mode, the data for receiving the main transmission of SD pass through data
SRAM and DMA encryption and decryption equipment are sent to SD master controller.
On the basis of the above embodiments, as a kind of specific embodiment, if SD is specifically used for order from controller
For reading data command and transmission mode is direct mode operation, then directly receives the data that SD master controller is sent, and data are read in
SD master；If order is reading data command and transmission mode is encryption mode, SD master controller is received by SRAM and DMA and adds solution
The data that close equipment is sent, and data are read in into SD master.
On the basis of the above embodiments, as a kind of specific real-time mode, SD master controller is also used to judge whether
It receives and ceases and desist order；It ceases and desist order if receiving, terminates data read-write operation.
Data transfer control system provided herein, when writing data, SD receives the transmission of SD master from controller
This data is simultaneously sent to SD master controller by data, with by SD master controller further write data into SD from；When reading data
When, SD receives the data that SD master controller is sent from controller, and data are read in SD master.The data transfer control method utilizes
SD in system on chip realizes data transmission from controller and the cooperation of SD master controller, can effectively improve message transmission rate.
Each embodiment is described in a progressive manner in specification, the highlights of each of the examples are with other realities
The difference of example is applied, same and similar module may refer to each other between each embodiment.
Professional further appreciates that, unit described in conjunction with the examples disclosed in the embodiments of the present disclosure
And algorithm steps, it can be realized with the combination of electronic hardware, computer equipment software or the two, it is hard in order to clearly demonstrate
The interchangeability of part and software generally describes each exemplary composition and step according to function in the above description.
These functions are implemented in hardware or software actually, the specific application and design constraint depending on technical solution.
Professional technician can use different methods to achieve the described function each specific application, but this realization
It is not considered that exceeding scope of the present application.
The step of method described in conjunction with the examples disclosed in this document or algorithm, can directly be held with hardware, processor
The combination of capable software module or the two is implemented.Software module can be placed in random access memory (RAM), memory, read-only deposit
Reservoir (ROM), electrically programmable ROM, electrically erasable programmable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technology
In any other form of storage medium well known in field.
Data transfer control method provided herein is described in detail with system above.It is used herein
The principle and implementation of this application are described for specific case, and the above embodiments are only used to help understand originally
The method and its core concept of application.It should be pointed out that for those skilled in the art, not departing from this Shen
Please under the premise of principle, can also to the application, some improvement and modification can also be carried out, these improvement and modification also fall into the application power
The protection scope that benefit requires.
Claims (8)
1. a kind of data transfer control method characterized by comprising
It receives the order of the main transmission of SD and the order is sent to CPU, so that the CPU is based on the order and configures SD master control
Device processed；
When the order is writes data command, receives the data of the main transmission of the SD and the data are sent to the SD master
Controller, with by the SD master controller by the data be written SD from；
When the order is reads data command, the data that the received SD master controller is sent are read in into the SD master.
2. data transfer control method according to claim 1, which is characterized in that described when the order is ordered to write data
When enabling, receives the data of the main transmission of the SD and the data is sent to the SD master controller, comprising:
If the order to write data command and transmission mode is direct mode operation, receives data of the main transmission of the SD and direct
The data are sent to SD master controller；
If the order is writes data command and transmission mode is encryption mode, the data for receiving the main transmission of the SD will be described
Data are sent to the SD master controller by SRAM and DMA encryption and decryption equipment.
3. data transfer control method according to claim 1, which is characterized in that described when the order is ordered to read data
When enabling, the data that the received SD master controller is sent are read in into the SD master, comprising:
If the order is reading data command and transmission mode is direct mode operation, directly receive what the SD master controller was sent
Data, and the data are read in into the SD master；
If the order is reading data command and transmission mode is encryption mode, the SD master controller is received described in
The data that SRAM and the DMA encryption and decryption equipment are sent, and the data are read in into the SD master.
4. data transfer control method according to claim 1, which is characterized in that further include:
Judge whether to receive and cease and desist order；
It ceases and desist order if receiving, terminates data read-write operation.
5. a kind of data transfer control system characterized by comprising
SD is from controller, SD master controller and CPU；
The SD is used to receive the order of the main transmission of SD from controller and the order is sent to CPU, so that the CPU is based on
The order configures SD master controller；When the order is writes data command, the data of the main transmission of the SD are received and by institute
State data and be sent to the SD master controller, with by the SD master controller by the data be written SD from；When the order
When to read data command, the data that the received SD master controller is sent are read in into the SD master.
6. data transfer control system according to claim 5, which is characterized in that if the SD is specifically used for from controller
The order to write data command and transmission mode is direct mode operation, then receive the data of the main transmission of the SD and directly will described in
Data are sent to SD master controller；If the order receives the SD to write data command and transmission mode is encryption mode
The data are sent to the SD master controller by SRAM and DMA encryption and decryption equipment by the data of main transmission.
7. data transfer control system according to claim 5, which is characterized in that if the SD is specifically used for from controller
The order is reading data command and transmission mode is direct mode operation, then directly receives the data that the SD master controller is sent,
And the data are read in into the SD master；If the order is reading data command and transmission mode is encryption mode, institute is received
The data that SD master controller is sent by the SRAM and the DMA encryption and decryption equipment are stated, and the data are read in into the SD
It is main.
8. data transfer control system according to claim 5, which is characterized in that the SD master controller is also used to judge
Whether receive and ceases and desist order；It ceases and desist order if receiving, terminates data read-write operation.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910779842.4A CN110489359B (en) | 2019-08-22 | 2019-08-22 | Data transmission control method and system |
| NL2026311A NL2026311B1 (en) | 2019-08-22 | 2020-08-20 | Control method and control system for data transmission |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910779842.4A CN110489359B (en) | 2019-08-22 | 2019-08-22 | Data transmission control method and system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110489359A true CN110489359A (en) | 2019-11-22 |
| CN110489359B CN110489359B (en) | 2021-05-14 |
Family
ID=68552823
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910779842.4A Active CN110489359B (en) | 2019-08-22 | 2019-08-22 | Data transmission control method and system |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN110489359B (en) |
| NL (1) | NL2026311B1 (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01318140A (en) * | 1988-06-20 | 1989-12-22 | Canon Inc | Multiprocessor system |
| CN101883446A (en) * | 2010-06-28 | 2010-11-10 | 华为终端有限公司 | Wireless internet equipment, secure digital (SD) control chip and data communication method |
| CN202523087U (en) * | 2012-04-11 | 2012-11-07 | 西北农林科技大学 | Radio frequency identification (RFID)-based self-service voice system |
| CN104063345A (en) * | 2013-03-21 | 2014-09-24 | 深圳市振华微电子有限公司 | SATA (serial advanced technology attachment) bridge device |
| DE102014212961A1 (en) * | 2013-07-16 | 2015-01-22 | Ford Global Technologies, Llc | Controller timing system and method |
| CN107025203A (en) * | 2017-03-31 | 2017-08-08 | 新华三技术有限公司 | First board, the second board and a kind of equipment |
| CN107066871A (en) * | 2015-12-04 | 2017-08-18 | 佳能株式会社 | Functional device and control device |
| WO2018116314A1 (en) * | 2016-12-21 | 2018-06-28 | Centre For Development Of Telematics (C-Dot) | A method and a mirrored serial interface (msi) for transferring data |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100365607C (en) * | 2004-12-31 | 2008-01-30 | 北京中星微电子有限公司 | Apparatus and method for controlling SD card interface |
| US8301822B2 (en) * | 2009-09-23 | 2012-10-30 | Sandisk Il Ltd. | Multi-protocol storage device bridge |
| CN109447225B (en) * | 2018-11-27 | 2024-06-04 | 公安部第一研究所 | High-speed safe encryption Micro SD card |
-
2019
- 2019-08-22 CN CN201910779842.4A patent/CN110489359B/en active Active
-
2020
- 2020-08-20 NL NL2026311A patent/NL2026311B1/en active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01318140A (en) * | 1988-06-20 | 1989-12-22 | Canon Inc | Multiprocessor system |
| CN101883446A (en) * | 2010-06-28 | 2010-11-10 | 华为终端有限公司 | Wireless internet equipment, secure digital (SD) control chip and data communication method |
| CN202523087U (en) * | 2012-04-11 | 2012-11-07 | 西北农林科技大学 | Radio frequency identification (RFID)-based self-service voice system |
| CN104063345A (en) * | 2013-03-21 | 2014-09-24 | 深圳市振华微电子有限公司 | SATA (serial advanced technology attachment) bridge device |
| DE102014212961A1 (en) * | 2013-07-16 | 2015-01-22 | Ford Global Technologies, Llc | Controller timing system and method |
| CN107066871A (en) * | 2015-12-04 | 2017-08-18 | 佳能株式会社 | Functional device and control device |
| WO2018116314A1 (en) * | 2016-12-21 | 2018-06-28 | Centre For Development Of Telematics (C-Dot) | A method and a mirrored serial interface (msi) for transferring data |
| CN107025203A (en) * | 2017-03-31 | 2017-08-08 | 新华三技术有限公司 | First board, the second board and a kind of equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| NL2026311B1 (en) | 2021-09-23 |
| CN110489359B (en) | 2021-05-14 |
| NL2026311A (en) | 2021-04-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11144465B2 (en) | Data access method and apparatus | |
| US8713287B2 (en) | Off-loading of processing from a processor blade to storage blades based on processing activity, availability of cache, and other status indicators | |
| KR101051703B1 (en) | Integrated circuit card and integrated circuit card system with suspend / reset function | |
| WO2010010686A1 (en) | Communication system, communication device, and communication method | |
| CN107092835B (en) | Computer data encryption device and method for virtual storage disk | |
| CN104714918A (en) | Method for receiving and buffering high-speed FC bus data in host computer environment | |
| CN115617718A (en) | Read-write order-preserving method based on AXI bus and SoC system | |
| JP6508912B2 (en) | Storage system, storage apparatus, and non-signal analysis method of storage system | |
| CN111722827B (en) | Efficient DDR access method | |
| JP2010176582A (en) | Ic chip, ic card, issuing device, issuing method and issuing system | |
| KR100843199B1 (en) | High speed IDE interface device and method for the same | |
| CN110489359A (en) | A kind of data transfer control method and system | |
| US7353298B2 (en) | Data transfer processing method | |
| US20100106869A1 (en) | USB Storage Device and Interface Circuit Thereof | |
| US20080162479A1 (en) | Memory card system and method for transmitting background information thereof | |
| KR101109600B1 (en) | Method for transmitting data using direct memory access control and apparatus therefor | |
| US9965183B2 (en) | Method for processing data in storage device and storage device | |
| KR101137297B1 (en) | Mobile storage control method | |
| US8635404B2 (en) | Data transfer systems with power management | |
| US20140325242A1 (en) | Encrypt data of storage device | |
| CN117971548B (en) | Communication link control method and device, electronic equipment and storage medium | |
| JP2008118211A (en) | Device and method for transferring data | |
| JP7363344B2 (en) | Memory control device and control method | |
| CN109039392B (en) | Bluetooth device | |
| JPWO2021075154A1 (en) | Data transfer system and system host |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |