NL2026311B1 - Control method and control system for data transmission - Google Patents

Control method and control system for data transmission Download PDF

Info

Publication number
NL2026311B1
NL2026311B1 NL2026311A NL2026311A NL2026311B1 NL 2026311 B1 NL2026311 B1 NL 2026311B1 NL 2026311 A NL2026311 A NL 2026311A NL 2026311 A NL2026311 A NL 2026311A NL 2026311 B1 NL2026311 B1 NL 2026311B1
Authority
NL
Netherlands
Prior art keywords
data
command
host
controller
host controller
Prior art date
Application number
NL2026311A
Other languages
Dutch (nl)
Other versions
NL2026311A (en
Inventor
Kuang Qihe
Zheng Jiang
Yin Ping
Wang Zongbao
Xiao Zuonan
Original Assignee
Cstarcore Tech Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cstarcore Tech Co Ltd filed Critical Cstarcore Tech Co Ltd
Publication of NL2026311A publication Critical patent/NL2026311A/en
Application granted granted Critical
Publication of NL2026311B1 publication Critical patent/NL2026311B1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Communication Control (AREA)
  • Bus Control (AREA)
  • Storage Device Security (AREA)

Abstract

Disclosed is a control method for data transmission that includes receiving a command sent by an SD host and sending the command to a CPU, and the CPU configuring an SD host controller based on the command; receiving data sent by the SD host and sending the data to the SD host controller When the command is a write command, and the SD host controller writing the data to an SD slave; and receiving data sent by the SD host controller and sending the data to the SD host When the command is a read command. The control method for data transmission realize data transmission by virtue of the cooperation of the SD slave controller and the SD host controller in the system on chip, Which can effectively improve the data transmission rate. A control system for data transmission is also disclosed that also has the above technical effects.

Description

CONTROL METHOD AND CONTROL SYSTEM FOR DATA TRANSMISSION
TECHNICAL FIELD The disclosure relates to the field of computer technology, in particular to a control method and a control system for data transmission.
BACKGROUND At present, the data transmission method is a single data block transmission realized by CPU control, which results in a slow data transmission. In order to improve the data transmission rate, the system needs to work at a higher frequency, which will lead to greater power consumption. In addition, when the CPU handles a lot of tasks, its processing efficiency will decrease, thereby affecting the reliability of the system. Therefore, how to increase the data transmission rate has become an urgent technical problem to be solved by those skilled in the art.
SUMMARY The present disclosure is to provide a control method and a control system for data transmission that can effectively improve a data transmission rate.
To solve the above problem, a control method for data transmission is provided that includes receiving a command sent by an SD host and sending the command to a CPU, and the CPU configuring an SD host controller based on the command; receiving data sent by the SD host and sending the data to the SD host controller when the command is a write command, and the SD host controller writing the data to an SD slave; and receiving data sent by the SD host controller and sending the data to the SD host when the command is a read command.
Optionally, the step of receiving data sent by the SD host and sending the data to the SD host controller when the command is a write command includes receiving the data sent by the SD host and sending the data directly to the SD host controller, if the command is a write command and a transmission mode is a pass-through mode; and receiving the data sent by the SD host and sending the data to the SD host controller through a SRAM and a DMA encryption and decryption device, if the command is a write command and the transmission mode is an encryption mode. Optionally, the step of receiving data sent by the SD host controller and sending the data to the SD host when the command is a read command includes receiving the data sent by the SD host controller directly and sending the data to the SD host, if the command is a read command and a transmission mode is a pass-through mode; and receiving the data sent by the SD host controller through a SRAM and a DMA encryption and decryption device and sending the data to the SD host, if the command is a read command and the transmission mode is an encryption mode.
Optionally, the method further includes determining whether a stop command is received and ending read and write operations if the stop command is received.
To solve the above problem, a control system for data transmission is also provided that includes an SD slave controller, an SD host controller and a CPU. The SD slave controller is configured to receive a command sent by an SD host and send the command to the CPU. The CPU configures the SD host controller based on the command. The SD slave controller is configured to receive data sent by the SD host and send the data to the SD host controller when the command is a write command. The SD host controller writes the data to an SD slave. The SD slave controller is configured to receive data sent by the SD host controller and send the data to the SD host when the command is a read command.
Optionally, the SD slave controller is configured to receive the data sent by the SD host and send the data directly to the SD host controller, if the command is a write command and a transmission mode is a pass-through mode, and configured to receive the data sent by the SD host and send the data to the SD host controller through a SRAM and a DMA encryption and decryption device, if the command is a write command and the transmission mode is an encryption mode.
Optionally, the SD slave controller is configured to receive the data sent by the SD host controller directly and send the data to the SD host, if the command is a read command and a transmission mode is a pass-through mode, and configured to receive the data sent by the SD host controller through a SRAM and a DMA encryption and decryption device and send the data to the SD host, if the command is a read command and the transmission mode is an encryption mode.
Optionally, the SD host controller is further configured to determine whether a stop command is received, and if received, end data read and write operations.
The control method for data transmission provided by the present disclosure includes receiving a command sent by an SD host and sending the command to a CPU, and the CPU configuring an SD host controller based on the command; receiving data sent by the SD host and sending the data to the SD host controller when the command is a write command, and the SD host controller writing the data to an SD slave; and receiving data sent by the SD host controller and sending the data to the SD host when the command is a read command. It can be appreciated that, according to the control method for data transmission provided by the disclosure, when writing data, the SD slave controller receives data sent by the SD host and sends the data to the SD host controller, and the SD host controller further writes data to the SD slave. When reading data, the SD slave controller receives data sent by the SD host controller and sends the data to the SD host. The control method for data transmission realize data transmission by virtue of the cooperation of the SD slave controller and the SD host controller in the system on chip, which can effectively improve the data transmission rate. The control system for data transmission provided by the disclosure also has the above technical effects.
BRIEF DESCRIPTION OF THE DRAWINGS To more clearly describe the technical solutions in the embodiments of the present disclosure, the drawings that are required in the description of the prior art and the embodiments will be briefly described. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and a person skilled in the art can further obtain other drawings according to these drawings without inventive effort. FIG. 1 is a schematic flowchart of a control method for data transmission control method according to an embodiment of the disclosure. FIG. 2 is a schematic diagram of a control system for data transmission control method according to an embodiment of the disclosure.
DETAILED DESCRIPTION OF THE EMBODIMENTS The disclosure is mainly to provide a control method and a control system for data transmission, which can effectively improve a data transmission rate.
Technical solutions of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. Apparently, the embodiments described are some, rather than all, of embodiments of the present disclosure. All other embodiments obtainable by a person skilled in the art on the basis of the embodiments in the present disclosure shall fall within the scope of the present disclosure.
FIG. 1 is a schematic flowchart of a control method for data transmission according to an embodiment of the present disclosure.
Referring to FIG. 1, the control method for data transmission inclades: Step S101: receiving a command sent by an SD host and sending the command to a CPU, and the CPU configuring an SD host controller based on the command; Specifically, after the CPU enables an SD slave controller and the SD host controller, the SD slave controller and the SD host controller enter into a ready state for transmission.
When the SD slave controller in the ready state for transmission receives the command sent by the SD host, the SD slave controller informs the CPU of the command, so that the CPU configures the SD host controller.
Specifically, when the command is a write command, the CPU configures the data address of the SD host controller to be a buffer area of the SD slave controller, so that the SD host controller sends a multiple data block write command to the SD slave.
When the command is a read command, the CPU configures the destination address of the SD host controller to be the SD slave controller, so that the SD host controller sends a multiple data block read command to the SD slave.
Step S102: receiving data sent by the SD host and sending the data to the SD host controller, and the SD host controller writing the data to an SD slave when the command is a write command; Specifically, upon the configuration of the SD host controller by the CPU, the SD slave controller receives data sent by the SD host and further sends the data to the SD host controller, and the SD host controller writes the data to the SD slave when the command sent by the SD host is a write command.
In a specific embodiment, when the command is a write command, the step of receiving data sent by the SD host and sending the data to the SD host controller may include: receiving the data sent by the SD host and sending the data directly to the SD host controller if the command is a write command and the transmission mode is a pass-through mode, and receiving the data sent by the SD host and sending the data to the SD host controller through a SRAM (Static Random Access Memory) and a DMA (Direct Memory Access) encryption and decryption device if the command is a write command and the transmission mode is encrypted mode.
Specifically, in this embodiment, the control methods for data transmission differ for different transmission modes when writing data.
If the transmission mode is the pass-through mode, the SD slave controller receives the data sent by the SD host and directly sends the data to the SD host controller, so that the SD host controller further writes the data to the SD slave. If the transmission mode is encryption and decryption mode, the data sent by the SD host is received and sent to the SD host controller through the SRAM and the DMA encryption and decryption device.
5 Specifically, the SD slave controller receives the data sent by the SD host and stores the data in the built-in buffer area, and sends a request to the DMA encryption and decryption device according to the state of the buffer area to write the data to an address space in the SRAM through the DMA encryption and decryption device. The SD host controller waits for a batch of data in the SRAM to be ready and sends it to the SD slave. At the same time, the SD slave controller can receive the next batch of data sent by the SD host, and write the data to another address space in the SRAM through the DMA encryption and decryption device. In this way, several address spaces in the SRAM receive data in turn, and the SD host controller writes the data in the address spaces of the received data to the SD slave.
Step S103: receiving data sent by the SD host controller and sending the data to the SD host when the command is a read command.
Specifically, upon the configuration of the SD host controller by the CPU, when the command sent by the SD host is a read command, the SD slave controller receives the data sent by the SD host controller which is read from the SD slave to the SD host controller, and send the data to the SD host.
In a specific embodiment, the step of receiving data sent by the SD host controller and sending the data to the SD host when the command is a read command may include: receiving the data sent by the SD host controller directly and sending the data to the SD host, if the command is a read command and a transmission mode is a pass-through mode, and receiving the data sent by the SD host controller through a SRAM and a DMA encryption and decryption device and sending the data to the SD host, if the command is a read command and the transmission mode is an encryption mode.
Specifically, for different transmission modes, this embodiment provides two control methods for data transmission when reading data, If the transmission mode is pass-through mode, the SD slave controller directly receives the data from the SD host sent by the SD host controller. That is, the SD host controller and the SD slave controller perform data transmission directly, and further read the received data to the SD host. If the transmission mode is the encryption and decryption mode, the SD slave controller receives data from SD slave sent by the SD host controller through the
SRAM and the DMA encryption and decryption device. Specifically, the SD host controller receives the data from the SD slave and writes the received batch of data to an address space in SRAM. After the batch of data is written to the SRAM, the DMA encryption and decryption device further writes the data in SRAM to the built-in buffer area of the SD slave controller constantly, and then the SD slave controller sends the data to the SD host. Further, the method may further include: the SD slave controller determining whether a stop command is received, and if the stop command is received, ending read and write operations. Specifically, the SD slave controller can also determine in real time whether a stop command sent by the SD host is received during the read operation or write operation described in the above embodiment, and if received, the stop command is also sent to the CPU, so that the CPU configures the SD host controller to send a stop command to the SD slave to end the current read operation or write operation.
In summary, according to the control method for data transmission provided in the disclosure, when writing data, the SD slave controller receives data sent by the SD host and sends the data to the SD host controller, and SD host controller further writes the data to the SD slave. When reading the data, the SD slave controller receives the data sent by the SD host controller and sends the data to the SD host. The control method for data transmission realize data transmission by virtue of the cooperation of the SD slave controller and the SD host controller in the system on chip, which can effectively improve the data transmission rate.
The present disclosure also provides a control system for data transmission. The system described below can be cross-referenced with the method described above. Referring to FIG. 2, the control system for data transmission includes an SD slave controller, an SD host controller and a CPU. The SD slave controller is configured to receive a command sent by the SD host and send the command to the CPU, so that the CPU configures the SD host controller based on the command. When the command is a write command, the data sent by the SD host is received and sent to the SD host controller, so that the SD host controller writes data to an SD slave. When the command is a read command, the received data sent by the SD host controller is read to the SD host.
Based on the above embodiment, as a specific implementation, the SD slave controller is specifically configured to receive the data sent by the SD host and send the data directly to the SD host controller, if the command is a write command and a transmission mode is a pass-through mode, and receive the data sent by the SD host and send the data to the SD host controller through a SRAM and a DMA encryption and decryption device, if the command is a write command and the transmission mode is an encryption mode. Based on the above embodiment, as a specific implementation, the SD slave controller is specifically configured to receive the data sent by the SD host controller directly and send the data to the SD host, if the command is a read command and a transmission mode is a pass-through mode, and receive the data sent by the SD host controller through a SRAM and a DMA encryption and decryption device and send the data to the SD host, if the command is a read command and the transmission mode is an encryption mode.
Based on the above embodiment, as a specific implementation, the SD host controller is further configured to determine whether a stop command is received, and if received, end data read and write operations.
According to the control system for data transmission provided by the disclosure, when writing data, the SD slave controller receives the data sent by the SD host and sends the data to the SD host controller, so that the SD host controller further writes data to the SD slave. When reading data, the SD slave controller receives the data sent by the SD host controller and sends the data to the SD host. The control method for data transmission realize data transmission by virtue of the cooperation of the SD slave controller and the SD host controller in the system on chip, which can effectively improve the data transmission rate.
Each embodiment in the specification is described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same and similar modules between the embodiments may refer to each other.
Those skilled in the art will appreciate that, the units and steps of the algorithms described in the embodiments disclosed herein can be implemented in electronic hardware, computer sof{ware, or a combination thereof. A general description of components and steps of the embodiments has been provided above in terms of their functionalities in order to clearly illustrate the interchangeability between hardware and software. Whether the functionalities are to be implemented in hardware or software depends on specific applications and design constramts of the technical solution. Different methods can be employed by those skilled in the art for any specific application so as to implement the described functionalities, and such implementation should not be considered as beyond the scope of the present disclosure.
The methods and the steps of the algorithms described in the embodiments disclosed herein can be implemented directly in hardware, in software modules executed by a processor, or a combination thereof.
The software modules can be provided in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a register, a hard drive, a
CD-ROM, or any other forms of storage media known in the art.
Descriptions of a control method and a control system for data transmission according to the present discourse are provided in detail.
The principle and implementation of the disclosure are illustrated herein by way of examples merely for the purpose of facilitating an understanding of the method of the disclosure and the key concept thereof. it should be noted that, for an ordinary person skilled in the art, variations and modifications can be made to the present disclosure in accordance with the spirit of the disclosure.
All these variations and modifications fall into the scope of the disclosure.

Claims (8)

ConclusiesConclusions 1. Een regelwerkwijze voor gegevensverzending, omvattende: het ontvangen van een door een SD host verzonden opdracht en het verzenden van de opdracht naar een CPU, en waarbij de CPU een SD hostregelinrichting configureert op basis van de opdracht; het ontvangen van door de SD host verzonden gegevens en het verzenden van de gegevens naar de SD hostregelinrichting wanneer de opdracht een schrijfopdracht is, en waarbij de SD hostregelinrichting de gegevens schrijft naar een SD slaaf; en het ontvangen van door de SD hostregelinrichting verzonden gegevens en het verzenden van de gegevens naar de SD host wanneer de opdracht een leesopdracht is.A data transmission control method comprising: receiving a command sent from an SD host and sending the command to a CPU, and wherein the CPU configures an SD host controller based on the command; receiving data sent from the SD host and sending the data to the SD host controller when the command is a write command, and wherein the SD host controller writes the data to an SD slave; and receiving data sent from the SD host controller and sending the data to the SD host when the command is a read command. 2. De regelwerkwijze voor gegevensverzending volgens conclusie 1, waarbij de stap van het ontvangen van door de SD host verzonden gegevens en het verzenden van de gegevens naar de SD hostregelinrichting wanneer de opdracht een schrijfopdracht is, omvat: het ontvangen van de door de SD host verzonden gegevens en het rechtstreeks naar de SD hostregelinrichting verzenden van de gegevens als de opdracht een schrijfopdracht is en een verzendingsmodus een doorloopmodus is; en het ontvangen van de door de SD host verzonden gegevens en het verzenden van de gegevens naar de SD hostregelinrichting via een SRAM en een DMA coderings- en decoderingsinrichting, als de opdracht een schrijfopdracht is en de verzendingsmodus een coderingsmodas is.The data transmission control method according to claim 1, wherein the step of receiving data sent from the SD host and sending the data to the SD host controller when the command is a write command comprises: receiving the data sent by the SD host transmitted data and transmitting the data directly to the SD host controller if the command is a write command and a transmission mode is a traverse mode; and receiving the data transmitted from the SD host and transmitting the data to the SD host controller via an SRAM and a DMA encoding and decoding device, if the command is a write command and the transmission mode is an encoding mode. 3. De regelwerkwijze voor gegevensverzending volgens conclusie |, waarbij de stap van het ontvangen van door de SD hostregelinrichting verzonden gegevens en het verzenden van de gegevens naar de SD host wanneer de opdracht een leesopdracht is, omvat: het rechtstreeks ontvangen van de door de SD hostregelinrichting verzonden gegevens en het naar de SD host verzenden van de gegevens, als de opdracht een leesopdracht is en een verzendingsmodus een doorloopmodus is; en het ontvangen van de door de SD hostregelinrichting verzonden gegevens via een SRAM en een DMA coderings- en decoderingsinrichting, en het verzenden van de gegevens naar de SD host, als de opdracht een leesopdracht is en de verzendingsmodus een coderingsmodus is.The data transmission control method according to claim |, wherein the step of receiving data sent from the SD host controller and sending the data to the SD host when the command is a read command comprises: directly receiving the data sent by the SD host controller transmitting data and transmitting the data to the SD host, if the command is a read command and a transmit mode is a traverse mode; and receiving the data sent from the SD host controller through a SRAM and a DMA encoding and decoding device, and transmitting the data to the SD host, if the command is a read command and the transmission mode is an encoding mode. 4. De regelwerkwijze voor gegevensverzending volgens conclusie 1, verder omvattende: het bepalen of een stopopdracht ontvangen is; en het beëindigen van lees- en schrijfactiviteiten als de stopopdracht ontvangen is.The data transmission control method according to claim 1, further comprising: determining whether a stop command has been received; and terminating read and write activities when the stop command is received. 5. Een regelsysteem voor gegevensverzending, omvattende een SD slaafregelinrichting, een SD hostregelinrichting en een CPU, waarbij de SD slaafregelinrichting mgericht is voor het ontvangen van een door een SD host verzonden opdracht en het verzenden van de opdracht naar de CPU, waarbij de CPU de SD hostregelinrichting configureert op basis van de opdracht; waarbij de SD slaafregelinrichting ingericht is voor het ontvangen van door de SD host verzonden gegevens en het naar de SD hostregelinrichting verzenden van de gegevens wanneer de opdracht een schrijfopdracht is, waarbij de SD hostregelinrichting de gegevens naar een SD slaaf schrijft; en waarbij de SD slaafregelinrichting ingericht is voor het ontvangen van door de SD hostregelinrichting verzonden gegevens en het verzenden van de gegevens naar de SD host wanneer de opdracht een leesopdracht is.A data transmission control system comprising an SD slave controller, an SD host controller and a CPU, the SD slave controller adapted to receive a command sent from an SD host and transmit the command to the CPU, the CPU the SD host controller configures based on the command; wherein the SD slave controller is configured to receive data sent from the SD host and send the data to the SD host controller when the command is a write command, the SD host controller writes the data to an SD slave; and wherein the SD slave controller is configured to receive data sent from the SD host controller and send the data to the SD host when the command is a read command. 6. Het regelsysteem voor gegevensverzending volgens conclusie 5, waarbij de SD slaafregelinrichting ingericht is voor het ontvangen van de door de SD host verzonden gegevens en het rechtstreeks naar de SD hostregelinrichting verzenden van de gegevens, als de opdracht een schrijfopdracht is en een verzendingsmodus een doorloopmodus is; en waarbij de SD slaafregelinrichting ingericht is voor het ontvangen van de door de SD host verzonden gegevens en het verzenden van de gegevens naar de SD hostregelinrichting via een SRAM en een DMA coderings- en decoderingsinrichting, als de opdracht een schrijfopdracht is en de verzendingsmodus een coderingsmodus is.The data transmission control system according to claim 5, wherein the SD slave controller is arranged to receive the data transmitted from the SD host and transmit the data directly to the SD host controller, if the command is a write command and a transmission mode is a walk mode. is; and wherein the SD slave controller is configured to receive the data transmitted from the SD host and transmit the data to the SD host controller via an SRAM and a DMA encoding and decoding device, if the command is a write command and the transmission mode is an encoding mode is. 7. Het regelsysteem voor gegevensverzending volgens conclusie 5, waarbij de SD slaafregelinrichting ingericht is voor het rechtstreeks ontvangen van de door de SD hostregelinrichting verzonden gegevens en het verzenden van de gegevens naar de SD host, als de opdracht een leesopdracht is en een verzendingsmodus een doorioopmodus is; en waarbij de SD slaafregelinrichting ingericht is om de door de SD hostregelinrichting verzonden gegevens via een SRAM en een DMA coderings- en decoderingsinrichting te ontvangen en de gegevens naar de SD host te verzenden, als de opdracht een leesopdracht is en de verzendingsmodus een coderingsmodus is.The data transmission control system according to claim 5, wherein the SD slave controller is arranged to directly receive the data transmitted from the SD host controller and transmit the data to the SD host, if the command is a read command and a transmission mode is a transit mode. is; and wherein the SD slave controller is configured to receive the data sent by the SD host controller through a SRAM and a DMA encoding and decoding device and send the data to the SD host if the command is a read command and the transmission mode is an encoding mode. 8. Het regelsysteem voor gegevensverzending volgens conclasie 5, waarbij de SD hostregelinrichting verder is ingericht om te bepalen of een stopopdracht ontvangen is, en indien ontvangen, gegevenslees- en schrijfactiviteiten te beëindigen.The data transmission control system according to claim 5, wherein the SD host control device is further arranged to determine whether a stop command has been received, and if received, to terminate data read and write operations.
NL2026311A 2019-08-22 2020-08-20 Control method and control system for data transmission NL2026311B1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910779842.4A CN110489359B (en) 2019-08-22 2019-08-22 Data transmission control method and system

Publications (2)

Publication Number Publication Date
NL2026311A NL2026311A (en) 2021-04-06
NL2026311B1 true NL2026311B1 (en) 2021-09-23

Family

ID=68552823

Family Applications (1)

Application Number Title Priority Date Filing Date
NL2026311A NL2026311B1 (en) 2019-08-22 2020-08-20 Control method and control system for data transmission

Country Status (2)

Country Link
CN (1) CN110489359B (en)
NL (1) NL2026311B1 (en)

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01318140A (en) * 1988-06-20 1989-12-22 Canon Inc Multiprocessor system
CN100365607C (en) * 2004-12-31 2008-01-30 北京中星微电子有限公司 Apparatus and method for controlling SD card interface
US8301822B2 (en) * 2009-09-23 2012-10-30 Sandisk Il Ltd. Multi-protocol storage device bridge
CN101883446B (en) * 2010-06-28 2014-03-26 华为终端有限公司 Secure digital (SD) control chip and data communication method
CN202523087U (en) * 2012-04-11 2012-11-07 西北农林科技大学 Radio frequency identification (RFID)-based self-service voice system
CN104063345A (en) * 2013-03-21 2014-09-24 深圳市振华微电子有限公司 SATA (serial advanced technology attachment) bridge device
US9766648B2 (en) * 2013-07-16 2017-09-19 Ford Global Technologies, Llc Controller system coordinated using a timing signal and method of controller coordination using a timing signal
JP6719894B2 (en) * 2015-12-04 2020-07-08 キヤノン株式会社 Functional device, control device
WO2018116314A1 (en) * 2016-12-21 2018-06-28 Centre For Development Of Telematics (C-Dot) A method and a mirrored serial interface (msi) for transferring data
CN107025203B (en) * 2017-03-31 2020-09-25 新华三技术有限公司 First board card, second board card and equipment

Also Published As

Publication number Publication date
NL2026311A (en) 2021-04-06
CN110489359B (en) 2021-05-14
CN110489359A (en) 2019-11-22

Similar Documents

Publication Publication Date Title
US20210124692A1 (en) Direct host access to storage device memory space
US11720283B2 (en) Coherent access to persistent memory region range
CN111061657B (en) System and method for supporting chassis level keep-alive in NVMe-oF based system
TWI699646B (en) Memory device, memory addressing method, and article comprising non-transitory storage medium
WO2018188084A1 (en) Data access method and device
US20190196972A1 (en) Managing flash memory read operations
US20140259028A1 (en) Mechanism for establishing temporary background communication between applications
TW201734804A (en) SSD, method and article for user configurable passive background operation
WO2017148292A1 (en) Cascade plate, and system and method for ssd remote sharing access
US10671141B2 (en) Storage device and method of controlling link state thereof
CN107590099A (en) A kind of more main frames access method, expanding unit and the storage medium of slave
WO2019190682A1 (en) System, apparatus and method for handshaking protocol for low power state transitions
KR20140142793A (en) Operating method for memory controller controlling nonvolatile memory device and nonvolatile memory system
US20160092377A1 (en) Method for fast access to a shared memory
US10585822B2 (en) Operation method of host system including storage device and operation method of storage device controller
CN103441948A (en) Data access method, network card and storage system
US10635322B2 (en) Storage device, computing device including the same, and operation method of the computing device
US8639840B2 (en) Processing unit, chip, computing device and method for accelerating data transmission
KR101317760B1 (en) Dynamic random access memory for a semiconductor storage device-based system
WO2018040622A1 (en) Method and apparatus for information processing
US10168934B2 (en) Method and device for monitoring data integrity in shared memory environment
US9377966B2 (en) Method and apparatus for efficiently processing storage commands
WO2018000765A1 (en) Co-processor, data reading method, processor system and storage medium
NL2026311B1 (en) Control method and control system for data transmission
US10949095B2 (en) Method, network adapters and computer program product using network adapter memory to service data requests