CN110473919A - Semiconductor structure, high electron mobility transistor and semiconductor structure manufacturing method - Google Patents

Abstract

The present invention provides a semiconductor structure, a high electron mobility transistor and a method for manufacturing a semiconductor structure, wherein the semiconductor structure comprises a substrate, a flowable dielectric material and a GaN-based semiconductor layer. The substrate has a pit exposed from the upper surface of the substrate, the flowable dielectric material fills the pit, and the GaN-based semiconductor layer is disposed on the substrate and the flowable dielectric material. The present invention can improve the manufacturing yield of semiconductor devices and reduce process costs.

Description

Semiconductor structure, high electron mobility transistor and semiconductor structure manufacturing method

technical field

The embodiments of the present invention relate to semiconductor manufacturing technology, and in particular to a semiconductor structure with gallium nitride-based semiconductor materials, a high electron mobility transistor, and a method for manufacturing the semiconductor structure.

Background technique

Gallium nitride-based (GaN-based) semiconductor materials have many excellent material properties, such as high heat resistance, wide band-gap, and high electron saturation rate. Therefore, gallium nitride-based semiconductor materials are suitable for high-speed and high-temperature operating environments. In recent years, gallium nitride-based semiconductor materials have been widely used in light emitting diode (light emitting diode, LED) components, high frequency components, such as high electron mobility transistors (high electron mobility transistors, HEMTs) with heterostructures.

With the development of gallium nitride-based semiconductor materials, these semiconductor structures using gallium nitride-based semiconductor materials are used in more severe working environments, such as higher frequency, higher temperature or higher voltage. Therefore, the process conditions of the semiconductor structure having gallium nitride-based semiconductor materials also face many new challenges.

Contents of the invention

Some embodiments of the present invention provide a semiconductor structure including a substrate, a flowable dielectric material, and a GaN-based semiconductor layer. The substrate has pits exposed from an upper surface of the substrate, the flowable dielectric material fills the pits, and a gallium nitride-based semiconductor layer is disposed over the substrate and the flowable dielectric material.

Some embodiments of the present invention provide a high electron mobility transistor (HEMT) comprising an aluminum nitride substrate having a plurality of cavities exposed from an upper surface of the aluminum nitride substrate , and the borophosphosilicate glass that fills these craters. The high electron mobility transistor also includes a gallium nitride semiconductor layer disposed on the aluminum nitride substrate and borophosphosilicate glass, a gallium aluminum nitride semiconductor layer disposed on the gallium nitride semiconductor layer, and a gallium nitride semiconductor layer disposed on the A source electrode, a drain electrode, and a gate electrode over the aluminum gallium nitride semiconductor layer.

Some embodiments of the present invention provide a method of fabricating a semiconductor structure, the method comprising providing a substrate having pits exposed from an upper surface of the substrate, forming a flowable dielectric material on the substrate, performing a heat treatment to make the flowable The dielectric material reflows to and fills the pits, a planarization process is performed to remove the portion of the flowable dielectric material outside the pits and expose the upper surface of the substrate, and after the planarization process, between the substrates GaN-based semiconductor layer is formed on it.

The semiconductor structure of the present invention can be applied to various types of semiconductor devices. In order to make the characteristics and advantages of the present invention more obvious and easy to understand, the following specifically lists the embodiments applied to high electron mobility transistors, and cooperates with the accompanying drawings , as detailed below.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained according to these drawings without any creative effort. For clarity of the drawings, various elements in the drawings may not be drawn to scale, wherein:

1A to 1E are schematic cross-sectional views illustrating various stages of forming a base structure according to some embodiments of the present invention.

FIG. 2 is a schematic cross-sectional view showing a high electron mobility transistor formed using the substrate structure of FIG. 1E according to some embodiments of the present invention.

Detailed ways

The following disclosure provides a number of embodiments or examples for implementing different components of the provided semiconductor structures. Specific examples of each component and its configuration are described below to simplify the description of the embodiments of the present invention. Certainly, these are only examples, and are not intended to limit the embodiments of the present invention. For example, if it is mentioned in the description that the first component is formed on the second component, it may include an embodiment in which the first and second components are in direct contact, and may also include an additional component formed between the first and second components , so that they are not in direct contact with the example. In addition, embodiments of the present invention may repeat reference numerals and/or letters in different instances. This repetition is for brevity and clarity rather than to show the relationship between the different embodiments discussed.

Some variations of the embodiment are described below. In the different drawings and described embodiments, similar reference numerals are used to designate similar components. It is understood that additional steps may be provided before, during, and after the method, and that some recited steps may be substituted or deleted in other embodiments of the method.

Embodiments of the present invention provide a semiconductor structure, a high electron mobility transistor (HEMT) and a manufacturing method thereof. Generally, semiconductor devices including GaN-based semiconductor materials are formed on ceramic substrates. Since the ceramic substrate formed by powder metallurgy has pits on the surface of the ceramic substrate, when the ceramic substrate is used in a semiconductor process, the material layer formed on the substrate will be formed in the pits, reducing the manufacturing of semiconductor devices. Yield rate. In order to improve the manufacturing yield of semiconductor devices, an embodiment of the present invention provides a method for manufacturing a semiconductor structure, which includes forming a flowable dielectric material on a substrate, and reflowing the flowable dielectric material to and through heat treatment. The cavity is filled, and then a planarization process is performed on the flowable dielectric material to expose the upper surface of the substrate, so that the substrate can provide a flat surface for subsequent semiconductor processes.

1A to 1E are schematic cross-sectional views illustrating various stages of forming the base structure 100' shown in FIG. 1E according to some embodiments of the present invention. Referring to FIG. 1A , a substrate 102 is provided. The base 102 may be circular, and the diameter P of the base 102 may be 4 inches or more, such as 6 inches, 8 inches or 12 inches, to be suitable for manufacturing equipment in the semiconductor industry.

The substrate 102 essentially has some defects 104 , and the defects 104 include holes 103 in the substrate 102 and pits 105 exposed from the upper surface of the substrate 102 . In some embodiments, the substrate 102 is a ceramic substrate, which is formed by sintering ceramic powder at high temperature through powder metallurgy. For example, the substrate 102 is an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, a sapphire (Sapphire) substrate or the like. During the sintering of the ceramic powders to manufacture the substrate 102, the voids between the ceramic powders are gradually reduced and eliminated. After the ceramic powder is sintered, the voids between the ceramic powder will not completely disappear. Therefore, some defects 104 still remain inside and on the surface of the substrate 102 . In addition, even if the sintered substrate 102 is polished to remove the surface pits 105 , the holes 103 in the substrate 102 will be exposed, and new pits 105 will be formed on the upper surface of the substrate 102 .

In some embodiments, the substrate 102 is used for manufacturing semiconductor devices including GaN-based semiconductor layers, such as light-emitting diodes (light-emitting diodes, LEDs), high-frequency devices or high-voltage devices. The high frequency device or high voltage device may be, for example, a high electron mobility transistor (HEMT), a schottky bipolar diode (SBD), a bipolar junction transistor (BJT), a junction field effect transistor (junction field effect transistor) transistor, JFET), insulated gate bipolar transistor (insulated gate bipolar transistor, IGBT).

Since there are pits 105 on the upper surface of the substrate 102 , the material subsequently grown on the upper surface of the substrate 102 will also grow in the pits 105 . With the miniaturization of the size of the semiconductor device, the pits 105 on the upper surface of the substrate 102 become killer defects of the semiconductor device and reduce the yield rate of the semiconductor device. Therefore, it is necessary to overcome the problem of low manufacturing yield caused by the pits on the upper surface of the substrate.

It should be noted that although the pothole 105 as shown in FIG. 1A has an arc-shaped cross-sectional profile, the shape of the pothole 105 is not limited thereto. In practice, the pothole 105 may have an irregular cross-sectional profile. In the schematic cross-sectional view of FIG. 1A , the potholes 105 may have respective widths W measured in the lateral direction, and respective depths D measured in the longitudinal direction. In the embodiment of the present invention, when the depth D of the pit 105 is greater than the width W thereof, the dimension of the pit 105 can be defined as its depth D. Conversely, when the width W of the pit 105 is greater than the depth D, the dimension of the pothole 105 can be defined as its width W. Generally, the size of the pits 105 may range from about 0.5 microns (μm) to about 15 microns.

Referring to FIG. 1B , a flowable dielectric material 106 is formed on the upper surface of the substrate 102 , and the flowable dielectric material 106 is filled into the cavity 105 and conforms to the contour of the cavity 105 . The flowable dielectric material 106 has a thickness T1 on the upper surface of the substrate 102 . In some embodiments, most of the cavities 105 are not filled by the flowable dielectric material 106 because the size of most of the cavities 105 is larger than the thickness T1 of the flowable dielectric material 106 . Although not shown, flowable dielectric material 106 may fill some of the smaller sized cavities 105 .

In the embodiment of the present invention, the flowable dielectric material 106 formed on the substrate 102 is solid at room temperature, and the flowable dielectric material 106 can be heated through heat treatment to make it have a flowability similar to a liquid state, and Reflow occurs. That is, the flowable dielectric material 106 is a dielectric material that does not have flowability at low temperatures but has flowability at high temperatures. In some embodiments, the flowable dielectric material 106 may be spin-on glass (SOG), borophosphosilicate glass (BPSG), phosphosilicate glass (PSG) ) similar materials or a combination of the foregoing. The flowable dielectric material 106 can be formed by spin-oncoating, chemical vapor deposition (CVD), similar methods, or a combination thereof.

Next, after the flowable dielectric material 106 is formed, a heat treatment 150 is performed on the substrate 102 on which the flowable dielectric material 106 is formed, so that the flowable dielectric material 106 may have fluidity for reflow. As shown in FIG. 1C , the flowable dielectric material reflows into the cavity 105 and fills up the cavity 105 . Usually, the thickness of the deposited dielectric material must be at least greater than the size of the hole to fill the hole. In the embodiment of the present invention, the flowable dielectric material 106 is used, and the flowable dielectric material 106 is reflowed into the pit 105 through the heat treatment 150 to fill the pit 105, so the flowable dielectric material 106 The thickness T1 may be smaller than the size of the dimple 105 . This can greatly reduce the deposition thickness and process time of the dielectric material used to fill the pits, thereby reducing manufacturing costs.

In embodiments where the flowable dielectric material 106 is spin-on-glass (SOG), the temperature of the heat treatment 150 can be in the range of about 300°C to about 500°C, such as about 350°C to about 450°C, and the heat treatment time can be In the range of about 20 minutes to about 60 minutes. When the heat treatment temperature is less than 300°C, spin-on-coated glass (SOG) may not be able to reflow, and when the heat-treatment temperature is greater than 500°C, the fluidity of spin-on-coated glass (SOG) is too high. Cracks may occur between the (SOG) and the substrate 102 , even causing the substrate 102 to break. In an embodiment where the flowable dielectric material 106 is spin-on-glass (SOG), when the thickness T1 of the flowable dielectric material 106 on the upper surface of the substrate 102 is greater than about 0.15 of the size of the pit 105, for example, about In the range of 0.15 to 0.3 of the dimension, the reflowed flowable dielectric material 106 can fill the cavity 105 after the heat treatment 150 .

In embodiments where the flowable dielectric material 106 is borophosphosilicate glass (BPSG), the temperature of the heat treatment 150 may be in the range of about 800°C to about 1000°C, such as about 850°C to about 950°C, and the heat treatment The time may range from about 20 minutes to 60 minutes. When the heat treatment temperature is less than 800°C, borophosphosilicate glass (BPSG) may not be able to reflow, and when the heat treatment temperature is greater than 1000°C, the fluidity of borophosphosilicate glass (BPSG) is too high. After cooling, Cracks may occur between the borophosphosilicate glass (BPSG) and the substrate 102 , even causing the substrate 102 to crack. In an embodiment where the flowable dielectric material 106 is borophosphosilicate glass (BPSG), when the thickness T1 of the flowable dielectric material 106 on the upper surface of the substrate 102 is greater than about 0.3 of the pit size, for example, about In the range of 0.3 to 0.6 of the hole size, and after the heat treatment 150 , the reflowed flowable dielectric material 106 can fill the hole 105 .

After the thermal treatment 150 , a planarization process 160 , such as chemical mechanical polishing (CMP), is performed on the flowable dielectric material 106 . As shown in FIG. 1D , after the planarization process 160 , the portion of the flowable dielectric material 106 outside the hole 105 is removed, so that the upper surface of the substrate 102 is exposed. The upper surface of the remaining portion 106' of the flowable dielectric material 106 in the cavity 105 is substantially coplanar with the upper surface of the substrate 102. In some embodiments, since the substrate 102 has a greater polishing selectivity than the flowable dielectric material 106, the upper surface of the remaining portion 106' of the flowable dielectric material 106 may be slightly lower than the upper surface of the substrate 102 after the planarization process. surface.

After the planarization process 160, the base structure 100 is formed. Compared with the substrate 102 , the base structure 100 has a substantially flat upper surface for forming semiconductor devices thereon.

Notably, after thermal treatment 150, the thermal stability of flowable dielectric material 106 is improved. For example, for spin on glass (SOG) after heat treatment 150, the temperature at which the spin on glass (SOG) undergoes secondary reflow needs to be greater than about 400° C. before the spin on glass (SOG) becomes flowable again. . For example, for borophosphosilicate glass (BPSG) after heat treatment 150°C, the temperature at which borophosphosilicate glass (BPSG) undergoes secondary reflow needs to be greater than about 1100°C for borophosphosilicate glass (BPSG) to will be mobile again. Therefore, when using the base structure 100 in subsequent semiconductor processes, the upper process temperature limit depends on the temperature at which the secondary reflow of the flowable dielectric material 106 (ie, the remaining portion 106') occurs. For example, if the cavity 105 is filled with borophosphosilicate glass (BPSG), the upper temperature limit of the subsequent semiconductor process can reach about 1100°C.

In some embodiments, as shown in FIG. 1E , a capping layer 108 is optionally fully formed on the upper surface of the substrate 102 and the upper surface of the remaining portion 106 ′ of the flowable dielectric material 106 to obtain the base structure 100 ′. .

Capping layer 108 is a high quality film with good thermal stability at high temperatures compared to flowable dielectric material 106 . In some embodiments, the capping layer 108 is a high-quality insulating layer formed by thermal growth, such as silicon oxide made of tetraethoxysilane (TEOS). In some other embodiments, the capping layer 108 is a dielectric layer formed by plasma enhanced chemical vapor deposition (PECVD), such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, similar materials or combinations thereof. The capping layer 108 can provide a higher quality surface for forming semiconductor devices. In addition, if the subsequent semiconductor process uses a process temperature slightly higher than the temperature at which the secondary reflow of the flowable dielectric material 106 occurs, the direct impact of the flowable dielectric material 106 (ie, the remaining portion 106 ′) due to the secondary reflow can be avoided. The semiconductor material formed thereon.

In other embodiments, the capping layer 108 is a diffusion barrier layer, such as titanium, titanium nitride, tantalum nitride, similar materials, or combinations thereof, and can be deposited by physical vapor deposition (PVD), sputtering Sputtering, similar deposition methods, or a combination of the foregoing form the diffusion barrier layer. Capping layer 108 thus prevents atoms from the material of substrate 102 (eg, aluminum from an aluminum nitride substrate) from diffusing into the semiconductor material above.

In an embodiment of the present invention, the base structure 100 or 100' has a planar upper surface for forming devices including GaN-based semiconductor materials thereon. Semiconductor devices containing gallium nitride-based (GaN-based) semiconductor materials can be, for example, light emitting diodes (LEDs), high electron mobility transistors (HEMTs), Schottky diodes (SBDs), dual carrier transistors (BJTs), junction Field Effect Transistors (JFETs), Insulated Gate Bipolar Transistors (IGBTs), or similar devices. Hereinafter, taking a high electron mobility transistor (HEMT) as an example, the formation of a semiconductor device on the base structure 100' in FIG. 1E will be described.

Please refer to FIG. 2 . FIG. 2 is a schematic cross-sectional view showing a high electron mobility transistor formed using the base structure 100' of FIG. 1E according to some embodiments of the present invention.

The breakdown voltage of a high electron mobility transistor (HEMT) mainly depends on the thickness of a gallium nitride (GaN) semiconductor layer as a channel layer. For example, increasing the thickness of the GaN semiconductor layer by 1 μm can increase the breakdown voltage of a high electron mobility transistor (HEMT) by about 100 volts. During the epitaxial growth process for forming the GaN semiconductor layer, it is necessary to use a substrate with high thermal conductivity and high mechanical strength to deposit the GaN semiconductor material thereon, otherwise the substrate may be bent or even cracked. Therefore, compared with the silicon substrate, the aluminum nitride substrate has higher thermal conductivity and higher mechanical strength, so as to form a thicker gallium nitride semiconductor layer on the aluminum nitride substrate. For example, the thickness of the gallium nitride semiconductor layer formed on the surface of the silicon substrate is about 2 to 4 microns. The thickness of the gallium nitride semiconductor layer formed on the surface of the aluminum nitride substrate can reach 5 microns to 15 microns.

Referring to FIG. 2 , the base structure 100' of FIG. 1E is provided. FIG. 2 shows a portion of the base structure 100' of FIG. 1E, wherein the portion of the base structure 100' has some cavities 105 therein, and a high electron mobility transistor 200 is formed on the portion of the base structure 100'. In the embodiment shown in FIG. 2, substrate 102 is an aluminum nitride substrate.

Spin-on-glass (SOG) is not suitable for filling the cavity 105 in this embodiment because some processes for manufacturing high electron mobility transistors may have a temperature higher than 500°C. In addition, borophosphosilicate glass (BPSG) has better reflow properties than phosphosilicate glass (PSG). That is, borophosphosilicate glass (BPSG) can be deposited to a lower thickness and fill the cavity 105 with a shorter heat treatment time and lower heat treatment temperature than PSG. . Thus, in this embodiment, the flowable dielectric material 106 is borophosphosilicate glass (BPSG) with a secondary reflow temperature up to 1100°C.

The material of the capping layer 108 may be silicon oxide formed by oxidation in a furnace using tetraethoxysilane (TEOS). The capping layer 108 covers the upper surface of the substrate 102 and the upper surface of the flowable dielectric material 106 (or remaining portion 106') filling the cavity 105.

Next, a buffer layer 110 is formed on the upper surface of the cap layer 108 , and a gallium nitride semiconductor layer 112 is formed on the buffer layer 110 . The aluminum gallium nitride semiconductor layer 114 is formed on the gallium nitride semiconductor layer 112 . In some embodiments, a seed layer (not shown) may be formed between the capping layer 108 and the buffer layer 110 .

The material of the seed layer can be formed of aluminum nitride (AlN), aluminum oxide (Al ₂ O ₃ ), aluminum gallium nitride (AlGaN), silicon carbide (SiC), aluminum (Al) or a combination of the foregoing, and the crystal The seed layer can be a single or multilayer structure. The seed layer can be formed by epitaxial growth process, such as metal organic chemical vapor deposition (metal organic chemical vapor deposition, MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (molecular beam epitaxy) , MBE), a combination of the foregoing, or similar methods.

The buffer layer 110 can relieve the strain of the gallium nitride semiconductor layer 112 subsequently formed above the buffer layer 110 to prevent defects from forming in the upper gallium nitride semiconductor layer 112. The strain is caused by the relationship between the gallium nitride semiconductor layer 112 and the substrate 102 caused by a mismatch between them. In some embodiments, the material of the buffer layer 110 may be AlN, GaN, AlxGa1 _{- xN} (where 0<x<1), a combination of the foregoing or similar materials. The buffer layer 110 can be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), combinations of the foregoing, or similar methods. Although in the embodiment shown in FIG. 2 , the buffer layer 110 is a single-layer structure, the buffer layer 110 may also be a multi-layer structure. In addition, in some embodiments, the material of the buffer layer 110 is determined by the material of the seed layer and the gas introduced during the epitaxy process.

A two-dimensional electron gas (2DEG) (not shown) is formed on the heterointerface between the GaN semiconductor layer 112 and the AlGaN semiconductor layer 114 . In some embodiments, there is no dopant in the gallium nitride semiconductor layer 112 and the aluminum gallium nitride semiconductor layer 114 . In some other embodiments, the gallium nitride semiconductor layer 112 and the aluminum gallium nitride semiconductor layer 114 may have dopants, such as n-type dopants or p-type dopants. The gallium nitride semiconductor layer 112 and the aluminum gallium nitride semiconductor layer 114 can be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), A combination of the foregoing or similar methods.

In the embodiment shown in FIG. 2 , since the substrate 102 is an aluminum nitride substrate with high thermal conductivity and high mechanical strength, the thickness T2 of the deposited gallium nitride semiconductor layer 112 is about 5 microns to 15 microns.

Next, an isolation structure 116 is formed in the GaN semiconductor layer 112 and the AlGaN semiconductor layer 114 to define the active region 50 . The material of the isolation structure 116 can be a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, similar materials or a combination thereof, and the isolation structure 116 can be formed through an etching process and a deposition process.

Next, a source/drain electrode 118 and a gate electrode 120 interposed between the source/drain electrodes 118 are formed on the AlGaN semiconductor layer 114 in the active region 50 to form a high electron mobility transistor 200 . In some embodiments, the material of the source/drain electrode 118 and the gate electrode 120 may be a conductive material, such as a metal, a metal nitride, or a semiconductor material. Metals can be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper ( Cu), similar materials, combinations of the foregoing, or multiple layers of the foregoing. The semiconductor material can be polycrystalline silicon or polycrystalline germanium. The step of forming the source electrode 118 and the gate electrode 120 may include depositing a conductive material on the AlGaN semiconductor layer 114 and patterning the conductive material to form the source/drain electrode 118 and the gate electrode 120 . The source/drain electrodes 118 and the gate electrodes 120 may be formed in the same process, or may be formed in different processes.

As shown in FIG. 2, since the flowable dielectric material 106 (that is, the remaining portion 106') fills the cavity 105 on the upper surface of the substrate 102, the material layer formed above the substrate 102 will not be formed in the cavity 105, Therefore, the manufacturing yield of the high electron mobility transistor 200 is improved.

In summary, the embodiments of the present invention provide a method for manufacturing a semiconductor structure, which includes forming a flowable dielectric material on a substrate, and reflowing the flowable dielectric material to and filling the cavity through heat treatment. , and then perform a planarization process on the flowable dielectric material to expose the upper surface of the substrate, so that the substrate can provide a flat surface for subsequent semiconductor processes.

In addition, the embodiments of the present invention use heat treatment to reflow the flowable dielectric material into the hole to fill the hole, so that the thickness of the flowable dielectric material can be smaller than the size of the hole. Therefore, the deposition thickness and processing time of the dielectric material for filling the pit can be greatly reduced, thereby reducing the processing cost.

Several embodiments are summarized above so that those skilled in the art can better understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention, so as to achieve the same purpose and/or advantages as the embodiments introduced here. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and they can make various changes without departing from the spirit and scope of the present invention. Alter, replace and replace.

Claims (20)

1. a kind of semiconductor structure characterized by comprising

There is one substrate a pit-hole to be exposed from the upper surface of the substrate；

One flowable dielectric material, fills up the pit-hole；And

One gallium nitride semiconductor layer setting is on the substrate and the flowable dielectric material.

2. semiconductor structure as described in claim 1, which is characterized in that the flowable dielectric material does not cover the upper of the substrate Surface.

3. semiconductor structure as described in claim 1, which is characterized in that further include: a cap rock is arranged in the substrate and the nitrogen Change between gallium based semiconductor layer, and covers the flowable dielectric material.

4. semiconductor structure as claimed in claim 3, which is characterized in that the material of the cap rock is insulating materials.

5. semiconductor structure as described in claim 1, which is characterized in that the substrate be aluminum-nitride-based bottom, silicon carbide substrate or Sapphire substrates.

6. semiconductor structure as described in claim 1, which is characterized in that the flowable dielectric material be spin on glass, Boron phosphorus silicate glass or phosphosilicate glass.

7. semiconductor structure as described in claim 1, which is characterized in that the semiconductor structure further includes that semiconductor device is set Set on the substrate, the semiconductor device include the gallium nitride semiconductor layer, and the semiconductor device be light emitting diode, High electron mobility transistor, Schottky diode, complex carries transistor, junction field effect transistor or insulated gate bipolar transistor Pipe.

8. semiconductor structure as described in claim 1, which is characterized in that the size of the substrate is greater than or equal to 4 inches.

9. a kind of high electron mobility transistor characterized by comprising

There are multiple pit-holes to be exposed from the upper surface at the aluminum-nitride-based bottom at one aluminum-nitride-based bottom；

One boron phosphorus silicate glass fills up the pit-hole；

One gallium nitride semiconductor layers, setting is on the aluminum-nitride-based bottom and the boron phosphorus silicate glass；

One aluminum gallium nitride semiconductor layer is arranged on the gallium nitride semiconductor layers；And

One source electrode, a drain electrode and a gate electrode are arranged in the aluminum gallium nitride semiconductor layer.

10. high electron mobility transistor as claimed in claim 9, which is characterized in that the thickness of the gallium nitride semiconductor layers At 5 microns to 15 microns.

11. a kind of manufacturing method of semiconductor structure characterized by comprising

A substrate is provided, which there is a pit-hole to be exposed from the upper surface of the substrate；

A flowable dielectric material is formed on this substrate；

A heat treatment is executed, the flowable dielectric material is back to and fills up the pit-hole；

A flatening process is executed, part of the flowable dielectric material other than the pit-hole is removed and exposes the upper of the substrate Surface；And

After the flatening process, a gallium nitride semiconductor layer is formed on the substrate.

12. the manufacturing method of semiconductor structure as claimed in claim 11, which is characterized in that before executing the heat treatment, The flowable dielectric material portion fills the pit-hole.

13. the manufacturing method of semiconductor structure as claimed in claim 11, which is characterized in that the substrate be aluminum-nitride-based bottom, Silicon carbide substrate or sapphire substrates.

14. the manufacturing method of semiconductor structure as claimed in claim 11, which is characterized in that the flowable dielectric material is boron Phosphosilicate glass.

15. the manufacturing method of semiconductor structure as claimed in claim 14, which is characterized in that form the flowable dielectric material The step of include: deposit the flowable dielectric material with a thickness of the 0.3 to 0.6 of the pit-hole size.

16. the manufacturing method of semiconductor structure as claimed in claim 14, which is characterized in that the temperature of the heat treatment is 800 DEG C to 1000 DEG C.

17. the manufacturing method of semiconductor structure as claimed in claim 11, which is characterized in that the flowable dielectric material is rotation Turn coated glass.

18. the manufacturing method of semiconductor structure as claimed in claim 17, which is characterized in that form the flowable dielectric material The step of include: deposit the flowable dielectric material with a thickness of the 0.15 to 0.3 of the pit-hole size.

19. the manufacturing method of semiconductor structure as claimed in claim 17, which is characterized in that the temperature of the heat treatment is 300 DEG C to 500 DEG C.

20. the manufacturing method of semiconductor structure as claimed in claim 11, which is characterized in that further include:

After the flatening process, and before forming the gallium nitride semiconductor layer, a cap rock is formed on this substrate and is covered Cover a remainder of the flowable dielectric material in the pit-hole.