CN110473851A - Mitigate the semiconductor devices of structure with stress - Google Patents

Mitigate the semiconductor devices of structure with stress Download PDF

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Publication number
CN110473851A
CN110473851A CN201910389088.3A CN201910389088A CN110473851A CN 110473851 A CN110473851 A CN 110473851A CN 201910389088 A CN201910389088 A CN 201910389088A CN 110473851 A CN110473851 A CN 110473851A
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CN
China
Prior art keywords
layer
folded
stress
heap
relieving
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CN201910389088.3A
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Chinese (zh)
Inventor
M.A.博德雅
T.R.海德曼
M.马塔尔恩
C.斯贾罗韦洛
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Infineon Technologies AG
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Infineon Technologies AG
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Priority claimed from US15/976,653 external-priority patent/US20190348373A1/en
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN110473851A publication Critical patent/CN110473851A/en
Pending legal-status Critical Current

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Abstract

The present invention relates to the semiconductor devices for mitigating structure with stress.Semiconductor devices includes: semiconductor body；Be arranged in semiconductor body at least partly on stress-relieving layer or layer heap it is folded, stress-relieving layer or layer heap it is folded include multiple openings, generate the patterned surface pattern folded for stress-relieving layer or layer heap；And be formed in stress-relieving layer or layer heap it is stacked on and occupy stress-relieving layer or layer heap it is folded in multiple openings metal layer or layer heap it is folded.The surface away from semiconductor body that the patterned surface pattern that stress-relieving layer or layer heap are folded is passed to metal layer or layer heap is folded.Stress-relieving layer or layer heap, which are stacked in have in certain temperature range, folds different elasticity modulus from metal layer or layer heap.

Description

Mitigate the semiconductor devices of structure with stress
Background technique
To with lower on-state resistance (RdsON) value, smaller tube core (chip) area and compared with the power half of small package The demand of conductor device is increasing.Other than the technological progress that semiconductor processes and concept units design, it is also necessary to improve Die metallization interacts with tube core is encapsulated into meet this increased demand.Die metallization and to be encapsulated into tube core mutual The recent advancement of effect includes using copper metallization on tube core and being pressed from both sides in a package using copper.
Compared with standard aluminum metallization, the introducing of copper metallization brings new challenge to encapsulation interaction to tube core. After the soldering process, increased bending/warpage in tube core and higher residual stress are since copper is incorporated to tube core and envelope Two examples challenged brought by dress technology.Tube core bending/warpage and residual stress may significantly affect tube core and clip is attached Termination process, so as to cause forming gap in solder and inclining relative to the formation of other substrates attached by lead frame or tube core Oblique tube core.
The shape in the gap in being conductively connected for example between tube core and tube core attachment substrate or between tube core and clip At the electrical property and hot property that may interfere with packaging, to the degree for allowing to occur initial failure.Moreover, cannot be always Filter out the packaging with this gap.
If tube core is relative to the substrate inclination attached by it, compared with other corner/edges, at an angle of tube core Fall or edge under there may be abnormal a small amount of solders.During temperature cycles, abnormal a small amount of solder may degrade, thus Lead to the initial failure of device.
Therefore, it is necessary to reduce the more steady technology of the bending of the tube core in tube core/warpage and higher residual stress.
Summary of the invention
According to the embodiment of semiconductor devices, semiconductor devices includes: semiconductor body；Semiconductor body is set extremely Stress-relieving layer or layer heap on small part is folded, and stress-relieving layer or layer heap are folded including multiple openings, generates and is used for stress The patterned surface pattern that relieved layer or layer heap are folded；And it is formed in stress-relieving layer or layer heap is stacked on and occupy stress-relieving layer Layer heap it is folded in multiple openings metal layer or layer heap it is folded.The patterned surface pattern that stress-relieving layer or layer heap are folded is passed The surface away from semiconductor body folded to metal layer or layer heap.Stress-relieving layer or layer heap, which are stacked in certain temperature range, to be had Different elasticity modulus are folded from metal layer or layer heap.In one embodiment, stress-relieving layer or layer heap are stacked in certain temperature model Have in enclosing and folds small elasticity modulus than metal layer or layer heap.In another embodiment, stress-relieving layer or layer heap are stacked in one Determine to have in temperature range and folds high elasticity modulus than metal layer or layer heap.
In embodiment, it may include the conjunction for selecting free polymer, acid imide, aluminium and copper that stress-relieving layer or layer heap, which are folded, The material in group that gold, oxide, nitride, silicon nitride, nitrogen oxides, nitride base ceramics and SiCOH are formed.
Either individually or in combination, semiconductor devices can also include wiring layer, form stress-relieving layer on the wiring layer Or layer heap is folded, wherein metal layer or layer heap are folded multiple openings in can folding by stress-relieving layer or layer heap and are connect with wiring layer electricity Touching.Multiple openings during stress-relieving layer or layer heap are folded can be arranged independently of the layout of wiring layer.
Either individually or in combination, metal layer or the folded most upper metal layer that can be semiconductor devices of layer heap.Stress-relieving layer Or the folded part of layer heap can be without being open or provide the surface topography of general planar with big opening, metal layer above Or it may include one or more contact pads (pad) that layer heap is folded.
Either individually or in combination, stress-relieving layer or layer heap it is folded in multiple openings can be arranged with regular pattern, make Obtaining the patterned surface pattern that stress-relieving layer or layer heap are folded can have regular pattern.
Either individually or in combination, stress-relieving layer or layer heap it is folded in multiple openings can be with checkerboard pattern, honeycomb pattern Or striped is arranged, stress-relieving layer or the folded patterned surface pattern of layer heap is allowed to be respectively provided with checkerboard pattern, honeycomb Pattern or candy strip.
Either individually or in combination, stress-relieving layer or layer heap, which are folded, can have corrugated contours, wherein having across multiple Alternate ridge and slot in the cross section of any row of opening.
Either individually or in combination, stress-relieving layer or layer heap it is folded in multiple openings may include that there is identical or basic phase The arrangement of the aturegularaintervals opening of similar shape.For example, the shape of aturegularaintervals opening can be selected from by square, rectangle, six sides The group of shape, ellipse and polygon composition.
Either individually or in combination, stress-relieving layer or layer heap it is folded in multiple openings may include same shape rule between Separate the row of mouth.
Either individually or in combination, stress-relieving layer or layer heap are folded can cover stress-relieving layer or the folded setting of layer heap its it On semiconductor body entire main surface 10% to 100% between.For example, stress-relieving layer or folded can cover of layer heap are answered The entire main surface of the semiconductor body of power relieved layer or the folded setting of layer heap above.
Either individually or in combination, multiple openings can be formed in the stress-relieving layer on the first part of semiconductor body Or layer heap it is folded in, and stress-relieving layer or layer heap is folded can be without being open or in the semiconductor body adjacent with first part Have big opening to provide the surface topography of general planar on second part.For example, the first part of semiconductor body can be with It is the center portion of semiconductor body, and the second part of semiconductor body can be lateral (laterally) around central portion The peripheral region of the semiconductor body divided.
Either individually or in combination, it may include: barrier metal layer that metal layer or layer heap, which are folded, cover stress-relieving layer or layer The side wall of opening during the top main surfaces and stress-relieving layer or layer heap of stacking are folded；And the copper of covering barrier metal layer Layer.
Either individually or in combination, in same a line opening in stress-relieving layer or layer heap are folded, the adjacent apertures in opening Between interval may be approximately equal to opening width.
Either individually or in combination, it may include copper that metal layer or layer heap, which are folded,.
Either individually or in combination, stress-relieving layer or layer heap are folded and can be formed on AlCu layer, and metal layer or layer heap It folds multiple openings in can folding by stress-relieving layer or layer heap or is in electrical contact by big opening with AlCu layers.
Either individually or in combination, stress-relieving layer or layer heap are folded may include the reeded semiconductor body of structuring after Doped region and/or polysilicon at main surface, and it may include the structure for covering semiconductor body that metal layer or layer heap, which are folded, Change rear major face barrier layer and formed over the barrier layer and filling semiconductor main body structuring rear major face in groove Layers of copper.
According to the embodiment of the method for manufacturing semiconductor devices, this method comprises: in the semiconductor body formed one or Multiple devices；Semiconductor body at least partly on to form stress-relieving layer or layer heap folded；In stress-relieving layer or layer heap Multiple openings are formed in folded, and it generates the patterned surface pattern folded for stress-relieving layer or layer heap；And in stress Relieved layer or the stacked on formation metal layer of layer heap or layer heap are folded so that metal layer or layer heap it is folded occupy stress-relieving layer or layer heap it is folded in Multiple openings, and the folded patterned surface pattern of stress-relieving layer or layer heap be transmitted to metal layer or layer heap it is folded away from half The surface of conductor main body, metal layer or layer heap, which are stacked in have in certain temperature range, folds different bullets from stress-relieving layer or layer heap Property modulus.In one embodiment, metal layer or layer heap, which are stacked in certain temperature range, has specific stress relieved layer or layer heap folded High elasticity modulus.In another embodiment, metal layer or layer heap, which are stacked in certain temperature range, has specific stress relieved layer Or layer heap folds small elasticity modulus.Either individually or in combination, semiconductor body at least partly on form stress-relieving layer Or it may include forming doped region at the rear major face of semiconductor body and/or polysilicon and by rear major face that layer heap is folded It is structured into groove, and folded in the stacked on formation metal layer of stress-relieving layer or layer heap or layer heap may include utilizing blocking Layer covers the structuring rear major face of semiconductor body and utilizes the layers of copper filling groove formed over the barrier layer.
According to the embodiment of semiconductor packages, semiconductor packages includes semiconductor devices, which includes: partly to lead Phosphor bodies；Be arranged in semiconductor body at least partly on stress-relieving layer or layer heap it is folded, stress-relieving layer or layer heap are folded Including multiple openings, the patterned surface pattern folded for stress-relieving layer or layer heap is generated；And it is formed in stress mitigation Layer or layer heap it is stacked on and occupy stress-relieving layer or layer heap it is folded in multiple openings metal layer or layer heap it is folded.Stress-relieving layer or The surface away from semiconductor body that the folded patterned surface pattern of layer heap is passed to metal layer or layer heap is folded.Stress-relieving layer Or layer heap is stacked in have in certain temperature range and folds different elasticity modulus from metal layer or layer heap.Semiconductor packages further includes attached It is connected to the folded metal connector of metal layer or layer heap.In one embodiment, stress-relieving layer or layer heap are stacked in certain temperature model Have in enclosing and folds small elasticity modulus than metal layer or layer heap.In another embodiment, stress-relieving layer or layer heap are stacked in one Determine to have in temperature range and folds high elasticity modulus than metal layer or layer heap.
It in embodiment, the part that stress-relieving layer or layer heap are folded can be without opening or with bigger opening to provide The surface topography of general planar, it may include contact pad that metal layer or layer heap are folded above, and metal connector can be with It is attached to contact pad.
Those skilled in the art will read described in detail below and recognize additional feature and advantage after checking attached drawing.
Detailed description of the invention
Element in each figure is not necessarily to scale relative to each other.Identical appended drawing reference indicates corresponding similar department Point.The feature of the embodiment of each diagram can be combined, unless they repel each other.Describe in the various figures and in description below Middle DETAILS SECTIONExample.
Fig. 1 shows the cross-sectional view of the part with the folded semiconductor devices of stress-relieving layer or layer heap.
Fig. 2 shows stress-relieving layer or layer heap to fold and in stress-relieving layer or the metal layer or layer heap of the stacked on formation of layer heap Folded perspective view.
Fig. 3 is shown without the folded stress-relieving layer of metal layer or layer heap or the folded perspective view of layer heap.
Fig. 4 A shows the plan view folded in the metal layer or layer heap of stress-relieving layer or the stacked on formation of layer heap.
Fig. 4 B shows the cross-sectional view of the structure by marking the line for being to intercept in Fig. 4 A.
Fig. 4 C shows the cross-sectional view of the structure by marking the line for being to intercept in Fig. 4 A.
Fig. 5 shows the plane in the folded another embodiment of the metal layer or layer heap of stress-relieving layer or the stacked on formation of layer heap Figure.
Fig. 6 shows the plane in the folded another embodiment of the metal layer or layer heap of stress-relieving layer or the stacked on formation of layer heap Figure.
Fig. 7 shows the plane in the folded another embodiment of the metal layer or layer heap of stress-relieving layer or the stacked on formation of layer heap Figure.
Fig. 8 shows the plane in the folded another embodiment of the metal layer or layer heap of stress-relieving layer or the stacked on formation of layer heap Figure.
Fig. 9 shows the plane in the folded another embodiment of the metal layer or layer heap of stress-relieving layer or the stacked on formation of layer heap Figure.
Figure 10 shows the plane in the folded another embodiment of the metal layer or layer heap of stress-relieving layer or the stacked on formation of layer heap Figure.
Figure 11, which is shown, has the stress-relieving layer or the stacked on formation of layer heap that small elasticity modulus is folded than metal layer or layer heap Metal layer or the folded another embodiment of layer heap partial cross sectional view.
Figure 12 is shown in the part of the folded another embodiment of the metal layer or layer heap of stress-relieving layer or the stacked on formation of layer heap Cross-sectional view.
Figure 13 is shown in the part of the folded another embodiment of the metal layer or layer heap of stress-relieving layer or the stacked on formation of layer heap Cross-sectional view.
Figure 14 shows the cross-sectional view of the semiconductor packages including semiconductor devices shown in Fig. 1.
Figure 15 A and 15B show the respective cross section figure of the part with the folded semiconductor devices of stress-relieving layer or layer heap.
Figure 16, which is shown, has the stress-relieving layer or the stacked on formation of layer heap that high elasticity modulus is folded than metal layer or layer heap Metal layer or the folded another embodiment of layer heap partial cross sectional view.
Specific embodiment
Embodiment described herein provide be arranged in semiconductor body at least partly on stress-relieving layer or layer Stack, be used to offset by be arranged in stress-relieving layer or layer heap it is folded on metal layer or folded the applied stress of layer heap.It answers Power relieved layer or layer heap are folded with multiple openings, generate patterned surface pattern.The figure folded for stress-relieving layer or layer heap The surface away from semiconductor body that case surface topography is passed to metal layer or layer heap is folded.Stress-relieving layer or the folded suction of layer heap During being received in temperature cycles by the folded at least some stress applied of metal layer or layer heap and/or be stored in metal layer or layer heap it is folded in Residual stress, thus a possibility that reducing high mechanical stress and tube core bending/warpage.
Fig. 1 shows the cross-sectional view of the part of semiconductor devices 100.Semiconductor devices 100 includes semiconductor body 102. Semiconductor body 102 be tube core singualtion before semiconductor wafer part, or can be after tube core singualtion half The part of conductor tube core (chip).In either case, it can be formed in semiconductor body 102 one or more passive And/or active device.For example, processor, ASIC(specific integrated circuit), memory, controller etc. logical device can To be formed in semiconductor body 102.Additionally or alternatively, such as insulated gate bipolar transistor (IGBT), power metal-oxide Object semiconductor field effect transistor (MOSFET), high electron mobility transistor (HEMT), power diode, half-bridge, full-bridge etc. Power device can also be formed in semiconductor body 102.Additionally or alternatively, such as Hall sensor, MEMS (MEMS) etc. sensor can also be formed in semiconductor body 102.Other can also be formed again in semiconductor body 102 The passive and/or active device of type.For ease of description, (one or more) device formed in semiconductor body 102 exists It is not shown in Fig. 1, but may include doped region, gate structure, groove, field plate, Ohmic contact of different conduction-types etc..
Semiconductor body 102 at least partly on that stress-relieving layer (i.e. single stress-relieving layer) or layer heap is arranged is folded (the i.e. one more than one stress-relieving layer stacked on top of the other) 104.That is, stress-relieving layer or layer heap are folded Completely or only a part of 104 covering semiconductor bodies 102.For example, stress-relieving layer or layer heap folded 104 can cover stress and subtract 10% to the 100% of the entire main surface 106 of the semiconductor body 102 of light layer or folded 104 setting of layer heap above.At one In embodiment, stress-relieving layer or layer heap folded 104 can cover stress-relieving layer or folded 104 setting of layer heap partly leading above The entire main surface 106 of phosphor bodies 102.
Stress-relieving layer or layer heap folded 104 have multiple openings 108, generate for stress-relieving layer or layer heap folded 104 Patterned surface pattern.That is, the surface 110 away from semiconductor body 102 of stress-relieving layer or layer heap folded 104 has There is patterned shape, by quantity, interval, the shape and size of the opening 108 formed in stress-relieving layer or layer heap folded 104 It limits.Opening 108 in stress-relieving layer or layer heap folded 104 can be arranged with rule or irregular pattern, so that stress subtracts Light layer or the patterned surface pattern of layer heap folded 104 are respectively provided with corresponding rule or irregular pattern.Opening 108 can pass through The standard etching process of the mask and wet process of such as stress-relieving layer or layer heap folded 104 or dry etching etc is subtracted by stress The laser drill of light layer or layer heap folded 104 is formed by patterned deposition of stress-relieving layer or layer heap folded 104 etc..
Metal layer (i.e. single metal layer) or layer heap fold (the i.e. one more than one metal layer stacked on top of the other) 112 form and occupy the opening 108 in stress-relieving layer or layer heap folded 104 in stress-relieving layer or layer heap folded 104.Metal Layer or layer heap folded 112 can partially or even wholly fill the opening 108 in stress-relieving layer or layer heap folded 104.It can be used Any commonly employed (one or more) metal or metal stack in semiconductor industry.
The patterned surface pattern of stress-relieving layer or layer heap folded 104 is passed to deviating from for metal layer or layer heap folded 112 The surface 114 of semiconductor body 102.Therefore, the surface 114 away from semiconductor body 102 of metal layer or layer heap folded 112 has The identical or essentially identical patterning shape with the surface 110 away from semiconductor body 102 of stress-relieving layer or layer heap folded 104 Shape.Although metal layer or layer heap folded 112 and stress-relieving layer or layer heap folded 104 have identical or essentially identical overall shape/ Structure/profile, but relative size can be different.For example, the vertical side of stress-relieving layer or the opening 108 in layer heap folded 104 Wall 116 can be covered with the material more little more or a little less than horizontal component 118, and along the side wall 116 of opening 108 Metal layer or layer heap folded 112 thickness can on the horizontal component 118 of stress-relieving layer or layer heap folded 104 and be open 108 Bottom 120 at metal layer or layer heap folded 112 thickness it is different.Moreover, having the metal layer of patterning pattern or layer heap folded 112 surface 114 is not flattened.Therefore, metal layer or layer heap folded 112 retain from folded 104 transmitting of stress-relieving layer or layer heap Patterned surface pattern.Metal layer or layer heap folded 112 can be thick-layer, so that from folded 104 transmitting of stress-relieving layer or layer heap Patterned surface pattern may be almost invisible.
In certain temperature range, stress-relieving layer or layer heap folded 104 are also with different from metal layer or layer heap folded 112 Elasticity modulus (such as Young's modulus), the temperature range can be whole (entire) work that may not be semiconductor devices 100 Make range.In one embodiment, stress-relieving layer or layer heap folded 104 have within the scope of temperature interested than metal layer or Layer heap folds 112 small elasticity modulus.For example, stress-relieving layer or layer heap folded 104 may include stable or soluble polymer, One of acid imide, the alloy of aluminium and copper and oxide are a variety of.Stress-relieving layer or layer heap folded 104 are absorbed in temperature At least some stress and/or be stored in metal layer or layer heap folded 112 that 112 apply are folded by metal layer or layer heap during circulation Residual stress, thus a possibility that reducing high mechanical stress and tube core bending/warpage.
In another embodiment, stress-relieving layer or layer heap folded 104 have within the scope of temperature interested than metal Layer or layer heap fold 112 high elasticity modulus.For example, stress-relieving layer or layer heap folded 104 may include tungsten-bast alloy (for example, tool Have titanium or nitride), nickel or nickel-base alloy (for example, there is vanadium or phosphorus), one of doped silicon and/or polysilicon or a variety of. In the case where doped silicon, then the rear major face 122 of semiconductor body 102 can for example be tied by etching doped with phosphorus Then structure is for example filled with copper.Stress-relieving layer or layer heap folded 104 can be bent/stick up to reduce high mechanical stress and tube core The mode of a possibility that bent compensates some stress and/or remnants applied during temperature cycles by metal layer or layer heap folded 112 Stress.
Metal layer or layer heap folded 112 can be applied on the either side of semiconductor body 102 and corresponding stress mitigates Layer or layer heap folded 104.That is, metal layer or layer heap folded 112 and corresponding stress-relieving layer or layer heap folded 104 can apply In the preceding main surface 106 of semiconductor body 102, on the rear major face 122 of semiconductor body 102 or two main surfaces 106, on 122.
With the metal layer or layer for folding 104 identical or essentially identical patterned surface patterns with stress-relieving layer or layer heap Stacking 112 can be most upper (final) metallization of semiconductor devices 100.In this case, metal layer or layer heap folded 112 are (one or more) device formed in semiconductor body 102 provides one or more external electrical contact points.For example, such as In the case where the power transistor device of IGBT, bipolar transistor, HEMT, MEMS etc., metal layer or layer heap folded 112 may include Gate pads, source pad and/or drain pad.In the case where power diode device, metal layer or layer heap folded 112 can be with Including anode bond pad and/or cathode pad.In the case where logical device, metal layer or layer heap folded 112 may include largely welding Disk.
As replacement, has and fold 104 identical or essentially identical patterned surface patterns with stress-relieving layer or layer heap Metal layer or layer heap folded 112 can be near semiconductor body 102 most under (first) metallize.In this case, may be used To provide additional layer or layer heap folded 124, such as oxide or one or more additional gold on metal layer or layer heap folded 112 Belong to layer or layer heap is folded.The quantity and composition that the layer on metal layer or layer heap folded 112 is arranged in can be directed to semiconductor devices 100 Different zones and change, independently of metal layer or layer heap folded 112 and stress-relieving layer or layer heap folded 104.As replacement, tool Having can with the metal layer or layer heap folded 112 of stress-relieving layer or the folded 104 identical or essentially identical patterned surface patterns of layer heap To be intermediate metallization.In this case, one or more additional metal layers are formed on intermediate metal layer or layer heap are folded Or layer heap is folded, and the one or more additional metal layers of formation or layer heap are folded under intermediate metal layer or layer heap are folded, middle layer Between dielectric different metalization layer is separated.
Fig. 1 shows the metal layer or layer heap folded 112 as most upper (final) metallization or as intermediate metallization.At this In the case of kind, one or more additional metals can be provided between metal layer or layer heap folded 112 and semiconductor body 102 Layer, and (one or more) extra play can be set between intermediate metallization and semiconductor substrate, as shown in vertical dotted line.
For example, one in extra play or layer heap folded 124 can be additional metal, it is such as formed on stress mitigation The wiring layer of layer or layer heap folded 104.With folding 104 identical or essentially identical patterned surface shapes with stress-relieving layer or layer heap The metal layer or layer heap of looks folded 112 can pass through the opening 108 and additional metallization layers electricity in stress-relieving layer or layer heap folded 104 Contact.In one embodiment, stress-relieving layer or layer heap fold the opening 108 in 104 independently of the cloth of additional metallization layers 124 Office arranges.Although being strain relieved that is, the opening 108 in stress-relieving layer or layer heap folded 104 makes it possible to realize Electrical contact between layer or two metalization layers 112,124 of folded 104 separation of layer heap, but the layout of opening 108 is designed to So that stress-relieving layer or layer heap folded 104 absorb and are applied at least during temperature cycles by upper metal-clad or layer heap folded 112 Some stress and/or the residual stress being stored in metal layer or layer heap folded 112.
Fig. 2 shows the stress-relieving layer according to the embodiment with identical or essentially identical patterned surface pattern or The perspective view of layer heap folded 104 and metal layer or layer heap folded 112.Fig. 3 shows no metal layer or the stress of layer heap folded 112 subtracts The perspective view of light layer or layer heap folded 104.According to this embodiment, stress-relieving layer or layer heap folded 104 have identical or essentially identical The row 126 of the aturegularaintervals opening 108 of shape.The shape of aturegularaintervals opening 108 can be square, rectangle, hexagon, ellipse Circle, polygon etc..Although the opening 108 that stress-relieving layer or layer heap are folded in 104 in figs 2 and 3 is shown as with rule schema Case arrangement, but as replacement, pattern can be irregular.In either case, the figure of stress-relieving layer or layer heap folded 104 Case surface topography is passed in the metal layer being formed in stress-relieving layer or layer heap folded 104 or layer heap folded 112, so that golden Belonging to layer or layer heap folded 112 has and stress-relieving layer or the folded 104 identical or essentially identical patterned surface patterns of layer heap.
Fig. 4 A shows the plan view of the metal layer or layer heap folded 112 that are formed in stress-relieving layer or layer heap folded 104.Figure 4B shows the cross-sectional view of the structure by marking the line for being to intercept in Fig. 4 A.Fig. 4 C is shown by marking in Fig. 4 A For the cross-sectional view for the structure that the line of B-B' intercepts.As described above, metal layer or layer heap folded 112 can be most upper (final) metal Change, most under (first) metallization or intermediate metallization.
Cross sections cross in Fig. 4 B passes through a line opening 108 in stress-relieving layer or layer heap folded 104, and in Fig. 4 C Structure of the cross sections cross across adjacent rows 108.According to this embodiment, stress-relieving layer or the folded 104 covering stress of layer heap The entire main surface 106 of the semiconductor body 102 of relieved layer or folded 104 setting of layer heap above.As shown in Figure 4 B and 4C, golden Category layer or the surface topography of layer heap folded 112 follow the surface topography of stress-relieving layer or layer heap folded 104.That is, metal layer Or the surface 114 away from semiconductor body 102 of layer heap folded 112 has and partly leads with stress-relieving layer or deviating from for layer heap folded 104 The identical or essentially identical patterned shape in the surface 110 of phosphor bodies 102.
Fig. 5 shows another embodiment of the metal layer or layer heap folded 112 that are formed in stress-relieving layer or layer heap folded 104 Plan view.According to this embodiment, metal layer or layer heap folded 112 are most upper (final) metal layers of semiconductor devices 100.Scheming In 5, stress-relieving layer or layer heap folded 104 be not in the visual field.However, the part of stress-relieving layer or layer heap folded 104 is not open And the surface topography with general planar.The surface topography of general planar is passed to metal layer or layer heap folded 112.Metal layer Or layer heap folded 112 may include one or more be arranged on the part of the stress-relieving layer not being open or layer heap folded 104 A contact pad 200, such as the feelings in the flat that electric current or temperature sensor are laid in metal layer or layer heap folded 112 Under condition.That is, one or more contact pads 200 are formed in the table with general planar of metal layer or layer heap folded 112 In the part 202 of face pattern.In another embodiment, the part of stress-relieving layer or layer heap folded 104 has big opening to provide The surface topography of general planar forms one or more contact pads 200 above for example to contact setting in stress and mitigate Metal layer under layer or layer heap folded 104.In any case, each contact pad 200 has the flat surfaces of opposite crests. External electrical connections can be such as by proceeding to one or more contact pads 200 closing line, metal tape, metal clip, solder. Metal layer or the rest part of layer heap folded 112 have non-planar surface pattern, have imitated following stress-relieving layer or layer heap Folded 104 non-planar surface pattern.Exploded view in Fig. 5 is exaggerated the flat and non-planar surface of metal layer or layer heap folded 112 Boundary between pattern.
Metal layer or layer heap folded 112 may include one or more bridge zone domains 201, for being electrically connected metal layer or layer heap Folded 112 adjacent area, without metal layer or layer heap folded 112 are connected to following conductive structure, such as metal or polysilicon Line.Following conductive structure can be source fingers, the gate fingers etc. laid under metal layer or layer heap folded 112.Such as Described herein, stress-relieving layer or layer heap folded 104 are present under each bridge zone domain 201, and are used as bridge mechanism, are used to connect Also metal layer or layer heap folded 112 are isolated with following conductive structure simultaneously for metal layer or the adjacent area of layer heap folded 112, such as In the case where the connection of the metal of the sensor of gate fingers, source fingers, electric current or temperature etc..
Fig. 6 shows another embodiment of the metal layer or layer heap folded 112 that are formed in stress-relieving layer or layer heap folded 104 Plan view.According to this embodiment, opening 108 in stress-relieving layer or layer heap folded 104 is arranged with checkerboard pattern, so that answering The patterned surface pattern of power relieved layer or layer heap folded 104 has checkerboard pattern, which is passed to metal layer or layer Stack 112.Adjacent apertures in opening 108 in the mutually colleague 126 of opening 108 in stress-relieving layer or layer heap folded 104 it Between interval (Sp) may be approximately equal to opening 108 width (W).Other intervals and width can be considered.It is spaced (Sp) and wide Spending (W) can be different, and can be different between the row of the opening 108 in stress-relieving layer or layer heap folded 104.Stress mitigates Opening 108 in layer or layer heap folded 104 is invisible in Fig. 6.
Fig. 7 shows another embodiment of the metal layer or layer heap folded 112 that are formed in stress-relieving layer or layer heap folded 104 Plan view.According to this embodiment, opening 108 in stress-relieving layer or layer heap folded 104 is arranged with honeycomb pattern, so that answering The patterned surface pattern of power relieved layer or layer heap folded 104 has honeycomb pattern, which is passed to metal layer or layer Stack 112.Between the adjacent apertures of opening 108 in the mutually colleague 126 of stress-relieving layer or the opening 108 in layer heap folded 104 Interval (Sp) may be approximately equal to opening 108 width (W).Other intervals and width can be considered.It is spaced (Sp) and width (W) can be different, and can be different between the row of the opening 108 in stress-relieving layer or layer heap folded 104.Stress-relieving layer Or the opening 108 in layer heap folded 104 is invisible in Fig. 7.
Fig. 8 shows another embodiment of the metal layer or layer heap folded 112 that are formed in stress-relieving layer or layer heap folded 104 Plan view.According to this embodiment, metal layer or layer heap folded 112 cover at least the 90% of semiconductor body 102 and are segmented At individual part 300,302,304.Some in part 300,302,304 may include contact pad 306 and/or part 300, some or all of 302,304 contact pad can be formed with itself.In each case, metal layer or layer heap folded 112 Each part 300,302,304 there is the table with stress-relieving layer or layer heap folded 104 below the part 300,302,304 The identical or essentially identical patterned shape in the part in face.Separate section 300,302,304 can be electrically connected each other by bridge zone domain It connects, for example, as previously described in conjunction with Figure 5 herein.
Fig. 9 shows another embodiment of the metal layer or layer heap folded 112 that are formed in stress-relieving layer or layer heap folded 104 Plan view.Embodiment shown in Fig. 9 is similar to embodiment shown in fig. 8.Unlike however, metal layer or layer heap Folded 112 covering semiconductor bodies 102 are less than 90%, between for example, about 75% to 25%.
Figure 10 shows another implementation of the metal layer or layer heap folded 112 that are formed in stress-relieving layer or layer heap folded 104 The plan view of example.According to this embodiment, stress-relieving layer or layer heap folded 104 have corrugated contours, wherein having across multiple Alternate ridge 400 and slot 402 in the lateral cross of any row of opening 108.Metal layer or layer heap folded 112 has and stress Relieved layer or layer heap fold 104 identical or essentially identical corrugated contours.
Figure 11 shows another implementation of the metal layer or layer heap folded 112 that are formed in stress-relieving layer or layer heap folded 104 The partial cross sectional view of example.According to this embodiment, metal layer or layer heap folded 112 include such as WTi, Ta, TaN, TiN, Ti, W, The barrier metal layer 500 of TiW etc., cover stress-relieving layer or layer heap folded 104 top main surfaces 110 and stress-relieving layer or The side wall 116 of opening 108 in layer heap folded 104.Metal layer or layer heap folded 112 include the layers of copper of covering barrier metal layer 500 502.Barrier metal layer 500 and layers of copper 502 can be used any common metallurgy of copper technique and formed, and such as physically or chemically sink Product, plating etc..It in some cases, can be with if the underlying metal composition of metal layer or layer heap folded 112 is less likely diffusion Barrier metal layer 500 is omitted, for example, in such as extension Cu3In the case where the Cu-Ge alloy of Ge.It is formed with stress mitigation thereon Layer or the material of layer heap folded 104 can be semiconductor body 102, another layer or layer heap fold 124(it is for example such as Cu layers another, AlCu layers etc.) or insulating layer (such as such as oxide, nitride, silicon nitride, nitrogen oxides, nitride base ceramics, SiCOH Deng).
Figure 12 shows another implementation of the metal layer or layer heap folded 112 that are formed in stress-relieving layer or layer heap folded 104 The partial cross sectional view of example.Exploded view in Figure 12 is exaggerated the part of shown semiconductor devices.According to this embodiment, stress subtracts Light layer or layer heap folded 104 include acid imide and cover the semiconductor body of stress-relieving layer or folded 104 setting of layer heap above 102 entire main surface 106.Upper metal-clad or layer heap folded 112 include barrier metal layer 600, such as WTi, Ta, TaN, TiN Deng the top main surfaces 110 and stress-relieving layer or the opening in layer heap folded 104 of covering stress-relieving layer or layer heap folded 104 108 side wall 116.Upper metal-clad or layer heap folded 112 include the layers of copper 602 of covering barrier metal layer 600.Barrier metal layer 600 and layers of copper 602 any common metallurgy of copper technique can be used and formed, physically or chemically deposit, be electroplated etc..On cover gold Belong to layer or layer heap folded 112 to connect by the opening 108 in stress-relieving layer or layer 104 with folded 124 electricity of following metal layer or layer heap Touching.In one embodiment, below metal layer or layer heap folded 124 includes being formed on stress-relieving layer or layer 104 The barrier layer 606 of W, TiW below AlCu layer 604 and AlCu layers etc..Barrier layer 606 is for example, by such as boron phosphoric silicate The dielectric layer 608 of glass (BPSG) is separated with semiconductor body 102.Dielectric layer 608 can have permission and semiconductor master The slot that body 102 is in electrical contact.
Multiple openings 108 in stress-relieving layer or layer heap folded 104 can arrange with rule or irregular pattern, so that The patterned surface pattern of stress-relieving layer or layer heap folded 104 is respectively provided with corresponding rule or irregular pattern.Figure 12 is shown The wherein interval between the adjacent apertures of the opening 108 in same a line opening 108 in stress-relieving layer or layer heap folded 104 (Sp) it is approximately equal to the embodiment of the width (W) of opening 108.For example, interval (Sp) and width (W) may be about 10 μm it is (micro- Rice).It can be considered other intervals and width, and 10 μm of example purely illustratives given above, and be not construed as It is restrictive.Being spaced (Sp) and width (W) parameter can be different, and can be in stress-relieving layer or layer heap folded 104 It is different between the row of opening 108.
The height or thickness (H) of stress-relieving layer or layer heap folded 104 for example can be in the range of about 6 to 11 μm.Invention People's discovery, the height/thickness (H) that the stress-relieving layer or layer heap for increasing the imide with patterned surface pattern are folded is (such as It is described herein, from about 6 μm to 11 μm) increase bending/warpage under the lower temperature below about 250 DEG C, and for being greater than about 250 DEG C higher temperature, bending/warpage is held essentially constant.As replacement, the height/thickness of stress-relieving layer or layer heap folded 104 It (H) can be less than 6 μm or greater than 11 μm.Inventor also found, for as described herein with patterned surface pattern Imide stress-relieving layer or the folded tube core of layer heap for, and there is the stress by such patterned imide The tube core for zero covering that relieved layer or layer heap are folded is compared, and the bending near 300 DEG C/warpage variation (slope) is more flat.This is It is especially important, because the solidification of solder occurs near the temperature, more so as to cause the technique change handled about tube core Stable tube core attachment technique.
Figure 13 shows another implementation of the metal layer or layer heap folded 112 that are formed in stress-relieving layer or layer heap folded 104 The partial cross sectional view of example.Embodiment shown in Figure 13 is similar to embodiment shown in Figure 12.Unlike however, answer Multiple openings 108 in power relieved layer or layer heap folded 104 are formed on the first part 700 of semiconductor body 102, and Shape in stress-relieving layer or layer heap folded 104 on the second part 702 of the semiconductor body 102 adjacent with first part 700 At big opening, to provide the surface topography of general planar.Metal layer or layer heap folded 112 contact following extra play by big opening Or layer heap folded 124.Inventors have found that folded with the stress-relieving layer or layer heap as described herein with patterned surface pattern Tube core part covering (for example, about 50% covering or the interior section of tube core) be still to have in terms of bending/warpage reduction Benefit, but not to identical degree is completely covered.This is equally applicable to will be patterned into surface topography and is placed on the outer of tube core In half portion (periphery).
In one embodiment, the first part 700 of semiconductor body 102 is the center portion of semiconductor body 102, and Second part 702 is the peripheral region of semiconductor body 102, along an at least side positioning for center portion or with its unitary side To around center portion.The central portion of semiconductor body 102 is arranged in the semiconductor devices being formed in semiconductor body 102 Point, it is considered the active region of semiconductor body 102.The active region of semiconductor body 102 is semiconductor body The region of 102 component part including device.For example, active region may include the doped region of different conduction-types, grid Pole structure, groove, field plate, Ohmic contact etc..
Figure 14 shows the cross-sectional view of the semiconductor packages 800 including semiconductor devices 100 shown in Fig. 1.Device 100 semiconductor body 102 is attached to standard substrate 802, printed circuit board (PCB), lead frame etc..Semiconductor packages 800 further include metal connector 804, such as clip, and metal layer or the layer heap that semiconductor devices 100 is attached at one end are folded 112.The opposite end of metal connector 804 is attached to substrate 802, for example, being attached to the metal trace of PCB, lead frame draws Line etc..Metal connector 804 can be connected to metal layer or layer heap folded 112 by solder 806.Inventors have found that using such as this Metal layer or layer heap described in text with patterned surface pattern are stacked in " recess " or " sinking " of metal layer or layer heap folded 112 Solder void is positioned and is distributed in region 808.
In one embodiment, the part of stress-relieving layer or layer heap folded 104 can without be open or have big opening with The surface topography of general planar is provided.Metal layer or layer heap folded 112 can have and be arranged on the surface topography of general planar Contact pad, for example, herein previously in conjunction with as described in Fig. 5,8 and 9.In this case, metal connector 804 can be attached To contact pad.Consider again other metal connector attachment arrangements, and embodiment described herein in the range of.
Although the metal layer with patterning pattern or layer heap are folded 112 surface 114 by the embodiment previously herein described It is described as non-planarization, but as replacement, surface 114 can be subjected to flatening process, such as chemically mechanical polishing (CMP). Figure 15 A shows corresponding semiconductor devices 900.As shown in fig. 15, metal layer or the top surface 114 of layer heap folded 112 are usually Flat.Since the opening 108 in stress-relieving layer or layer heap folded 104 is filled with metal, so by stress-relieving layer or layer It stacks 104 and provides enough stress mitigations.In some cases, such as shown in fig. 15b, in metal layer or layer heap folded 112 Planarization after, the top surface 110 of stress-relieving layer or layer heap folded 104 can be partially visible.Depending on used The type of flatening process or by design, metal layer or layer heap folded 112 can be recessed in stress-relieving layer or layer heap folded 104 Under top surface 110.
Figure 16 is shown in which that layers of copper 1000 and barrier metal layer 1002 are formed in the rear major face of semiconductor body 102 The partial cross sectional view of the embodiment of back metalization stacking is formed on 122.According to this embodiment, stress-relieving layer or layer heap Folded 104 have within the scope of temperature interested than back metal change 1000/1002 high elasticity modulus of stacking.For example, stress Relieved layer or layer heap folded 104 may include doped silicon and/or polysilicon.In the case where doped silicon, after semiconductor body 102 Main surface 122 can be doped with phosphorus, then for example by etching come structuring, so that the rear major face 122 of semiconductor body 102 With groove.Then, the rear major face 122 of semiconductor body 102 is blocked the covering of metal layer 1002, is then filled out with layers of copper 1000 Fill groove.Stress-relieving layer or layer heap folded 104 can be in a manner of a possibility that reducing high mechanical stress and tube core bending/warpage It compensates and some stress and/or residual stress that 1000/1002 applies is stacked by back metalization during temperature cycles, such as herein It is previously described.
For ease of description, using " under ", " under ", " lower part ", " on ", the spatially relative term on " top " etc. To explain positioning of the element relative to second element.These terms be intended to include in addition to it is discribed in the accompanying drawings those Orient being differently directed for the device other than different orientations.In addition, the term of " first ", " second " etc. is also used to describe respectively Kind element, region, section etc., and it is restrictive for being not intended to.Throughout specification, same term refers to same member Part.
As it is used herein, term " having ", " containing ", " including ", " including " etc. are open-ended terms, institute is indicated The presence of the elements or features of statement, but it is not excluded for additional elements or features.Article " one ", " one " and " being somebody's turn to do " are intended to include Plural number and odd number, unless the context clearly indicates otherwise.
In view of the modification and application of above range, it should be appreciated that the present invention is not limited by foregoing description, also not by Attached drawing limitation.As replacement, the present invention is only limited by following claims and their legal equivalents.

Claims (24)

1. a kind of semiconductor devices comprising:
Semiconductor body；
Be arranged in semiconductor body at least partly on stress-relieving layer or layer heap it is folded, stress-relieving layer or layer heap is folded includes Multiple openings generate the patterned surface pattern folded for stress-relieving layer or layer heap；And
Be formed in stress-relieving layer or layer heap it is stacked on and occupy stress-relieving layer or layer heap it is folded in multiple openings metal layer or Layer heap is folded,
Wherein, the folded patterned surface pattern of stress-relieving layer or layer heap be passed to metal layer or layer heap it is folded away from semiconductor The surface of main body,
Wherein, stress-relieving layer or layer heap, which are stacked in have in certain temperature range, folds different springforms from metal layer or layer heap Amount.
2. semiconductor devices according to claim 1, wherein stress-relieving layer or layer heap are folded including selecting free polymer, acyl In the group that imines, the alloy of aluminium and copper, oxide, nitride, silicon nitride, nitrogen oxides, nitride base ceramics and SiCOH are formed Material.
3. semiconductor devices according to claim 1 further includes wiring layer, formed on the wiring layer stress-relieving layer or Layer heap is folded, wherein metal layer or layer heap it is folded by stress-relieving layer or layer heap it is folded in multiple openings and wiring layer be in electrical contact.
4. semiconductor devices according to claim 3, wherein stress-relieving layer or layer heap it is folded in multiple openings independently of The layout of wiring layer is arranged.
5. semiconductor devices according to claim 1, wherein metal layer or layer heap it is folded be semiconductor devices most upper metal Layer.
6. semiconductor devices according to claim 5, the part that wherein stress-relieving layer or layer heap are folded is not open or has There is big opening to provide the surface topography of general planar, metal layer or layer heap are folded including one or more Contact weldings above Disk.
7. semiconductor devices according to claim 1, wherein stress-relieving layer or layer heap it is folded in multiple openings with rule Pattern arranges, so that stress-relieving layer or the folded patterned surface pattern of layer heap have regular pattern.
8. semiconductor devices according to claim 1, wherein stress-relieving layer or layer heap it is folded in multiple openings with chessboard Pattern, honeycomb pattern or striped arrange, so that stress-relieving layer or the folded patterned surface pattern of layer heap are respectively provided with chessboard Pattern, honeycomb pattern or candy strip.
9. semiconductor devices according to claim 1, wherein stress-relieving layer or layer heap are folded with corrugated contours, wherein having There are the alternate ridge and slot in the cross section of any row for passing through multiple openings.
10. semiconductor devices according to claim 1, wherein stress-relieving layer or layer heap it is folded in multiple openings include phase The row of the aturegularaintervals opening of same or essentially identical shape.
11. semiconductor devices according to claim 10, wherein the shape of aturegularaintervals opening is selected from by square, square The group of shape, hexagon, ellipse and polygon composition.
12. semiconductor devices according to claim 1, wherein stress-relieving layer or layer heap superimposition lid stress-relieving layer or layer Between stack the entire main surface of the semiconductor body of setting above 10% to 100%.
13. semiconductor devices according to claim 12, wherein stress-relieving layer or layer heap superimposition lid stress-relieving layer or The entire main surface of the semiconductor body of the folded setting of layer heap above.
14. semiconductor devices according to claim 1, it is plurality of be open be formed in semiconductor body first part it On stress-relieving layer or layer heap it is folded in, and wherein stress-relieving layer or layer heap are folded without opening or adjacent with first part Semiconductor body second part on have big opening to provide the surface topography of the general planar for second part.
15. semiconductor devices according to claim 14, wherein the first part of semiconductor body is semiconductor body Center portion, and wherein the second part of semiconductor body is the external zones laterally around the semiconductor body of center portion Domain.
16. semiconductor devices according to claim 1, wherein metal layer or layer heap, which are folded, includes:
During the top main surfaces and stress-relieving layer or layer heap that barrier metal layer, covering stress-relieving layer or layer heap are folded are folded The side wall of opening；And
Cover the layers of copper of barrier metal layer.
17. semiconductor devices according to claim 1, wherein same a line opening in stress-relieving layer or layer heap are folded In, the interval between the adjacent apertures in opening is approximately equal to the width of opening.
18. semiconductor devices according to claim 1, wherein metal layer or layer heap are folded including copper.
It further include being formed on stress-relieving layer or layer heap is folded 19. semiconductor devices according to claim 18 AlCu layers, wherein metal layer or layer heap it is folded by stress-relieving layer or layer heap it is folded in multiple openings or pass through big opening and AlCu Layer electrical contact.
20. semiconductor devices according to claim 1, wherein stress-relieving layer or layer heap are folded reeded including structuring Doped region and/or polysilicon at the rear major face of semiconductor body, and wherein metal layer or layer heap are folded including covering half The barrier layer of the structuring rear major face of conductor main body and formation are over the barrier layer and after the structuring of filling semiconductor main body The layers of copper of groove in main surface.
21. a kind of method of manufacturing semiconductor devices, which comprises
One or more devices are formed in the semiconductor body；
Semiconductor body at least partly on to form stress-relieving layer or layer heap folded；
Multiple openings are formed in stress-relieving layer or layer heap are folded, and it generates the pattern folded for stress-relieving layer or layer heap Change surface topography；And
It is folded in the stacked on formation metal layer of stress-relieving layer or layer heap or layer heap, so that metal layer or layer heap fold and occupy stress-relieving layer Or layer heap it is folded in multiple openings, and stress-relieving layer or the folded patterned surface pattern of layer heap are transmitted to metal layer or layer heap The folded surface away from semiconductor body, metal layer or layer heap, which are stacked in certain temperature range, to be had and stress-relieving layer or layer heap Fold different elasticity modulus.
22. according to the method for claim 21, wherein semiconductor body at least partly on form stress-relieving layer Or it includes forming doped region at the rear major face of semiconductor body and/or polysilicon and by rear major face structure that layer heap is folded Chemical conversion has groove, and wherein folds in the stacked on formation metal layer of stress-relieving layer or layer heap or layer heap and cover including the use of barrier layer The structuring rear major face of lid semiconductor body and utilize the layers of copper filling groove formed over the barrier layer.
23. a kind of semiconductor packages, comprising:
Semiconductor devices, the semiconductor devices include:
Semiconductor body；
Be arranged in semiconductor body at least partly on stress-relieving layer or layer heap it is folded, stress-relieving layer or layer heap is folded includes Multiple openings generate the patterned surface pattern folded for stress-relieving layer or layer heap；And
Be formed in stress-relieving layer or layer heap it is stacked on and occupy stress-relieving layer or layer heap it is folded in multiple openings metal layer or Layer heap is folded,
Wherein, the folded patterned surface pattern of stress-relieving layer or layer heap be passed to metal layer or layer heap it is folded away from semiconductor The surface of main body,
Wherein, stress-relieving layer or layer heap, which are stacked in have in certain temperature range, folds different springforms from metal layer or layer heap Amount；And
It is attached to the folded metal connector of metal layer or layer heap.
24. semiconductor packages according to claim 23, wherein stress-relieving layer or the folded part of layer heap be not open or With big opening to provide the surface topography of general planar, metal layer or layer heap are folded including contact pad above, and its Middle metal connector is attached to contact pad.
CN201910389088.3A 2018-05-10 2019-05-10 Mitigate the semiconductor devices of structure with stress Pending CN110473851A (en)

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