CN110459163B - Shift temporary storage device and display device - Google Patents

Shift temporary storage device and display device Download PDF

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CN110459163B
CN110459163B CN201910832250.4A CN201910832250A CN110459163B CN 110459163 B CN110459163 B CN 110459163B CN 201910832250 A CN201910832250 A CN 201910832250A CN 110459163 B CN110459163 B CN 110459163B
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shift register
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CN110459163A (en
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林炜力
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AUO Corp
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AU Optronics Corp
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/0286Details of a shift registers arranged for use in a driving circuit

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  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Shift Register Type Memory (AREA)

Abstract

The invention provides a shift register device, which comprises a plurality of stages of shift registers connected in series. The nth stage shift register outputs a scan signal according to the nth clock signal. The driving transistor is controlled by the driving signal and receives the nth clock signal to output the scanning signal of the nth shift register. The pull-up circuit is controlled by the driving signal, and starts to pull up the driving signal of the (n + 2) th stage shift register based on the reference high voltage in the enabling time of the nth clock signal. The pull-down control transistor controls the pull-up circuit to stop outputting the driving signal to the (n + 2) th stage shift register. The pull-up control transistor is controlled by a scanning signal of the (n-2) th stage of shift register and is coupled with the pull-up circuit and a reference low voltage, wherein n is an integer greater than or equal to 3. A display device is also provided.

Description

移位暂存装置与显示装置Shift temporary storage device and display device

技术领域technical field

本发明涉及一种显示面板驱动技术,且特别涉及一种移位暂存装置与显示装置。The invention relates to a display panel driving technology, and in particular to a shift temporary storage device and a display device.

背景技术Background technique

随着显示面板技术的发展,窄边框显示屏幕已经成为目前的主流产品。现有的显示面板可以利用一种栅极驱动电路基板技术(gate on array,GOA),通过将驱动电路整合到显示面板的玻璃基板上以减少面积。With the development of display panel technology, display screens with narrow borders have become mainstream products at present. Existing display panels can use a gate-on-array (GOA) technology to reduce the area by integrating the driving circuit on the glass substrate of the display panel.

但另一方面来说,同样的显示面板可能会应用在不同系列的产品,因此可能需要具备搭配不同的时序设定的灵活度,例如对扫描线进行预充电的驱动时序或是非预充电的驱动时序。为了同时满足这两种驱动时序,驱动电路的设计上就需要额外小心。例如,现有技术中彼此间具有连动关系的移位暂存器可能因为驱动信号浮动造成漏电流问题。如何抑制漏电流就变成一个待解决的问题。But on the other hand, the same display panel may be applied to different series of products, so it may need to have the flexibility to match different timing settings, such as the driving timing of pre-charging or non-precharging driving timing. In order to satisfy these two driving timings at the same time, extra care is required in the design of the driving circuit. For example, the shift registers in the prior art that have a linkage relationship with each other may cause a leakage current problem due to floating driving signals. How to suppress the leakage current becomes a problem to be solved.

发明内容Contents of the invention

本发明提供一种移位暂存装置与显示装置,能够降低移位暂存装置的漏电流并增加移位暂存器的驱动能力与稳定性。The invention provides a shift register and a display device, which can reduce the leakage current of the shift register and increase the driving ability and stability of the shift register.

本发明的实施例提供一种配置于显示面板的基板上的移位暂存装置,移位暂存装置包括多级彼此串接在一起的移位暂存器。这些移位暂存器会根据多个时钟信号分别输出扫描信号至显示面板,其中第n级移位暂存器根据第n个时钟信号输出扫描信号,且包括驱动晶体管、上拉电路、下拉控制晶体管与上拉控制晶体管。驱动晶体管受控于驱动信号,其第一端接收第n个时钟信号,其第二端输出第n级移位暂存器的扫描信号。上拉电路受控于驱动信号并耦接参考高电压,用以输出给第(n+2)级移位暂存器的驱动信号,其中上拉电路用以在第n个时钟信号的使能时间中基于参考高电压开始上拉第(n+2)级移位暂存器的驱动信号。下拉控制晶体管耦接上拉电路且受控于第(n+4)级移位暂存器的扫描信号,用以控制上拉电路停止输出给第(n+2)级移位暂存器的驱动信号。上拉控制晶体管受控于第(n-2)级移位暂存器的扫描信号,其第一端耦接上拉电路,其第二端耦接参考低电压,其中n为大于或等于3的整数。An embodiment of the present invention provides a shift register device disposed on a substrate of a display panel. The shift register device includes multiple stages of shift registers connected in series. These shift registers output scanning signals to the display panel respectively according to multiple clock signals, wherein the shift register of the nth stage outputs scanning signals according to the nth clock signal, and includes driving transistors, pull-up circuits, pull-down control transistor with a pull-up control transistor. The driving transistor is controlled by the driving signal, its first terminal receives the nth clock signal, and its second terminal outputs the scanning signal of the nth stage shift register. The pull-up circuit is controlled by the driving signal and coupled to the reference high voltage to output the driving signal to the (n+2)th stage shift register, wherein the pull-up circuit is used to enable the nth clock signal In time, start to pull up the driving signal of the (n+2)th stage shift register based on the reference high voltage. The pull-down control transistor is coupled to the pull-up circuit and is controlled by the scan signal of the (n+4)th stage shift register to control the pull-up circuit to stop outputting to the (n+2) stage shift register drive signal. The pull-up control transistor is controlled by the scan signal of the (n-2)th stage shift register, its first end is coupled to the pull-up circuit, and its second end is coupled to the reference low voltage, where n is greater than or equal to 3 an integer of .

在本发明的一实施例中,在上述的移位暂存装置中,当这些时钟信号的使能时间彼此不重叠时,上拉控制晶体管被控制以使上拉电路在第(n+1)个时钟信号的使能时间中保持第(n+2)级移位暂存器的驱动信号被上拉后的电压电平。In an embodiment of the present invention, in the above-mentioned shift register device, when the enabling times of these clock signals do not overlap with each other, the pull-up control transistor is controlled so that the pull-up circuit The voltage level after the driving signal of the (n+2)th stage shift register is pulled up is maintained during the enabling time of the first clock signal.

在本发明的一实施例中,上述的移位暂存装置的上拉电路包括受控于驱动信号的第一上拉晶体管,其第一端耦接参考高电压,其第二端提供启动电压,以及第二上拉晶体管。第二上拉晶体管的栅极端耦接第一上拉晶体管的第二端与上拉控制晶体管的第一端,且接收启动电压,其第一端与其栅极端耦接在一起或者其第一端耦接参考高电压,以及其第二端输出给第(n+2)级移位暂存器的驱动信号。In an embodiment of the present invention, the pull-up circuit of the above-mentioned shift register device includes a first pull-up transistor controlled by a driving signal, its first end is coupled to a reference high voltage, and its second end provides a start-up voltage , and a second pull-up transistor. The gate terminal of the second pull-up transistor is coupled to the second terminal of the first pull-up transistor and the first terminal of the pull-up control transistor, and receives the startup voltage, and its first terminal is coupled to its gate terminal or its first terminal It is coupled to the reference high voltage, and its second terminal is output to the driving signal of the (n+2)th stage shift register.

在本发明的一实施例中,上述的移位暂存装置中的上拉控制晶体管的尺寸不同于第一上拉晶体管的尺寸。In an embodiment of the present invention, the size of the pull-up control transistor in the shift register device is different from the size of the first pull-up transistor.

在本发明的一实施例中,上述的移位暂存装置中的上拉控制晶体管的通道宽度大于第一上拉晶体管的通道宽度。In an embodiment of the present invention, the channel width of the pull-up control transistor in the shift register device is larger than the channel width of the first pull-up transistor.

在本发明的一实施例中,在上述的移位暂存装置中,在第(n+1)个时钟信号的使能时间中,上拉控制晶体管被关闭,且第一上拉晶体管与第二上拉晶体管被导通,第(n+2)级移位暂存器的驱动信号持续被参考高电压上拉。In an embodiment of the present invention, in the above-mentioned shift register device, during the enabling time of the (n+1)th clock signal, the pull-up control transistor is turned off, and the first pull-up transistor and the first pull-up transistor The second pull-up transistor is turned on, and the driving signal of the (n+2)th shift register is continuously pulled up by the reference high voltage.

在本发明的一实施例中,上述的移位暂存装置的第n级移位暂存器还包括下拉电路。下拉电路耦接于参考低电压与驱动晶体管的第二端之间且受控于第(n+4)级移位暂存器的扫描信号,用以下拉第n级移位暂存器的扫描信号。In an embodiment of the present invention, the shift register of the nth stage of the above-mentioned shift register device further includes a pull-down circuit. The pull-down circuit is coupled between the reference low voltage and the second end of the driving transistor and is controlled by the scan signal of the (n+4)th stage shift register to pull down the scanning of the nth stage shift register Signal.

在本发明的一实施例中,上述的移位暂存装置的下拉电路包括第一下拉晶体管与第二下拉晶体管。第一下拉晶体管受控于第(n+4)级移位暂存器的扫描信号,其第一端耦接驱动晶体管的栅极端,其第二端耦接参考低电压。第二下拉晶体管受控于第(n+4)级移位暂存器的扫描信号,其第一端耦接驱动晶体管的第二端,其第二端耦接参考低电压。In an embodiment of the present invention, the pull-down circuit of the shift register device includes a first pull-down transistor and a second pull-down transistor. The first pull-down transistor is controlled by the scan signal of the (n+4)th stage shift register, its first terminal is coupled to the gate terminal of the driving transistor, and its second terminal is coupled to the reference low voltage. The second pull-down transistor is controlled by the scan signal of the (n+4)th stage shift register, its first terminal is coupled to the second terminal of the driving transistor, and its second terminal is coupled to the reference low voltage.

在本发明的一实施例中,上述的移位暂存装置,还包括第一稳压电路与第二稳压电路。第一稳压电路与第二稳压电路耦接驱动晶体管的第二端且接收驱动信号,其中第一稳压电路与第二稳压电路用以根据驱动信号稳压第n级移位暂存器的扫描信号。In an embodiment of the present invention, the shift register device further includes a first voltage stabilizing circuit and a second voltage stabilizing circuit. The first voltage stabilizing circuit and the second voltage stabilizing circuit are coupled to the second terminal of the driving transistor and receive the driving signal, wherein the first voltage stabilizing circuit and the second voltage stabilizing circuit are used for stabilizing the nth stage shift register according to the driving signal the scanning signal of the device.

在本发明的一实施例中,在上述的移位暂存装置中,在第(n-2)个时钟信号的使能时间中,驱动信号从第一电平被改变至第二电平,其中第二电平大于第一电平;在第(n-1)个时钟信号的使能时间中,驱动信号被保持在不小于第二电平的状态;以及在第n个时钟信号的使能时间中,驱动信号被改变至第三电平,其中第三电平大于第二电平。In an embodiment of the present invention, in the above-mentioned shift register device, during the enabling time of the (n-2)th clock signal, the driving signal is changed from the first level to the second level, Wherein the second level is greater than the first level; during the enabling time of the (n-1)th clock signal, the driving signal is maintained at a state not less than the second level; and during the enabling time of the nth clock signal During the enabling time, the driving signal is changed to a third level, wherein the third level is greater than the second level.

在本发明的一实施例中,上述的移位暂存装置,其中参考高电压为直流高电压。In an embodiment of the present invention, in the above-mentioned shift register device, the reference high voltage is a DC high voltage.

本发明的一实施例提供一种显示装置,包括显示面板与移位暂存装置。移位暂存装置包括多级彼此串接在一起的移位暂存器,根据多个时钟信号分别输出扫描信号至显示面板,其中第n级移位暂存器根据第n个时钟信号输出扫描信号,且包括驱动晶体管、上拉电路、下拉控制晶体管与上拉控制晶体管。驱动晶体管受控于驱动信号,其第一端接收第n个时钟信号,其第二端输出第n级移位暂存器的扫描信号。上拉电路受控于驱动信号并耦接参考高电压,用以输出给第(n+2)级移位暂存器的驱动信号,其中上拉电路用以在第n个时钟信号的使能时间中基于参考高电压开始上拉第(n+2)级移位暂存器的驱动信号。下拉控制晶体管耦接上拉电路且受控于第(n+4)级移位暂存器的扫描信号,用以控制上拉电路停止输出给第(n+2)级移位暂存器的驱动信号。上拉控制晶体管受控于第(n-2)级移位暂存器的扫描信号,其第一端耦接上拉电路,其第二端耦接参考低电压,其中n为大于或等于3的整数。An embodiment of the present invention provides a display device, including a display panel and a shift register. The shift register device includes multiple stages of shift registers connected in series, which respectively output scan signals to the display panel according to multiple clock signals, wherein the shift register of the nth stage outputs scan signals according to the nth clock signal. signal, and includes a driving transistor, a pull-up circuit, a pull-down control transistor and a pull-up control transistor. The driving transistor is controlled by the driving signal, its first terminal receives the nth clock signal, and its second terminal outputs the scanning signal of the nth stage shift register. The pull-up circuit is controlled by the driving signal and coupled to the reference high voltage to output the driving signal to the (n+2)th stage shift register, wherein the pull-up circuit is used to enable the nth clock signal In time, start to pull up the driving signal of the (n+2)th stage shift register based on the reference high voltage. The pull-down control transistor is coupled to the pull-up circuit and is controlled by the scan signal of the (n+4)th stage shift register to control the pull-up circuit to stop outputting to the (n+2) stage shift register drive signal. The pull-up control transistor is controlled by the scan signal of the (n-2)th stage shift register, its first end is coupled to the pull-up circuit, and its second end is coupled to the reference low voltage, where n is greater than or equal to 3 an integer of .

为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合附图作详细说明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

附图说明Description of drawings

图1是依照本发明一实施例的显示装置的示意图。FIG. 1 is a schematic diagram of a display device according to an embodiment of the invention.

图2是依照本发明一实施例的第n级移位暂存器的电路简图。FIG. 2 is a schematic circuit diagram of an nth stage shift register according to an embodiment of the present invention.

图3是依照本发明另一实施例的第n级移位暂存器的电路图。FIG. 3 is a circuit diagram of an nth stage shift register according to another embodiment of the present invention.

图4是依照本发明一实施例的第n级移位暂存器的运行时序图。FIG. 4 is an operation timing diagram of an nth stage shift register according to an embodiment of the present invention.

图5是依照本发明另一实施例的第n级移位暂存器的运行时序图。FIG. 5 is an operation timing diagram of an nth stage shift register according to another embodiment of the present invention.

图6是依照本发明另一实施例的第n级移位暂存器的电路图。FIG. 6 is a circuit diagram of an nth stage shift register according to another embodiment of the present invention.

附图标记说明:Explanation of reference signs:

100:显示装置100: display device

110:移位暂存装置110: shift temporary storage device

120:显示面板120: display panel

130:上拉电路130: pull-up circuit

140:下拉电路140: Pull-down circuit

150:第一稳压电路150: The first voltage regulator circuit

160:第二稳压电路160: Second voltage regulator circuit

C:电容C: Capacitance

DT:驱动晶体管DT: drive transistor

G1~G(N):扫描信号G1~G(N): scanning signal

HC1~HCN:时钟信号HC1~HCN: clock signal

LC1:第一稳压时钟信号LC1: the first regulated clock signal

LC2:第二稳压时钟信号LC2: Second regulated clock signal

SR1~SRN、300、300’:移位暂存器SR1~SRN, 300, 300’: shift register

ST(n):启动电压ST(n): starting voltage

T1:第一上拉晶体管T1: first pull-up transistor

T2:第二上拉晶体管T2: second pull-up transistor

T3:上拉控制晶体管T3: pull-up control transistor

T4:下拉控制晶体管T4: pull-down control transistor

T5:第一下拉晶体管T5: first pull-down transistor

T6:第二下拉晶体管T6: second pull-down transistor

T7~T12、T13~T18:晶体管T7~T12, T13~T18: Transistors

Q(1)~Q(N):驱动信号Q(1)~Q(N): drive signal

VGH:参考高电压VGH: reference high voltage

VSS:参考低电压VSS: reference low voltage

V1、V2、V21、V3:电压电平V1, V2, V21, V3: voltage levels

具体实施方式Detailed ways

图1是依照本发明一实施例的显示装置的示意图。请参照图1,显示装置100至少包括移位暂存装置110与显示面板120。移位暂存装置110可利用栅极驱动电路基板技术(gateon array,GOA)直接形成于显示面板120的玻璃基板上,用以序列提供扫描信号G(n)至显示面板120内的多条扫描线。移位暂存装置110内具有多级电路架构实质上相同且彼此串接在一起的移位暂存器SR1~SRN。这些移位暂存器SR1~SRN会根据多个时钟信号HC1~HCN分别输出对应的扫描信号G1~G(N)至显示面板120。举例来说,第n级移位暂存器是根据时钟信号HC(n)输出扫描信号G(n),其中扫描信号G(n)的上升缘会实质地对齐对应的时钟信号HC(n)的上升缘。FIG. 1 is a schematic diagram of a display device according to an embodiment of the invention. Referring to FIG. 1 , the display device 100 at least includes a shift register 110 and a display panel 120 . The shift register device 110 can be directly formed on the glass substrate of the display panel 120 by utilizing gate drive circuit substrate technology (gateon array, GOA), and is used to sequentially provide the scan signal G(n) to multiple scans in the display panel 120 Wire. The shift register device 110 has multi-stage shift registers SR1 - SRN which have substantially the same circuit structure and are connected in series. These shift registers SR1 - SRN output corresponding scan signals G1 - G(N) to the display panel 120 respectively according to a plurality of clock signals HC1 - HCN. For example, the nth stage shift register outputs the scan signal G(n) according to the clock signal HC(n), wherein the rising edge of the scan signal G(n) is substantially aligned with the corresponding clock signal HC(n) rising edge.

在下文会进一步描述每一级移位暂存器SR1~SRN的各元件间的耦接关系及运行原理。The coupling relationship and operating principle among the components of each stage of shift registers SR1 - SRN will be further described below.

图2是依照本发明一实施例的第n级移位暂存器的电路简图。请搭配图1参照图2,图2的实施例描述图1的第n级移位暂存器SR(n)的电路结构与其运行原理,n为大于或等于3的整数。图1中的其余移位暂存器的电路结构与其运行原理皆与图2的实施例类似,因此不再加以赘述。FIG. 2 is a schematic circuit diagram of an nth stage shift register according to an embodiment of the present invention. Please refer to FIG. 2 in conjunction with FIG. 1 . The embodiment in FIG. 2 describes the circuit structure and operating principle of the nth stage shift register SR(n) in FIG. 1 , where n is an integer greater than or equal to 3. The circuit structures and operating principles of the rest of the shift registers in FIG. 1 are similar to those in the embodiment in FIG. 2 , so details are not repeated here.

在图2中,第n级移位暂存器SR(n)至少包括驱动晶体管DT、上拉电路130、上拉控制晶体管T3与下拉控制晶体管T4。在本实施例中,上拉电路130是由第一上拉晶体管T1与第二上拉晶体管T2所构成。驱动晶体管DT受控于本级的驱动信号Q(n),其栅极从第(n-2)级移位暂存器SR(n-2)接收驱动信号Q(n),且第一端接收该第n个时钟信号HC(n),第二端输出对应的第n级扫描信号G(n)。上拉电路130受控于驱动信号Q(n)并耦接参考高电压VGH。上拉电路130会输出给第(n+2)级移位暂存器SR(n+2)的驱动信号Q(n+2)并且在第n个时钟信号HC(n)的使能时间中基于参考高电压VGH开始上拉驱动信号Q(n+2)。参考高电压VGH例如为直流高电压。In FIG. 2 , the nth stage shift register SR(n) at least includes a driving transistor DT, a pull-up circuit 130 , a pull-up control transistor T3 and a pull-down control transistor T4 . In this embodiment, the pull-up circuit 130 is composed of a first pull-up transistor T1 and a second pull-up transistor T2. The driving transistor DT is controlled by the driving signal Q(n) of this stage, and its gate receives the driving signal Q(n) from the shift register SR(n-2) of the (n-2)th stage, and the first terminal After receiving the nth clock signal HC(n), the second terminal outputs the corresponding nth level scanning signal G(n). The pull-up circuit 130 is controlled by the driving signal Q(n) and coupled to the reference high voltage VGH. The pull-up circuit 130 will output the driving signal Q(n+2) to the (n+2)th stage shift register SR(n+2) and in the enable time of the nth clock signal HC(n) The driving signal Q(n+2) is pulled up based on the reference high voltage VGH. The reference high voltage VGH is, for example, a DC high voltage.

下拉控制晶体管T4耦接上拉电路130且受控于第(n+4)级移位暂存器的扫描信号G(n+4)。下拉控制晶体管T4可以控制上拉电路130停止输出给第(n+2)级移位暂存器SR(n+2)的驱动信号Q(n+2)。上拉控制晶体管T3受控于第(n-2)级移位暂存器SR(n-2)的扫描信号G(n-2),其第一端耦接上拉电路130,其第二端耦接参考低电压VSS。The pull-down control transistor T4 is coupled to the pull-up circuit 130 and is controlled by the scan signal G(n+4) of the (n+4)th shift register. The pull-down control transistor T4 can control the pull-up circuit 130 to stop outputting the driving signal Q(n+2) to the (n+2)th shift register SR(n+2). The pull-up control transistor T3 is controlled by the scan signal G(n-2) of the (n-2)th stage shift register SR(n-2), its first end is coupled to the pull-up circuit 130, and its second The terminal is coupled to the reference low voltage VSS.

在本实施例中,在上拉电路130中,第一上拉晶体管T1受控于驱动信号Q(n),其第一端耦接参考高电压VGH,其第二端提供启动电压ST(n)。第二上拉晶体管T2的第一端与栅极端耦接在一起,并且还耦接第一上拉晶体管T1的第二端以接收启动电压ST(n)。第二上拉晶体管T2的栅极端还耦接上拉控制晶体管T3的第一端。第二上拉晶体管T2的第二端输出给第(n+2)级移位暂存器SR(n+2)的驱动信号Q(n+2)。In this embodiment, in the pull-up circuit 130, the first pull-up transistor T1 is controlled by the driving signal Q(n), its first terminal is coupled to the reference high voltage VGH, and its second terminal provides the start-up voltage ST(n ). The first terminal of the second pull-up transistor T2 is coupled to the gate terminal, and is also coupled to the second terminal of the first pull-up transistor T1 to receive the start-up voltage ST(n). The gate terminal of the second pull-up transistor T2 is also coupled to the first terminal of the pull-up control transistor T3. The second terminal of the second pull-up transistor T2 outputs the driving signal Q(n+2) to the (n+2)th shift register SR(n+2).

特别说明的是,上拉控制晶体管T3的尺寸会不同于第一上拉晶体管T1的尺寸。例如,上拉控制晶体管T3的通道宽度会大于第一上拉晶体管T1的通道宽度。如此一来,当第一上拉晶体管T1与上拉控制晶体管T3同时导通的时候,启动电压ST(n)会被参考低电压VSS下拉而维持在参考低电压VSS的电压电平,因此第二上拉晶体管T2不会提早被导通。In particular, the size of the pull-up control transistor T3 is different from the size of the first pull-up transistor T1. For example, the channel width of the pull-up control transistor T3 is greater than the channel width of the first pull-up transistor T1. In this way, when the first pull-up transistor T1 and the pull-up control transistor T3 are turned on at the same time, the start-up voltage ST(n) will be pulled down by the reference low voltage VSS to maintain the voltage level of the reference low voltage VSS, so the first The second pull-up transistor T2 will not be turned on early.

图3是依照本发明另一实施例的第n级移位暂存器的电路图。图3的第n级移位暂存器300可适用于图2的第n级移位暂存器SR(n)。移位暂存器300还包括下拉电路140、第一稳压电路150与第二稳压电路160。FIG. 3 is a circuit diagram of an nth stage shift register according to another embodiment of the present invention. The nth stage shift register 300 in FIG. 3 is applicable to the nth stage shift register SR(n) in FIG. 2 . The shift register 300 further includes a pull-down circuit 140 , a first voltage stabilizing circuit 150 and a second voltage stabilizing circuit 160 .

下拉电路140耦接于参考低电压VSS与驱动晶体管DT的第二端之间。下拉电路140会受控于该第(n+4)级移位暂存器的扫描信号G(n+4),用以下拉第n级移位暂存器300的扫描信号G(n)。The pull-down circuit 140 is coupled between the reference low voltage VSS and the second terminal of the driving transistor DT. The pull-down circuit 140 is controlled by the scanning signal G(n+4) of the (n+4)th stage shift register to pull down the scanning signal G(n) of the nth stage shift register 300 .

下拉电路140包括第一下拉晶体管T5与第二下拉晶体管T6。第一下拉晶体管T5受控于第(n+4)级移位暂存器的扫描信号G(n+4),其第一端耦接驱动晶体管DT的栅极端,其第二端耦接参考低电压VSS。第二下拉晶体管T6也受控于第(n+4)级移位暂存器的扫描信号G(n+4),其第一端耦接驱动晶体管DT的第二端,其第二端也耦接参考低电压VSS。The pull-down circuit 140 includes a first pull-down transistor T5 and a second pull-down transistor T6. The first pull-down transistor T5 is controlled by the scan signal G(n+4) of the (n+4) shift register, its first end is coupled to the gate end of the drive transistor DT, and its second end is coupled to Referenced to low voltage VSS. The second pull-down transistor T6 is also controlled by the scan signal G(n+4) of the (n+4)th stage shift register, its first end is coupled to the second end of the drive transistor DT, and its second end is also Coupled to the reference low voltage VSS.

第一稳压电路150包括多个晶体管T7~T12。晶体管T7的第一端与栅极端耦接在一起,并且接收第一稳压时钟信号LC1。晶体管T8耦接于晶体管T7的第二端与参考低电压VSS之间,并且受控于驱动信号Q(n)。晶体管T9的第一端与栅极端分别耦接晶体管T7的第一端与第二端,晶体管T9的第二端串接晶体管T10。晶体管T10的另一端则耦接参考低电压VSS,其中晶体管T10的栅极端同样接收驱动信号Q(n)。晶体管T11与晶体管T12都受控于晶体管T9的第二端的电压电平,并且其第二端都耦接参考低电压VSS。但是晶体管T11的第一端接收驱动信号Q(n),晶体管T12的第一端耦接驱动晶体管DT的第二端以接收扫描信号G(n),同时耦接电容C,而电容C的另一端接收驱动信号Q(n)。也就是说,电容C两端的电位差会反应驱动信号Q(n)与扫描信号G(n)之间的电位差。当晶体管T12导通时,扫描信号G(n)会被下拉至参考低电压VSS。The first voltage stabilizing circuit 150 includes a plurality of transistors T7 - T12 . The first terminal of the transistor T7 is coupled to the gate terminal, and receives the first regulated clock signal LC1 . The transistor T8 is coupled between the second terminal of the transistor T7 and the reference low voltage VSS, and is controlled by the driving signal Q(n). The first terminal and the gate terminal of the transistor T9 are respectively coupled to the first terminal and the second terminal of the transistor T7, and the second terminal of the transistor T9 is connected to the transistor T10 in series. The other terminal of the transistor T10 is coupled to the reference low voltage VSS, wherein the gate terminal of the transistor T10 also receives the driving signal Q(n). Both the transistor T11 and the transistor T12 are controlled by the voltage level of the second terminal of the transistor T9, and the second terminal is coupled to the reference low voltage VSS. However, the first end of the transistor T11 receives the driving signal Q(n), the first end of the transistor T12 is coupled to the second end of the driving transistor DT to receive the scanning signal G(n), and is coupled to the capacitor C at the same time, and the other end of the capacitor C One end receives the driving signal Q(n). That is to say, the potential difference between the two ends of the capacitor C will reflect the potential difference between the driving signal Q(n) and the scanning signal G(n). When the transistor T12 is turned on, the scan signal G(n) will be pulled down to the reference low voltage VSS.

第二稳压电路160包括多个晶体管T13~T18。第二稳压电路160的电路结构与第一稳压电路150类似。晶体管T13的第一端与栅极端耦接在一起,并且接收第二稳压时钟信号LC2。晶体管T14耦接于晶体管T13的第二端与参考低电压VSS之间,并且受控于驱动信号Q(n)。晶体管T15的第一端与栅极端分别耦接晶体管T13的第一端与第二端,晶体管T15的第二端串接晶体管T16。晶体管T16的另一端则耦接参考低电压VSS,其中晶体管T16的栅极端同样接收驱动信号Q(n)。晶体管T17与晶体管T18的栅极端都耦接晶体管T15的第二端与晶体管T16的第一端之间,并且晶体管T17与晶体管T18的第二端都耦接参考低电压VSS。晶体管T17的第一端接收驱动信号Q(n)。晶体管T18的第一端则耦接驱动晶体管DT的第二端。当晶体管T18导通时,扫描信号G(n)会被下拉至参考低电压VSS。The second voltage stabilizing circuit 160 includes a plurality of transistors T13 - T18 . The circuit structure of the second voltage stabilizing circuit 160 is similar to that of the first voltage stabilizing circuit 150 . The first terminal and the gate terminal of the transistor T13 are coupled together, and receive the second regulated clock signal LC2 . The transistor T14 is coupled between the second terminal of the transistor T13 and the reference low voltage VSS, and is controlled by the driving signal Q(n). The first terminal and the gate terminal of the transistor T15 are respectively coupled to the first terminal and the second terminal of the transistor T13, and the second terminal of the transistor T15 is connected to the transistor T16 in series. The other terminal of the transistor T16 is coupled to the reference low voltage VSS, wherein the gate terminal of the transistor T16 also receives the driving signal Q(n). The gate terminals of the transistor T17 and the transistor T18 are both coupled between the second terminal of the transistor T15 and the first terminal of the transistor T16 , and the second terminals of the transistor T17 and the transistor T18 are both coupled to the reference low voltage VSS. The first terminal of the transistor T17 receives the driving signal Q(n). The first terminal of the transistor T18 is coupled to the second terminal of the driving transistor DT. When the transistor T18 is turned on, the scan signal G(n) will be pulled down to the reference low voltage VSS.

进一步来说,第一稳压电路150与第二稳压电路160都耦接驱动晶体管DT的第二端且接收驱动信号Q(n)。第一稳压电路150与第二稳压电路160可以根据第一稳压时钟信号LC1与第二稳压时钟信号LC2相互交替运行,以根据驱动信号Q(n)稳压扫描信号G(n)。Further, both the first voltage stabilizing circuit 150 and the second voltage stabilizing circuit 160 are coupled to the second end of the driving transistor DT and receive the driving signal Q(n). The first stabilizing circuit 150 and the second stabilizing circuit 160 can operate alternately according to the first stabilizing clock signal LC1 and the second stabilizing clock signal LC2, so as to stabilize the scanning signal G(n) according to the driving signal Q(n). .

图4是依照本发明一实施例的第n级移位暂存器的运行时序图。请同时参照图1、图3与图4,在本实施例中,移位暂存装置110所提供的扫描信号G(n)可以被设定成对显示面板120中的扫描线进行预充电或是不对这些扫描线预充电。然而在图4的实施例中,移位暂存装置110所提供的扫描信号G(n)是以不对显示面板120进行预充电的时序为例,并且图4仅以第3级移位暂存器SR3作为说明(n=3)。另外补充,本说明书中的晶体管都是以NMOS晶体管的方式实施,因此信号的逻辑高电平(High或1)表示可使能。但本发明并不限制晶体管的实施方式。FIG. 4 is an operation timing diagram of an nth stage shift register according to an embodiment of the present invention. Please refer to FIG. 1 , FIG. 3 and FIG. 4 at the same time. In this embodiment, the scan signal G(n) provided by the shift register 110 can be set to precharge the scan lines in the display panel 120 or is not to precharge these scan lines. However, in the embodiment of FIG. 4 , the scanning signal G(n) provided by the shift register 110 is an example of a sequence in which the display panel 120 is not precharged, and FIG. 4 only uses the third-level shift register SR3 as an illustration (n=3). In addition, the transistors in this specification are all implemented in the form of NMOS transistors, so the logic high level (High or 1) of the signal indicates that it can be enabled. However, the present invention does not limit the embodiment of the transistor.

由于在本实施例中,显示面板120的驱动方式是非预充电模式,因此图4中显示的这些时钟信号HC1~HC6的使能时间彼此之间不重叠,移位暂存装置110所提供的扫描信号G(1)~G(6)的使能时间彼此之间也不重叠。Since in this embodiment, the driving mode of the display panel 120 is a non-precharge mode, the enabling times of these clock signals HC1-HC6 shown in FIG. The enabling times of the signals G( 1 )˜G( 6 ) do not overlap with each other.

在时钟信号HC1的使能时间中,即时间t1~t2,第1级移位暂存器SR1被使能,输出的扫描信号G(1)也处于使能状态,并且驱动信号Q(3)从低电平,如图4所标示的电压电平V1,被改变至高电平,如图4所标示的电压电平V2。相应地,第3级移位暂存器SR3中的第一上拉晶体管T1与上拉控制晶体管T3被导通。因为第一上拉晶体管T1的尺寸小于上拉控制晶体管T3的尺寸,所以即使两者同时导通,第二上拉晶体管T2的栅极端上的启动电压ST(3)仍会被参考低电压VSS下拉,造成第二上拉晶体管T2不导通。During the enabling time of the clock signal HC1, that is, time t1~t2, the first-stage shift register SR1 is enabled, and the output scanning signal G(1) is also in the enabled state, and the driving signal Q(3) From a low level, voltage level V1 indicated in FIG. 4 , is changed to a high level, voltage level V2 indicated in FIG. 4 . Correspondingly, the first pull-up transistor T1 and the pull-up control transistor T3 in the third-stage shift register SR3 are turned on. Because the size of the first pull-up transistor T1 is smaller than that of the pull-up control transistor T3, even if both are turned on at the same time, the start-up voltage ST(3) on the gate terminal of the second pull-up transistor T2 is still referenced to the low voltage VSS pulled down, causing the second pull-up transistor T2 to be non-conductive.

在时钟信号HC2的使能时间中(时间t2~t3),上拉控制晶体管T3被扫描信号G(1)关闭,驱动信号Q(3)被保持在不小于电压电平V2的电压电平V21(在本实施例中,电压电平V21大于电压电平V2),第一上拉晶体管T1仍旧维持导通,第二上拉晶体管T2的栅极端开始被参考高电压VGH充电,但此时启动电压ST(3)仍未超过第二上拉晶体管T2的临界电压,第二上拉晶体管T2还是处在关闭状态。During the enabling time of the clock signal HC2 (time t2~t3), the pull-up control transistor T3 is turned off by the scanning signal G(1), and the driving signal Q(3) is kept at a voltage level V21 not less than the voltage level V2 (In this embodiment, the voltage level V21 is greater than the voltage level V2), the first pull-up transistor T1 is still turned on, and the gate terminal of the second pull-up transistor T2 starts to be charged by the reference high voltage VGH, but at this time The voltage ST(3) still does not exceed the threshold voltage of the second pull-up transistor T2, and the second pull-up transistor T2 is still in the off state.

在时钟信号HC3的使能时间中(时间t3~t4),上拉控制晶体管T3维持关闭,第一上拉晶体管T1维持导通,启动电压ST(3)被参考高电压VGH充电到高电平状态而导通第二上拉晶体管T2。导通的第二上拉晶体管T2会根据启动电压ST(3)开始上拉第5级移位暂存器SR5的驱动信号Q(5)。如图4显示,驱动信号Q(5)开始从低电平(电压电平V1)被上拉到高电平(电压电平V2)。During the enabling time of the clock signal HC3 (time t3~t4), the pull-up control transistor T3 remains turned off, the first pull-up transistor T1 remains turned on, and the start-up voltage ST(3) is charged to a high level by the reference high voltage VGH state to turn on the second pull-up transistor T2. The turned-on second pull-up transistor T2 starts to pull up the driving signal Q(5) of the fifth-stage shift register SR5 according to the start-up voltage ST(3). As shown in FIG. 4 , the driving signal Q ( 5 ) starts to be pulled up from a low level (voltage level V1 ) to a high level (voltage level V2 ).

在这段时间中,时钟信号HC3处于高电平状态,驱动晶体管DT所输出的扫描信号G(3)也是位于高电平状态,驱动信号Q(3)被耦合到更高的电压电平,如图4所标示的电压电平V3。另外,第5级移位暂存器SR5中的第一上拉晶体管T1与上拉控制晶体管T3会分别被驱动信号Q(5)与扫描信号G(3)导通,请参考上面关于时间t1~t2的实施说明。During this period, the clock signal HC3 is in a high level state, the scanning signal G(3) output by the driving transistor DT is also in a high level state, and the driving signal Q(3) is coupled to a higher voltage level, The voltage level V3 is indicated in FIG. 4 . In addition, the first pull-up transistor T1 and the pull-up control transistor T3 in the fifth-stage shift register SR5 are respectively turned on by the driving signal Q(5) and the scanning signal G(3). Please refer to the above about time t1 Implementation instructions for ~t2.

在时钟信号HC4的使能时间中(时间t4~t5),上拉控制晶体管T3维持关闭,驱动信号Q(3)的电压电平降低,回到电压电平V21,第一上拉晶体管T1维持导通。启动电压ST(3)会被参考高电压VGH维持在高电平状态,第二上拉晶体管T2保持导通,因此驱动信号Q(5)不会处在浮动状态(Floating),而是由启动电压ST(3)继续维持在高电平状态。During the enabling time of the clock signal HC4 (time t4-t5), the pull-up control transistor T3 remains closed, the voltage level of the driving signal Q(3) decreases, and returns to the voltage level V21, and the first pull-up transistor T1 maintains conduction. The start-up voltage ST(3) will be maintained in a high-level state by the reference high voltage VGH, and the second pull-up transistor T2 will remain on, so the driving signal Q(5) will not be in a floating state (Floating), but will be activated by the The voltage ST(3) continues to maintain a high level state.

直到时间t7(第7级扫描信号G(7)的上升缘),下拉电路140以及下拉控制晶体管T4被扫描信号G(7)使能。下拉控制晶体管T4被导通后,启动电压ST(3)会被参考低电压VSS下拉,以关闭第二上拉晶体管T2。另外,驱动信号Q(3)被切换回电压电平V1。下拉电路140中的第一下拉晶体管T5与第二下拉晶体管T6被导通后,驱动晶体管DT也会对应地被关闭,扫描信号G(3)被稳定在参考低电压VSS。Until time t7 (the rising edge of the seventh-level scan signal G( 7 )), the pull-down circuit 140 and the pull-down control transistor T4 are enabled by the scan signal G( 7 ). After the pull-down control transistor T4 is turned on, the start-up voltage ST( 3 ) is pulled down with reference to the low voltage VSS to turn off the second pull-up transistor T2 . Additionally, drive signal Q(3) is switched back to voltage level V1. After the first pull-down transistor T5 and the second pull-down transistor T6 in the pull-down circuit 140 are turned on, the driving transistor DT is correspondingly turned off, and the scan signal G( 3 ) is stabilized at the reference low voltage VSS.

简言之,对第3级移位暂存器SR3来说,驱动信号Q(3)和扫描信号G(3)会控制第3级移位暂存器SR3输出驱动信号Q(5)给下两级移位暂存器SR5,如此类推。在时钟信号HC1的使能时间中,驱动信号Q(3)从第一电平(例如电压电平V1)被改变至第二电平(例如电压电平V2),其中第二电平大于第一电平。在时钟信号HC2的使能时间中,驱动信号Q(3)被保持在不小于第二电平的状态(例如电压电平V21);在时钟信号HC3的使能时间中,驱动信号Q(3)被改变至第三电平(例如电压电平V3),其中第三电平大于第二电平;在时钟信号HC4至时钟信号HC6的使能时间(时间t4~t7)中,驱动信号Q(3)从第三电平被切换至不小于第二电平的电压电平(例如回到电压电平V21);在第(n+4)级移位暂存器的扫描信号G(7)的使能时间中,驱动信号Q(3)被切换回第一电平。In short, for the third-stage shift register SR3, the drive signal Q(3) and the scan signal G(3) will control the third-stage shift register SR3 to output the drive signal Q(5) to the next Two-stage shift register SR5, and so on. During the enabling time of the clock signal HC1, the drive signal Q(3) is changed from a first level (such as a voltage level V1) to a second level (such as a voltage level V2), wherein the second level is greater than the first level One level. During the enabling time of the clock signal HC2, the driving signal Q(3) is maintained at a state not less than the second level (for example, voltage level V21); during the enabling time of the clock signal HC3, the driving signal Q(3) ) is changed to a third level (such as voltage level V3), wherein the third level is greater than the second level; during the enabling time (time t4-t7) of the clock signal HC4 to the clock signal HC6, the driving signal Q (3) Switched from the third level to a voltage level not less than the second level (for example, back to the voltage level V21); the scan signal G (7 ) during the enabling time, the driving signal Q(3) is switched back to the first level.

在此说明的是,在本实施例中,当这些时钟信号HC1~HCN的使能时间彼此不重叠并且第n级移位暂存器会输出给第n+2级移位暂存器的驱动信号Q(n+2)时,对第n级移位暂存器来说,在时钟信号HC(n)的使能时间中,驱动信号Q(n+2)被预充电,在时钟信号HC(n+1)的使能时间中,上拉控制晶体管T3被控制以使上拉电路130能够保持驱动信号Q(n+2)被上拉后的电压电平。在这段时间中,驱动信号Q(n+2)能够继续被充电而不是处在浮动状态,因此第二上拉晶体管T2的第一端与第二端之间的跨电压(漏极-源极间电压,VDS)可以有效下降,能够降低漏电流并且增加移位暂存器的驱动力。It is explained here that, in this embodiment, when the enable times of these clock signals HC1˜HCN do not overlap with each other and the shift register of the nth stage will output to the driver of the shift register of the n+2th stage When the signal Q(n+2), for the shift register of the nth stage, during the enable time of the clock signal HC(n), the driving signal Q(n+2) is precharged, and the clock signal HC During the enable time of (n+1), the pull-up control transistor T3 is controlled so that the pull-up circuit 130 can maintain the voltage level of the driving signal Q(n+2) after being pulled up. During this time, the driving signal Q(n+2) can continue to be charged instead of being in a floating state, so the voltage across the first terminal and the second terminal of the second pull-up transistor T2 (drain-source The inter-electrode voltage, V DS ) can be effectively reduced, which can reduce the leakage current and increase the driving force of the shift register.

图5是依照本发明另一实施例的第n级移位暂存器的运行时序图。请同时参照图1、图3与图5,在本实施例中,移位暂存装置110所提供的扫描信号G(n)被设定成对显示面板120中的扫描线进行预充电。以下同样以第3级移位暂存器SR3作为说明(n=3)。FIG. 5 is an operation timing diagram of an nth stage shift register according to another embodiment of the present invention. Please refer to FIG. 1 , FIG. 3 and FIG. 5 at the same time. In this embodiment, the scan signal G(n) provided by the shift register 110 is set to precharge the scan lines in the display panel 120 . Hereinafter, the third-stage shift register SR3 is also used as an illustration (n=3).

由于要对显示面板120中的扫描线进行预充电,图5中的这些时钟信号HC1~HC6的使能时间会有部分重叠。同样地,因为扫描信号G(n)的上升缘实质地对齐对应的时钟信号HC(n)的上升缘,所以扫描信号G(1)~G(6)的使能时间也会有部分重叠。在本实施例中,第n个时钟信号HC(n)与下一个时钟信号HC(n+1)有1/2的使能时间重叠。Due to the need to precharge the scan lines in the display panel 120 , the enable times of the clock signals HC1 - HC6 in FIG. 5 may partially overlap. Likewise, because the rising edge of the scanning signal G(n) is substantially aligned with the rising edge of the corresponding clock signal HC(n), the enabling times of the scanning signals G(1)-G(6) also partially overlap. In this embodiment, the enabling time of the nth clock signal HC(n) overlaps with the next clock signal HC(n+1) by 1/2.

如图5所示,在时间t9~时间t10,在第3级移位暂存器SR3中,上拉控制晶体管T3处于关闭状态且上拉电路130被使能,驱动信号Q(5)的电压电平被预充到高电平,直到时间t12,其中,在时间t10~时间t11,由于扫描信号G(5)是处于使能电平,驱动信号Q(5)被耦合到更高的电压电平。As shown in FIG. 5, at time t9~time t10, in the third-stage shift register SR3, the pull-up control transistor T3 is in the off state and the pull-up circuit 130 is enabled, and the voltage of the drive signal Q(5) The level is precharged to a high level until time t12, wherein, at time t10 to time t11, since the scanning signal G(5) is at the enable level, the driving signal Q(5) is coupled to a higher voltage level.

根据图4与图5的实施例,通过改变时钟信号HC1~HCN的时序,移位暂存器300可以对显示面板110的扫描线进行预充电或是非预充电的驱动。尤其在非预充电的驱动方式中,由移位暂存器300组成的移位暂存装置110能够避免内部的驱动信号Q(n)处在浮动的状态,有效的降低漏电流。According to the embodiment shown in FIG. 4 and FIG. 5 , by changing the timing of the clock signals HC1 -HCN , the shift register 300 can drive the scan lines of the display panel 110 with or without pre-charging. Especially in the non-precharge driving mode, the shift register device 110 composed of the shift register 300 can prevent the internal drive signal Q(n) from being in a floating state, effectively reducing the leakage current.

图6是依照本发明另一实施例的第n级移位暂存器的电路图。图6的第n级移位暂存器300’可适用于图2的第n级移位暂存器SR(n)并与图3的第n级移位暂存器300相似。移位暂存器300’与移位暂存器300的差别在于上拉电路130的内部结构略有差异。FIG. 6 is a circuit diagram of an nth stage shift register according to another embodiment of the present invention. The nth stage shift register 300' in FIG. 6 is applicable to the nth stage shift register SR(n) in FIG. 2 and is similar to the nth stage shift register 300 in FIG. 3 . The difference between the shift register 300' and the shift register 300 is that the internal structure of the pull-up circuit 130 is slightly different.

在图6的实施例中,第二上拉晶体管T2的第一端与栅极端没有耦接在一起,第一端是耦接第一上拉晶体管T1的第一端以接收参考高电压VGH。其余的电路架构以及相关的驱动方式,本领域技术人员可从上面的说明获致足够的启示、建议与实施说明,因此不再赘述。In the embodiment of FIG. 6 , the first terminal of the second pull-up transistor T2 is not coupled to the gate terminal, and the first terminal is coupled to the first terminal of the first pull-up transistor T1 to receive the reference high voltage VGH. Those skilled in the art can obtain sufficient enlightenment, suggestions and implementation descriptions from the above descriptions for the rest of the circuit structure and related driving methods, so no more details are given here.

综上所述,本发明的移位暂存装置通过另外引入参考高电压,让上拉电路可以根据参考高电压来保持移位暂存器的驱动信号的电压电平,避免有浮动的空窗期。因此能够降低移位暂存装置的漏电流并增加移位暂存器的驱动能力与稳定性。本发明提出的显示装置可采用上述的移位暂存装置,以提升扫描信号的稳定度。In summary, the shift register device of the present invention additionally introduces a reference high voltage, so that the pull-up circuit can maintain the voltage level of the drive signal of the shift register according to the reference high voltage, avoiding floating empty windows Expect. Therefore, the leakage current of the shift register device can be reduced and the driving capability and stability of the shift register can be increased. The display device proposed by the present invention can adopt the above-mentioned shift register device to improve the stability of the scanning signal.

虽然本发明已以实施例公开如上,然其并非用以限定本发明,任何所属技术领域中技术人员,在不脱离本发明的构思和范围内,当可作些许的变动与润饰,故本发明的保护范围当视权利要求所界定者为准。Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and modifications without departing from the concept and scope of the present invention. Therefore, the present invention The scope of protection shall prevail as defined by the claims.

Claims (12)

1.一种移位暂存装置,包括:1. A shift temporary storage device, comprising: 多级彼此串接在一起的移位暂存器,根据多个时钟信号输出多个扫描信号至一显示面板,其中第n级移位暂存器根据第n个时钟信号输出该扫描信号,且包括:Multi-stage shift registers connected in series output multiple scan signals to a display panel according to multiple clock signals, wherein the nth shift register outputs the scan signals according to the nth clock signal, and include: 一驱动晶体管,受控于一本级驱动信号,其第一端接收该第n个时钟信号,其第二端输出该第n级移位暂存器的扫描信号;A drive transistor, controlled by a primary drive signal, its first end receives the nth clock signal, and its second end outputs the scan signal of the nth stage shift register; 一上拉电路,受控于该本级驱动信号并耦接一参考高电压,用以输出给第(n+2)级移位暂存器的驱动信号,其中该上拉电路用以在该第n个时钟信号的使能时间中基于该参考高电压开始上拉该第(n+2)级移位暂存器的驱动信号;A pull-up circuit, controlled by the drive signal of the current stage and coupled to a reference high voltage, is used to output the drive signal to the (n+2)th stage shift register, wherein the pull-up circuit is used for the Starting to pull up the driving signal of the (n+2)th stage shift register based on the reference high voltage during the enabling time of the nth clock signal; 一下拉控制晶体管,耦接该上拉电路且受控于第(n+4)级移位暂存器的扫描信号,用以控制该上拉电路停止输出给该第(n+2)级移位暂存器的驱动信号;以及A pull-up control transistor, coupled to the pull-up circuit and controlled by the scan signal of the (n+4) shift register, is used to control the pull-up circuit to stop outputting to the (n+2) shift register. drive signals for bit registers; and 一上拉控制晶体管,受控于第(n-2)级移位暂存器的扫描信号,其第一端耦接该上拉电路,其第二端耦接一参考低电压,A pull-up control transistor, controlled by the scanning signal of the (n-2)th stage shift register, its first end is coupled to the pull-up circuit, its second end is coupled to a reference low voltage, 其中n为大于或等于3的整数。Where n is an integer greater than or equal to 3. 2.如权利要求1所述的移位暂存装置,其中,当该些时钟信号的使能时间彼此不重叠时,该上拉控制晶体管被控制以使该上拉电路在第(n+1)个时钟信号的使能时间中保持该第(n+2)级移位暂存器的驱动信号被上拉后的电压电平。2. The shift register device as claimed in claim 1, wherein when the enabling times of the clock signals do not overlap with each other, the pull-up control transistor is controlled so that the pull-up circuit at the (n+1th The voltage level after the drive signal of the (n+2)th stage shift register is pulled up is maintained during the enabling time of the ) clock signal. 3.如权利要求1所述的移位暂存装置,其中该上拉电路包括:3. The shift register device as claimed in claim 1, wherein the pull-up circuit comprises: 一第一上拉晶体管,受控于该本级驱动信号,其第一端耦接该参考高电压,其第二端提供一启动电压;以及A first pull-up transistor, controlled by the driving signal of the current stage, its first terminal is coupled to the reference high voltage, and its second terminal provides a start-up voltage; and 一第二上拉晶体管,其栅极端耦接该第一上拉晶体管的第二端与该上拉控制晶体管的第一端,且接收该启动电压,其第一端与其栅极端耦接在一起或者其第一端耦接该参考高电压,以及其第二端输出给该第(n+2)级移位暂存器的驱动信号。A second pull-up transistor, the gate terminal of which is coupled to the second terminal of the first pull-up transistor and the first terminal of the pull-up control transistor, and receives the startup voltage, and whose first terminal is coupled together with the gate terminal Or its first end is coupled to the reference high voltage, and its second end is output to the driving signal of the (n+2)th stage shift register. 4.如权利要求3所述的移位暂存装置,其中该上拉控制晶体管的尺寸不同于该第一上拉晶体管的尺寸。4. The shift register device as claimed in claim 3, wherein the size of the pull-up control transistor is different from that of the first pull-up transistor. 5.如权利要求4所述的移位暂存装置,其中该上拉控制晶体管的通道宽度大于该第一上拉晶体管的通道宽度。5. The shift register device as claimed in claim 4, wherein the channel width of the pull-up control transistor is larger than the channel width of the first pull-up transistor. 6.如权利要求3所述的移位暂存装置,其中,在第(n+1)个时钟信号的使能时间中,该上拉控制晶体管被关闭,且该第一上拉晶体管与该第二上拉晶体管被导通,该第(n+2)级移位暂存器的驱动信号持续被该参考高电压上拉。6. The shift register device as claimed in claim 3, wherein, during the enable time of the (n+1)th clock signal, the pull-up control transistor is turned off, and the first pull-up transistor and the The second pull-up transistor is turned on, and the driving signal of the (n+2)th shift register is continuously pulled up by the reference high voltage. 7.如权利要求1所述的移位暂存装置,其中该第n级移位暂存器还包括:7. The shift register device as claimed in claim 1, wherein the nth stage shift register further comprises: 一下拉电路,耦接于该参考低电压与该驱动晶体管的第二端之间且受控于该第(n+4)级移位暂存器的扫描信号,用以下拉该第n级移位暂存器的扫描信号。A pull-down circuit, coupled between the reference low voltage and the second terminal of the drive transistor and controlled by the scan signal of the (n+4)th stage shift register, is used to pull down the nth stage shift register Scan signal for the bit register. 8.如权利要求7所述的移位暂存装置,其中该下拉电路包括:8. The shift register device as claimed in claim 7, wherein the pull-down circuit comprises: 一第一下拉晶体管,受控于该第(n+4)级移位暂存器的扫描信号,其第一端耦接该驱动晶体管的栅极端,其第二端耦接该参考低电压;以及A first pull-down transistor, controlled by the scanning signal of the (n+4)th stage shift register, its first terminal is coupled to the gate terminal of the driving transistor, and its second terminal is coupled to the reference low voltage ;as well as 一第二下拉晶体管,受控于该第(n+4)级移位暂存器的扫描信号,其第一端耦接该驱动晶体管的第二端,其第二端耦接该参考低电压。A second pull-down transistor, controlled by the scan signal of the (n+4)th stage shift register, its first end coupled to the second end of the driving transistor, and its second end coupled to the reference low voltage . 9.如权利要求1所述的移位暂存装置,还包括:9. The shift temporary storage device as claimed in claim 1, further comprising: 一第一稳压电路与一第二稳压电路,耦接该驱动晶体管的第二端且接收该本级驱动信号,其中该第一稳压电路与该第二稳压电路用以根据该本级驱动信号稳压该第n级移位暂存器的扫描信号。A first voltage stabilizing circuit and a second voltage stabilizing circuit are coupled to the second terminal of the drive transistor and receive the driving signal of the current stage, wherein the first voltage stabilizing circuit and the second voltage stabilizing circuit are used for The level driving signal stabilizes the scan signal of the nth level shift register. 10.如权利要求1所述的移位暂存装置,其中,10. The shift temporary storage device as claimed in claim 1, wherein, 在第(n-2)个时钟信号的使能时间中,该本级驱动信号从一第一电平被改变至一第二电平,其中该第二电平大于该第一电平;During the enable time of the (n-2)th clock signal, the driving signal of the current stage is changed from a first level to a second level, wherein the second level is greater than the first level; 在第(n-1)个时钟信号的使能时间中,该本级驱动信号被保持在不小于该第二电平的状态;以及During the enabling time of the (n-1)th clock signal, the driving signal of the current stage is maintained at a state not lower than the second level; and 在该第n个时钟信号的使能时间中,该本级驱动信号被改变至一第三电平,其中该第三电平大于该第二电平。During the enabling time of the nth clock signal, the driving signal of the current stage is changed to a third level, wherein the third level is greater than the second level. 11.如权利要求1所述的移位暂存装置,其中该参考高电压为一直流高电压。11. The shift register device as claimed in claim 1, wherein the reference high voltage is a DC high voltage. 12.一种显示装置,包括:12. A display device comprising: 一显示面板;以及a display panel; and 一移位暂存装置,包括多级彼此串接在一起的移位暂存器,根据多个时钟信号分别输出一扫描信号至该显示面板,其中第n级移位暂存器根据第n个时钟信号输出该扫描信号,且包括:A shift register device, including multi-stage shift registers connected in series, respectively outputting a scan signal to the display panel according to multiple clock signals, wherein the shift register of the nth stage is based on the nth The clock signal outputs the scanning signal, and includes: 一驱动晶体管,受控于一本级驱动信号,其第一端接收该第n个时钟信号,其第二端输出该第n级移位暂存器的扫描信号;A drive transistor, controlled by a primary drive signal, its first end receives the nth clock signal, and its second end outputs the scan signal of the nth stage shift register; 一上拉电路,受控于该本级驱动信号并耦接一参考高电压,用以输出给第(n+2)级移位暂存器的驱动信号,其中该上拉电路用以在该第n个时钟信号的使能时间中基于该参考高电压开始上拉该第(n+2)级移位暂存器的驱动信号;A pull-up circuit, controlled by the drive signal of the current stage and coupled to a reference high voltage, is used to output the drive signal to the (n+2)th stage shift register, wherein the pull-up circuit is used for the Starting to pull up the driving signal of the (n+2)th stage shift register based on the reference high voltage during the enabling time of the nth clock signal; 一下拉控制晶体管,耦接该上拉电路且受控于第(n+4)级移位暂存器的扫描信号,用以控制该上拉电路停止输出给该第(n+2)级移位暂存器的驱动信号;以及A pull-up control transistor, coupled to the pull-up circuit and controlled by the scan signal of the (n+4) shift register, is used to control the pull-up circuit to stop outputting to the (n+2) shift register. drive signals for bit registers; and 一上拉控制晶体管,受控于第(n-2)级移位暂存器的扫描信号,其第一端耦接该上拉电路,其第二端耦接一参考低电压,A pull-up control transistor, controlled by the scanning signal of the (n-2)th stage shift register, its first end is coupled to the pull-up circuit, its second end is coupled to a reference low voltage, 其中n为大于或等于3的整数。Where n is an integer greater than or equal to 3.
CN201910832250.4A 2019-02-12 2019-09-04 Shift temporary storage device and display device Active CN110459163B (en)

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