CN110459163B - Shift temporary storage device and display device - Google Patents

Abstract

The invention provides a shift register device, which comprises a plurality of stages of shift registers connected in series. The nth stage shift register outputs a scan signal according to the nth clock signal. The driving transistor is controlled by the driving signal and receives the nth clock signal to output the scanning signal of the nth shift register. The pull-up circuit is controlled by the driving signal, and starts to pull up the driving signal of the (n + 2) th stage shift register based on the reference high voltage in the enabling time of the nth clock signal. The pull-down control transistor controls the pull-up circuit to stop outputting the driving signal to the (n + 2) th stage shift register. The pull-up control transistor is controlled by a scanning signal of the (n-2) th stage of shift register and is coupled with the pull-up circuit and a reference low voltage, wherein n is an integer greater than or equal to 3. A display device is also provided.

Description

Shift temporary storage device and display device

technical field

The invention relates to a display panel driving technology, and in particular to a shift temporary storage device and a display device.

Background technique

With the development of display panel technology, display screens with narrow borders have become mainstream products at present. Existing display panels can use a gate-on-array (GOA) technology to reduce the area by integrating the driving circuit on the glass substrate of the display panel.

But on the other hand, the same display panel may be applied to different series of products, so it may need to have the flexibility to match different timing settings, such as the driving timing of pre-charging or non-precharging driving timing. In order to satisfy these two driving timings at the same time, extra care is required in the design of the driving circuit. For example, the shift registers in the prior art that have a linkage relationship with each other may cause a leakage current problem due to floating driving signals. How to suppress the leakage current becomes a problem to be solved.

Contents of the invention

The invention provides a shift register and a display device, which can reduce the leakage current of the shift register and increase the driving ability and stability of the shift register.

An embodiment of the present invention provides a shift register device disposed on a substrate of a display panel. The shift register device includes multiple stages of shift registers connected in series. These shift registers output scanning signals to the display panel respectively according to multiple clock signals, wherein the shift register of the nth stage outputs scanning signals according to the nth clock signal, and includes driving transistors, pull-up circuits, pull-down control transistor with a pull-up control transistor. The driving transistor is controlled by the driving signal, its first terminal receives the nth clock signal, and its second terminal outputs the scanning signal of the nth stage shift register. The pull-up circuit is controlled by the driving signal and coupled to the reference high voltage to output the driving signal to the (n+2)th stage shift register, wherein the pull-up circuit is used to enable the nth clock signal In time, start to pull up the driving signal of the (n+2)th stage shift register based on the reference high voltage. The pull-down control transistor is coupled to the pull-up circuit and is controlled by the scan signal of the (n+4)th stage shift register to control the pull-up circuit to stop outputting to the (n+2) stage shift register drive signal. The pull-up control transistor is controlled by the scan signal of the (n-2)th stage shift register, its first end is coupled to the pull-up circuit, and its second end is coupled to the reference low voltage, where n is greater than or equal to 3 an integer of .

In an embodiment of the present invention, in the above-mentioned shift register device, when the enabling times of these clock signals do not overlap with each other, the pull-up control transistor is controlled so that the pull-up circuit The voltage level after the driving signal of the (n+2)th stage shift register is pulled up is maintained during the enabling time of the first clock signal.

In an embodiment of the present invention, the pull-up circuit of the above-mentioned shift register device includes a first pull-up transistor controlled by a driving signal, its first end is coupled to a reference high voltage, and its second end provides a start-up voltage , and a second pull-up transistor. The gate terminal of the second pull-up transistor is coupled to the second terminal of the first pull-up transistor and the first terminal of the pull-up control transistor, and receives the startup voltage, and its first terminal is coupled to its gate terminal or its first terminal It is coupled to the reference high voltage, and its second terminal is output to the driving signal of the (n+2)th stage shift register.

In an embodiment of the present invention, the size of the pull-up control transistor in the shift register device is different from the size of the first pull-up transistor.

In an embodiment of the present invention, the channel width of the pull-up control transistor in the shift register device is larger than the channel width of the first pull-up transistor.

In an embodiment of the present invention, in the above-mentioned shift register device, during the enabling time of the (n+1)th clock signal, the pull-up control transistor is turned off, and the first pull-up transistor and the first pull-up transistor The second pull-up transistor is turned on, and the driving signal of the (n+2)th shift register is continuously pulled up by the reference high voltage.

In an embodiment of the present invention, the shift register of the nth stage of the above-mentioned shift register device further includes a pull-down circuit. The pull-down circuit is coupled between the reference low voltage and the second end of the driving transistor and is controlled by the scan signal of the (n+4)th stage shift register to pull down the scanning of the nth stage shift register Signal.

In an embodiment of the present invention, the pull-down circuit of the shift register device includes a first pull-down transistor and a second pull-down transistor. The first pull-down transistor is controlled by the scan signal of the (n+4)th stage shift register, its first terminal is coupled to the gate terminal of the driving transistor, and its second terminal is coupled to the reference low voltage. The second pull-down transistor is controlled by the scan signal of the (n+4)th stage shift register, its first terminal is coupled to the second terminal of the driving transistor, and its second terminal is coupled to the reference low voltage.

In an embodiment of the present invention, the shift register device further includes a first voltage stabilizing circuit and a second voltage stabilizing circuit. The first voltage stabilizing circuit and the second voltage stabilizing circuit are coupled to the second terminal of the driving transistor and receive the driving signal, wherein the first voltage stabilizing circuit and the second voltage stabilizing circuit are used for stabilizing the nth stage shift register according to the driving signal the scanning signal of the device.

In an embodiment of the present invention, in the above-mentioned shift register device, during the enabling time of the (n-2)th clock signal, the driving signal is changed from the first level to the second level, Wherein the second level is greater than the first level; during the enabling time of the (n-1)th clock signal, the driving signal is maintained at a state not less than the second level; and during the enabling time of the nth clock signal During the enabling time, the driving signal is changed to a third level, wherein the third level is greater than the second level.

In an embodiment of the present invention, in the above-mentioned shift register device, the reference high voltage is a DC high voltage.

An embodiment of the present invention provides a display device, including a display panel and a shift register. The shift register device includes multiple stages of shift registers connected in series, which respectively output scan signals to the display panel according to multiple clock signals, wherein the shift register of the nth stage outputs scan signals according to the nth clock signal. signal, and includes a driving transistor, a pull-up circuit, a pull-down control transistor and a pull-up control transistor. The driving transistor is controlled by the driving signal, its first terminal receives the nth clock signal, and its second terminal outputs the scanning signal of the nth stage shift register. The pull-up circuit is controlled by the driving signal and coupled to the reference high voltage to output the driving signal to the (n+2)th stage shift register, wherein the pull-up circuit is used to enable the nth clock signal In time, start to pull up the driving signal of the (n+2)th stage shift register based on the reference high voltage. The pull-down control transistor is coupled to the pull-up circuit and is controlled by the scan signal of the (n+4)th stage shift register to control the pull-up circuit to stop outputting to the (n+2) stage shift register drive signal. The pull-up control transistor is controlled by the scan signal of the (n-2)th stage shift register, its first end is coupled to the pull-up circuit, and its second end is coupled to the reference low voltage, where n is greater than or equal to 3 an integer of .

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of a display device according to an embodiment of the invention.

FIG. 2 is a schematic circuit diagram of an nth stage shift register according to an embodiment of the present invention.

FIG. 3 is a circuit diagram of an nth stage shift register according to another embodiment of the present invention.

FIG. 4 is an operation timing diagram of an nth stage shift register according to an embodiment of the present invention.

FIG. 5 is an operation timing diagram of an nth stage shift register according to another embodiment of the present invention.

FIG. 6 is a circuit diagram of an nth stage shift register according to another embodiment of the present invention.

Explanation of reference signs:

100: display device

110: shift temporary storage device

120: display panel

130: pull-up circuit

140: Pull-down circuit

150: The first voltage regulator circuit

160: Second voltage regulator circuit

C: Capacitance

DT: drive transistor

G1～G(N): scanning signal

HC1～HCN: clock signal

LC1: the first regulated clock signal

LC2: Second regulated clock signal

SR1～SRN, 300, 300’: shift register

ST(n): starting voltage

T1: first pull-up transistor

T2: second pull-up transistor

T3: pull-up control transistor

T4: pull-down control transistor

T5: first pull-down transistor

T6: second pull-down transistor

T7～T12, T13～T18: Transistors

Q(1)～Q(N): drive signal

VGH: reference high voltage

VSS: reference low voltage

V1, V2, V21, V3: voltage levels

Detailed ways

FIG. 1 is a schematic diagram of a display device according to an embodiment of the invention. Referring to FIG. 1 , the display device 100 at least includes a shift register 110 and a display panel 120 . The shift register device 110 can be directly formed on the glass substrate of the display panel 120 by utilizing gate drive circuit substrate technology (gateon array, GOA), and is used to sequentially provide the scan signal G(n) to multiple scans in the display panel 120 Wire. The shift register device 110 has multi-stage shift registers SR1 - SRN which have substantially the same circuit structure and are connected in series. These shift registers SR1 - SRN output corresponding scan signals G1 - G(N) to the display panel 120 respectively according to a plurality of clock signals HC1 - HCN. For example, the nth stage shift register outputs the scan signal G(n) according to the clock signal HC(n), wherein the rising edge of the scan signal G(n) is substantially aligned with the corresponding clock signal HC(n) rising edge.

The coupling relationship and operating principle among the components of each stage of shift registers SR1 - SRN will be further described below.

FIG. 2 is a schematic circuit diagram of an nth stage shift register according to an embodiment of the present invention. Please refer to FIG. 2 in conjunction with FIG. 1 . The embodiment in FIG. 2 describes the circuit structure and operating principle of the nth stage shift register SR(n) in FIG. 1 , where n is an integer greater than or equal to 3. The circuit structures and operating principles of the rest of the shift registers in FIG. 1 are similar to those in the embodiment in FIG. 2 , so details are not repeated here.

In FIG. 2 , the nth stage shift register SR(n) at least includes a driving transistor DT, a pull-up circuit 130 , a pull-up control transistor T3 and a pull-down control transistor T4 . In this embodiment, the pull-up circuit 130 is composed of a first pull-up transistor T1 and a second pull-up transistor T2. The driving transistor DT is controlled by the driving signal Q(n) of this stage, and its gate receives the driving signal Q(n) from the shift register SR(n-2) of the (n-2)th stage, and the first terminal After receiving the nth clock signal HC(n), the second terminal outputs the corresponding nth level scanning signal G(n). The pull-up circuit 130 is controlled by the driving signal Q(n) and coupled to the reference high voltage VGH. The pull-up circuit 130 will output the driving signal Q(n+2) to the (n+2)th stage shift register SR(n+2) and in the enable time of the nth clock signal HC(n) The driving signal Q(n+2) is pulled up based on the reference high voltage VGH. The reference high voltage VGH is, for example, a DC high voltage.

The pull-down control transistor T4 is coupled to the pull-up circuit 130 and is controlled by the scan signal G(n+4) of the (n+4)th shift register. The pull-down control transistor T4 can control the pull-up circuit 130 to stop outputting the driving signal Q(n+2) to the (n+2)th shift register SR(n+2). The pull-up control transistor T3 is controlled by the scan signal G(n-2) of the (n-2)th stage shift register SR(n-2), its first end is coupled to the pull-up circuit 130, and its second The terminal is coupled to the reference low voltage VSS.

In this embodiment, in the pull-up circuit 130, the first pull-up transistor T1 is controlled by the driving signal Q(n), its first terminal is coupled to the reference high voltage VGH, and its second terminal provides the start-up voltage ST(n ). The first terminal of the second pull-up transistor T2 is coupled to the gate terminal, and is also coupled to the second terminal of the first pull-up transistor T1 to receive the start-up voltage ST(n). The gate terminal of the second pull-up transistor T2 is also coupled to the first terminal of the pull-up control transistor T3. The second terminal of the second pull-up transistor T2 outputs the driving signal Q(n+2) to the (n+2)th shift register SR(n+2).

In particular, the size of the pull-up control transistor T3 is different from the size of the first pull-up transistor T1. For example, the channel width of the pull-up control transistor T3 is greater than the channel width of the first pull-up transistor T1. In this way, when the first pull-up transistor T1 and the pull-up control transistor T3 are turned on at the same time, the start-up voltage ST(n) will be pulled down by the reference low voltage VSS to maintain the voltage level of the reference low voltage VSS, so the first The second pull-up transistor T2 will not be turned on early.

FIG. 3 is a circuit diagram of an nth stage shift register according to another embodiment of the present invention. The nth stage shift register 300 in FIG. 3 is applicable to the nth stage shift register SR(n) in FIG. 2 . The shift register 300 further includes a pull-down circuit 140 , a first voltage stabilizing circuit 150 and a second voltage stabilizing circuit 160 .

The pull-down circuit 140 is coupled between the reference low voltage VSS and the second terminal of the driving transistor DT. The pull-down circuit 140 is controlled by the scanning signal G(n+4) of the (n+4)th stage shift register to pull down the scanning signal G(n) of the nth stage shift register 300 .

The pull-down circuit 140 includes a first pull-down transistor T5 and a second pull-down transistor T6. The first pull-down transistor T5 is controlled by the scan signal G(n+4) of the (n+4) shift register, its first end is coupled to the gate end of the drive transistor DT, and its second end is coupled to Referenced to low voltage VSS. The second pull-down transistor T6 is also controlled by the scan signal G(n+4) of the (n+4)th stage shift register, its first end is coupled to the second end of the drive transistor DT, and its second end is also Coupled to the reference low voltage VSS.

The first voltage stabilizing circuit 150 includes a plurality of transistors T7 - T12 . The first terminal of the transistor T7 is coupled to the gate terminal, and receives the first regulated clock signal LC1 . The transistor T8 is coupled between the second terminal of the transistor T7 and the reference low voltage VSS, and is controlled by the driving signal Q(n). The first terminal and the gate terminal of the transistor T9 are respectively coupled to the first terminal and the second terminal of the transistor T7, and the second terminal of the transistor T9 is connected to the transistor T10 in series. The other terminal of the transistor T10 is coupled to the reference low voltage VSS, wherein the gate terminal of the transistor T10 also receives the driving signal Q(n). Both the transistor T11 and the transistor T12 are controlled by the voltage level of the second terminal of the transistor T9, and the second terminal is coupled to the reference low voltage VSS. However, the first end of the transistor T11 receives the driving signal Q(n), the first end of the transistor T12 is coupled to the second end of the driving transistor DT to receive the scanning signal G(n), and is coupled to the capacitor C at the same time, and the other end of the capacitor C One end receives the driving signal Q(n). That is to say, the potential difference between the two ends of the capacitor C will reflect the potential difference between the driving signal Q(n) and the scanning signal G(n). When the transistor T12 is turned on, the scan signal G(n) will be pulled down to the reference low voltage VSS.

The second voltage stabilizing circuit 160 includes a plurality of transistors T13 - T18 . The circuit structure of the second voltage stabilizing circuit 160 is similar to that of the first voltage stabilizing circuit 150 . The first terminal and the gate terminal of the transistor T13 are coupled together, and receive the second regulated clock signal LC2 . The transistor T14 is coupled between the second terminal of the transistor T13 and the reference low voltage VSS, and is controlled by the driving signal Q(n). The first terminal and the gate terminal of the transistor T15 are respectively coupled to the first terminal and the second terminal of the transistor T13, and the second terminal of the transistor T15 is connected to the transistor T16 in series. The other terminal of the transistor T16 is coupled to the reference low voltage VSS, wherein the gate terminal of the transistor T16 also receives the driving signal Q(n). The gate terminals of the transistor T17 and the transistor T18 are both coupled between the second terminal of the transistor T15 and the first terminal of the transistor T16 , and the second terminals of the transistor T17 and the transistor T18 are both coupled to the reference low voltage VSS. The first terminal of the transistor T17 receives the driving signal Q(n). The first terminal of the transistor T18 is coupled to the second terminal of the driving transistor DT. When the transistor T18 is turned on, the scan signal G(n) will be pulled down to the reference low voltage VSS.

Further, both the first voltage stabilizing circuit 150 and the second voltage stabilizing circuit 160 are coupled to the second end of the driving transistor DT and receive the driving signal Q(n). The first stabilizing circuit 150 and the second stabilizing circuit 160 can operate alternately according to the first stabilizing clock signal LC1 and the second stabilizing clock signal LC2, so as to stabilize the scanning signal G(n) according to the driving signal Q(n). .

FIG. 4 is an operation timing diagram of an nth stage shift register according to an embodiment of the present invention. Please refer to FIG. 1 , FIG. 3 and FIG. 4 at the same time. In this embodiment, the scan signal G(n) provided by the shift register 110 can be set to precharge the scan lines in the display panel 120 or is not to precharge these scan lines. However, in the embodiment of FIG. 4 , the scanning signal G(n) provided by the shift register 110 is an example of a sequence in which the display panel 120 is not precharged, and FIG. 4 only uses the third-level shift register SR3 as an illustration (n=3). In addition, the transistors in this specification are all implemented in the form of NMOS transistors, so the logic high level (High or 1) of the signal indicates that it can be enabled. However, the present invention does not limit the embodiment of the transistor.

Since in this embodiment, the driving mode of the display panel 120 is a non-precharge mode, the enabling times of these clock signals HC1-HC6 shown in FIG. The enabling times of the signals G( 1 )˜G( 6 ) do not overlap with each other.

During the enabling time of the clock signal HC1, that is, time t1~t2, the first-stage shift register SR1 is enabled, and the output scanning signal G(1) is also in the enabled state, and the driving signal Q(3) From a low level, voltage level V1 indicated in FIG. 4 , is changed to a high level, voltage level V2 indicated in FIG. 4 . Correspondingly, the first pull-up transistor T1 and the pull-up control transistor T3 in the third-stage shift register SR3 are turned on. Because the size of the first pull-up transistor T1 is smaller than that of the pull-up control transistor T3, even if both are turned on at the same time, the start-up voltage ST(3) on the gate terminal of the second pull-up transistor T2 is still referenced to the low voltage VSS pulled down, causing the second pull-up transistor T2 to be non-conductive.

During the enabling time of the clock signal HC2 (time t2~t3), the pull-up control transistor T3 is turned off by the scanning signal G(1), and the driving signal Q(3) is kept at a voltage level V21 not less than the voltage level V2 (In this embodiment, the voltage level V21 is greater than the voltage level V2), the first pull-up transistor T1 is still turned on, and the gate terminal of the second pull-up transistor T2 starts to be charged by the reference high voltage VGH, but at this time The voltage ST(3) still does not exceed the threshold voltage of the second pull-up transistor T2, and the second pull-up transistor T2 is still in the off state.

During the enabling time of the clock signal HC3 (time t3~t4), the pull-up control transistor T3 remains turned off, the first pull-up transistor T1 remains turned on, and the start-up voltage ST(3) is charged to a high level by the reference high voltage VGH state to turn on the second pull-up transistor T2. The turned-on second pull-up transistor T2 starts to pull up the driving signal Q(5) of the fifth-stage shift register SR5 according to the start-up voltage ST(3). As shown in FIG. 4 , the driving signal Q ( 5 ) starts to be pulled up from a low level (voltage level V1 ) to a high level (voltage level V2 ).

During this period, the clock signal HC3 is in a high level state, the scanning signal G(3) output by the driving transistor DT is also in a high level state, and the driving signal Q(3) is coupled to a higher voltage level, The voltage level V3 is indicated in FIG. 4 . In addition, the first pull-up transistor T1 and the pull-up control transistor T3 in the fifth-stage shift register SR5 are respectively turned on by the driving signal Q(5) and the scanning signal G(3). Please refer to the above about time t1 Implementation instructions for ~t2.

During the enabling time of the clock signal HC4 (time t4-t5), the pull-up control transistor T3 remains closed, the voltage level of the driving signal Q(3) decreases, and returns to the voltage level V21, and the first pull-up transistor T1 maintains conduction. The start-up voltage ST(3) will be maintained in a high-level state by the reference high voltage VGH, and the second pull-up transistor T2 will remain on, so the driving signal Q(5) will not be in a floating state (Floating), but will be activated by the The voltage ST(3) continues to maintain a high level state.

Until time t7 (the rising edge of the seventh-level scan signal G( 7 )), the pull-down circuit 140 and the pull-down control transistor T4 are enabled by the scan signal G( 7 ). After the pull-down control transistor T4 is turned on, the start-up voltage ST( 3 ) is pulled down with reference to the low voltage VSS to turn off the second pull-up transistor T2 . Additionally, drive signal Q(3) is switched back to voltage level V1. After the first pull-down transistor T5 and the second pull-down transistor T6 in the pull-down circuit 140 are turned on, the driving transistor DT is correspondingly turned off, and the scan signal G( 3 ) is stabilized at the reference low voltage VSS.

In short, for the third-stage shift register SR3, the drive signal Q(3) and the scan signal G(3) will control the third-stage shift register SR3 to output the drive signal Q(5) to the next Two-stage shift register SR5, and so on. During the enabling time of the clock signal HC1, the drive signal Q(3) is changed from a first level (such as a voltage level V1) to a second level (such as a voltage level V2), wherein the second level is greater than the first level One level. During the enabling time of the clock signal HC2, the driving signal Q(3) is maintained at a state not less than the second level (for example, voltage level V21); during the enabling time of the clock signal HC3, the driving signal Q(3) ) is changed to a third level (such as voltage level V3), wherein the third level is greater than the second level; during the enabling time (time t4-t7) of the clock signal HC4 to the clock signal HC6, the driving signal Q (3) Switched from the third level to a voltage level not less than the second level (for example, back to the voltage level V21); the scan signal G (7 ) during the enabling time, the driving signal Q(3) is switched back to the first level.

It is explained here that, in this embodiment, when the enable times of these clock signals HC1˜HCN do not overlap with each other and the shift register of the nth stage will output to the driver of the shift register of the n+2th stage When the signal Q(n+2), for the shift register of the nth stage, during the enable time of the clock signal HC(n), the driving signal Q(n+2) is precharged, and the clock signal HC During the enable time of (n+1), the pull-up control transistor T3 is controlled so that the pull-up circuit 130 can maintain the voltage level of the driving signal Q(n+2) after being pulled up. During this time, the driving signal Q(n+2) can continue to be charged instead of being in a floating state, so the voltage across the first terminal and the second terminal of the second pull-up transistor T2 (drain-source The inter-electrode voltage, V _DS ) can be effectively reduced, which can reduce the leakage current and increase the driving force of the shift register.

FIG. 5 is an operation timing diagram of an nth stage shift register according to another embodiment of the present invention. Please refer to FIG. 1 , FIG. 3 and FIG. 5 at the same time. In this embodiment, the scan signal G(n) provided by the shift register 110 is set to precharge the scan lines in the display panel 120 . Hereinafter, the third-stage shift register SR3 is also used as an illustration (n=3).

Due to the need to precharge the scan lines in the display panel 120 , the enable times of the clock signals HC1 - HC6 in FIG. 5 may partially overlap. Likewise, because the rising edge of the scanning signal G(n) is substantially aligned with the rising edge of the corresponding clock signal HC(n), the enabling times of the scanning signals G(1)-G(6) also partially overlap. In this embodiment, the enabling time of the nth clock signal HC(n) overlaps with the next clock signal HC(n+1) by 1/2.

As shown in FIG. 5, at time t9～time t10, in the third-stage shift register SR3, the pull-up control transistor T3 is in the off state and the pull-up circuit 130 is enabled, and the voltage of the drive signal Q(5) The level is precharged to a high level until time t12, wherein, at time t10 to time t11, since the scanning signal G(5) is at the enable level, the driving signal Q(5) is coupled to a higher voltage level.

According to the embodiment shown in FIG. 4 and FIG. 5 , by changing the timing of the clock signals HC1 -HCN , the shift register 300 can drive the scan lines of the display panel 110 with or without pre-charging. Especially in the non-precharge driving mode, the shift register device 110 composed of the shift register 300 can prevent the internal drive signal Q(n) from being in a floating state, effectively reducing the leakage current.

FIG. 6 is a circuit diagram of an nth stage shift register according to another embodiment of the present invention. The nth stage shift register 300' in FIG. 6 is applicable to the nth stage shift register SR(n) in FIG. 2 and is similar to the nth stage shift register 300 in FIG. 3 . The difference between the shift register 300' and the shift register 300 is that the internal structure of the pull-up circuit 130 is slightly different.

In the embodiment of FIG. 6 , the first terminal of the second pull-up transistor T2 is not coupled to the gate terminal, and the first terminal is coupled to the first terminal of the first pull-up transistor T1 to receive the reference high voltage VGH. Those skilled in the art can obtain sufficient enlightenment, suggestions and implementation descriptions from the above descriptions for the rest of the circuit structure and related driving methods, so no more details are given here.

In summary, the shift register device of the present invention additionally introduces a reference high voltage, so that the pull-up circuit can maintain the voltage level of the drive signal of the shift register according to the reference high voltage, avoiding floating empty windows Expect. Therefore, the leakage current of the shift register device can be reduced and the driving capability and stability of the shift register can be increased. The display device proposed by the present invention can adopt the above-mentioned shift register device to improve the stability of the scanning signal.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and modifications without departing from the concept and scope of the present invention. Therefore, the present invention The scope of protection shall prevail as defined by the claims.

Claims (12)

1. A shift temporary storage device, comprising: Multi-stage shift registers connected in series output multiple scan signals to a display panel according to multiple clock signals, wherein the nth shift register outputs the scan signals according to the nth clock signal, and include: A drive transistor, controlled by a primary drive signal, its first end receives the nth clock signal, and its second end outputs the scan signal of the nth stage shift register; A pull-up circuit, controlled by the drive signal of the current stage and coupled to a reference high voltage, is used to output the drive signal to the (n+2)th stage shift register, wherein the pull-up circuit is used for the Starting to pull up the driving signal of the (n+2)th stage shift register based on the reference high voltage during the enabling time of the nth clock signal; A pull-up control transistor, coupled to the pull-up circuit and controlled by the scan signal of the (n+4) shift register, is used to control the pull-up circuit to stop outputting to the (n+2) shift register. drive signals for bit registers; and A pull-up control transistor, controlled by the scanning signal of the (n-2)th stage shift register, its first end is coupled to the pull-up circuit, its second end is coupled to a reference low voltage, Where n is an integer greater than or equal to 3. 2. The shift register device as claimed in claim 1, wherein when the enabling times of the clock signals do not overlap with each other, the pull-up control transistor is controlled so that the pull-up circuit at the (n+1th The voltage level after the drive signal of the (n+2)th stage shift register is pulled up is maintained during the enabling time of the ) clock signal. 3. The shift register device as claimed in claim 1, wherein the pull-up circuit comprises: A first pull-up transistor, controlled by the driving signal of the current stage, its first terminal is coupled to the reference high voltage, and its second terminal provides a start-up voltage; and A second pull-up transistor, the gate terminal of which is coupled to the second terminal of the first pull-up transistor and the first terminal of the pull-up control transistor, and receives the startup voltage, and whose first terminal is coupled together with the gate terminal Or its first end is coupled to the reference high voltage, and its second end is output to the driving signal of the (n+2)th stage shift register. 4. The shift register device as claimed in claim 3, wherein the size of the pull-up control transistor is different from that of the first pull-up transistor. 5. The shift register device as claimed in claim 4, wherein the channel width of the pull-up control transistor is larger than the channel width of the first pull-up transistor. 6. The shift register device as claimed in claim 3, wherein, during the enable time of the (n+1)th clock signal, the pull-up control transistor is turned off, and the first pull-up transistor and the The second pull-up transistor is turned on, and the driving signal of the (n+2)th shift register is continuously pulled up by the reference high voltage. 7. The shift register device as claimed in claim 1, wherein the nth stage shift register further comprises: A pull-down circuit, coupled between the reference low voltage and the second terminal of the drive transistor and controlled by the scan signal of the (n+4)th stage shift register, is used to pull down the nth stage shift register Scan signal for the bit register. 8. The shift register device as claimed in claim 7, wherein the pull-down circuit comprises: A first pull-down transistor, controlled by the scanning signal of the (n+4)th stage shift register, its first terminal is coupled to the gate terminal of the driving transistor, and its second terminal is coupled to the reference low voltage ;as well as A second pull-down transistor, controlled by the scan signal of the (n+4)th stage shift register, its first end coupled to the second end of the driving transistor, and its second end coupled to the reference low voltage . 9. The shift temporary storage device as claimed in claim 1, further comprising: A first voltage stabilizing circuit and a second voltage stabilizing circuit are coupled to the second terminal of the drive transistor and receive the driving signal of the current stage, wherein the first voltage stabilizing circuit and the second voltage stabilizing circuit are used for The level driving signal stabilizes the scan signal of the nth level shift register. 10. The shift temporary storage device as claimed in claim 1, wherein, During the enable time of the (n-2)th clock signal, the driving signal of the current stage is changed from a first level to a second level, wherein the second level is greater than the first level; During the enabling time of the (n-1)th clock signal, the driving signal of the current stage is maintained at a state not lower than the second level; and During the enabling time of the nth clock signal, the driving signal of the current stage is changed to a third level, wherein the third level is greater than the second level. 11. The shift register device as claimed in claim 1, wherein the reference high voltage is a DC high voltage. 12. A display device comprising: a display panel; and A shift register device, including multi-stage shift registers connected in series, respectively outputting a scan signal to the display panel according to multiple clock signals, wherein the shift register of the nth stage is based on the nth The clock signal outputs the scanning signal, and includes: A drive transistor, controlled by a primary drive signal, its first end receives the nth clock signal, and its second end outputs the scan signal of the nth stage shift register; A pull-up circuit, controlled by the drive signal of the current stage and coupled to a reference high voltage, is used to output the drive signal to the (n+2)th stage shift register, wherein the pull-up circuit is used for the Starting to pull up the driving signal of the (n+2)th stage shift register based on the reference high voltage during the enabling time of the nth clock signal; A pull-up control transistor, coupled to the pull-up circuit and controlled by the scan signal of the (n+4) shift register, is used to control the pull-up circuit to stop outputting to the (n+2) shift register. drive signals for bit registers; and A pull-up control transistor, controlled by the scanning signal of the (n-2)th stage shift register, its first end is coupled to the pull-up circuit, its second end is coupled to a reference low voltage, Where n is an integer greater than or equal to 3.

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