CN110459163B

CN110459163B - Shift temporary storage device and display device

Info

Publication number: CN110459163B
Application number: CN201910832250.4A
Authority: CN
Inventors: 林炜力
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2019-02-12
Filing date: 2019-09-04
Publication date: 2023-03-28
Anticipated expiration: 2039-09-04
Also published as: TW202030738A; TWI680463B; CN110459163A

Abstract

The invention provides a shift register device, which comprises a plurality of stages of shift registers connected in series. The nth stage shift register outputs a scan signal according to the nth clock signal. The driving transistor is controlled by the driving signal and receives the nth clock signal to output the scanning signal of the nth shift register. The pull-up circuit is controlled by the driving signal, and starts to pull up the driving signal of the (n + 2) th stage shift register based on the reference high voltage in the enabling time of the nth clock signal. The pull-down control transistor controls the pull-up circuit to stop outputting the driving signal to the (n + 2) th stage shift register. The pull-up control transistor is controlled by a scanning signal of the (n-2) th stage of shift register and is coupled with the pull-up circuit and a reference low voltage, wherein n is an integer greater than or equal to 3. A display device is also provided.

Description

Shift temporary storage device and display device

Technical Field

The present invention relates to a display panel driving technology, and more particularly, to a shift register device and a display device.

Background

With the development of display panel technology, a narrow-bezel display screen has become a mainstream product at present. The conventional display panel may utilize a Gate On Array (GOA) technology to reduce the area by integrating the driving circuit on the glass substrate of the display panel.

On the other hand, the same display panel may be applied to different series of products, and therefore, flexibility of matching different timing settings, such as a driving timing for precharging the scan lines or a driving timing for non-precharging, may be required. In order to satisfy both of these driving timings, extra care is required in designing the driving circuit. For example, in the prior art, the shift registers having the interlocking relationship may cause a leakage current problem due to the floating of the driving signal. How to suppress the leakage current becomes a problem to be solved.

Disclosure of Invention

The invention provides a shift register device and a display device, which can reduce the leakage current of the shift register device and increase the driving capability and stability of a shift register.

The embodiment of the invention provides a shift register device arranged on a substrate of a display panel, which comprises a plurality of stages of shift registers connected in series. The shift registers respectively output scanning signals to the display panel according to a plurality of clock signals, wherein the nth stage shift register outputs the scanning signals according to the nth clock signal and comprises a driving transistor, a pull-up circuit, a pull-down control transistor and a pull-up control transistor. The driving transistor is controlled by a driving signal, a first end of the driving transistor receives the nth clock signal, and a second end of the driving transistor outputs a scanning signal of the nth stage of shift register. The pull-up circuit is controlled by the driving signal and coupled to the reference high voltage for outputting the driving signal to the (n + 2) th stage shift register, wherein the pull-up circuit is used for pulling up the driving signal of the (n + 2) th stage shift register based on the reference high voltage in the enabling time of the nth clock signal. The pull-down control transistor is coupled to the pull-up circuit and controlled by a scanning signal of the (n + 4) th stage shift register, so as to control the pull-up circuit to stop outputting a driving signal to the (n + 2) th stage shift register. The pull-up control transistor is controlled by a scanning signal of the (n-2) th-stage shift register, a first end of the pull-up control transistor is coupled with the pull-up circuit, a second end of the pull-up control transistor is coupled with a reference low voltage, and n is an integer greater than or equal to 3.

In an embodiment of the invention, in the shift register device, when the enabling times of the clock signals do not overlap with each other, the pull-up control transistor is controlled to make the pull-up circuit maintain the voltage level of the pulled-up driving signal of the (n + 2) th stage shift register during the enabling time of the (n + 1) th clock signal.

In an embodiment of the invention, the pull-up circuit of the shift register device includes a first pull-up transistor controlled by a driving signal, a first terminal of the first pull-up transistor is coupled to a reference high voltage, a second terminal of the first pull-up transistor provides a start-up voltage, and a second pull-up transistor. The second pull-up transistor has a gate terminal coupled to the second terminal of the first pull-up transistor and the first terminal of the pull-up control transistor, receives the start-up voltage, has a first terminal coupled to the gate terminal thereof or a first terminal coupled to the reference high voltage, and has a second terminal outputting the driving signal to the (n + 2) -th stage shift register.

In an embodiment of the invention, a size of the pull-up control transistor in the shift register device is different from a size of the first pull-up transistor.

In an embodiment of the invention, a channel width of the pull-up control transistor in the shift register device is greater than a channel width of the first pull-up transistor.

In an embodiment of the invention, in the shift register device, during the enabling time of the (n + 1) th clock signal, the pull-up control transistor is turned off, the first pull-up transistor and the second pull-up transistor are turned on, and the driving signal of the (n + 2) th stage of the shift register is continuously pulled up by the reference high voltage.

In an embodiment of the invention, the nth stage shift register of the shift register device further includes a pull-down circuit. The pull-down circuit is coupled between the reference low voltage and the second end of the driving transistor and is controlled by a scanning signal of the (n + 4) th stage shift register to pull down the scanning signal of the nth stage shift register.

In an embodiment of the invention, the pull-down circuit of the shift register device includes a first pull-down transistor and a second pull-down transistor. The first pull-down transistor is controlled by a scanning signal of the (n + 4) th stage shift register, and has a first terminal coupled to the gate terminal of the driving transistor and a second terminal coupled to a reference low voltage. The second pull-down transistor is controlled by a scanning signal of the (n + 4) th stage shift register, and has a first terminal coupled to the second terminal of the driving transistor and a second terminal coupled to the reference low voltage.

In an embodiment of the invention, the shift register device further includes a first voltage regulator circuit and a second voltage regulator circuit. The first voltage stabilizing circuit and the second voltage stabilizing circuit are coupled to the second end of the driving transistor and receive the driving signal, wherein the first voltage stabilizing circuit and the second voltage stabilizing circuit are used for stabilizing the scanning signal of the nth stage shift register according to the driving signal.

In an embodiment of the invention, in the shift register device, during the enabling time of the (n-2) th clock signal, the driving signal is changed from the first level to the second level, wherein the second level is greater than the first level; in the enable time of the (n-1) th clock signal, the driving signal is maintained at a state not less than the second level; and in an enable time of the nth clock signal, the driving signal is changed to a third level, wherein the third level is greater than the second level.

In an embodiment of the invention, in the shift register device, the reference high voltage is a dc high voltage.

An embodiment of the invention provides a display device, which includes a display panel and a shift register device. The shift register device comprises a plurality of stages of shift registers which are connected in series, and respectively outputs scanning signals to the display panel according to a plurality of clock signals, wherein the nth stage of shift register outputs the scanning signals according to the nth clock signal, and comprises a driving transistor, a pull-up circuit, a pull-down control transistor and a pull-up control transistor. The driving transistor is controlled by a driving signal, a first end of the driving transistor receives the nth clock signal, and a second end of the driving transistor outputs a scanning signal of the nth stage of shift register. The pull-up circuit is controlled by the driving signal and coupled to the reference high voltage for outputting the driving signal to the (n + 2) th stage shift register, wherein the pull-up circuit is used for pulling up the driving signal of the (n + 2) th stage shift register based on the reference high voltage in the enabling time of the nth clock signal. The pull-down control transistor is coupled to the pull-up circuit and controlled by a scanning signal of the (n + 4) th stage shift register, so as to control the pull-up circuit to stop outputting a driving signal to the (n + 2) th stage shift register. The pull-up control transistor is controlled by a scanning signal of the (n-2) th-stage shift register, a first end of the pull-up control transistor is coupled with the pull-up circuit, a second end of the pull-up control transistor is coupled with a reference low voltage, and n is an integer greater than or equal to 3.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a schematic diagram of a display device according to an embodiment of the invention.

Fig. 2 is a schematic circuit diagram of an nth stage shift register according to an embodiment of the invention.

Fig. 3 is a circuit diagram of an nth stage shift register according to another embodiment of the present invention.

FIG. 4 is a timing diagram illustrating operation of the nth shift register stage according to an embodiment of the present invention.

FIG. 5 is a timing diagram illustrating operation of an nth shift register stage according to another embodiment of the present invention.

FIG. 6 is a circuit diagram of an nth stage shift register according to another embodiment of the present invention.

Description of the reference numerals:

100: display device

110: shift temporary storage device

120: display panel

130: pull-up circuit

140: pull-down circuit

150: first voltage stabilizing circuit

160: second voltage stabilizing circuit

C: capacitor with a capacitor element

DT: driving transistor

G1 to G (N): scanning signal

HC1 to HCN: clock signal

LC1: a first regulated clock signal

LC2: second regulated clock signal

SR 1-SRN, 300': shift temporary storage device

ST (n): starting voltage

T1: a first pull-up transistor

T2: a second pull-up transistor

T3: pull-up control transistor

T4: pull-down control transistor

T5: a first pull-down transistor

T6: second pull-down transistor

T7 to T12, T13 to T18: transistor with a high breakdown voltage

Q (1) to Q (N): drive signal

VGH: reference high voltage

VSS: reference low voltage

V1, V2, V21, V3: voltage level

Detailed Description

Fig. 1 is a schematic diagram of a display device according to an embodiment of the invention. Referring to fig. 1, the display device 100 at least includes a shift register device 110 and a display panel 120. The shift register device 110 may be directly formed on a glass substrate of the display panel 120 by Gate On Array (GOA) technology, and is configured to sequentially provide the scan signals G (n) to a plurality of scan lines in the display panel 120. The shift register device 110 has a plurality of shift registers SR1 SRN with substantially the same circuit structure and connected in series. The shift registers SR1 SRN output corresponding scan signals G1G (N) to the display panel 120 according to the clock signals HC1 HCN, respectively. For example, the nth stage shift register outputs the scan signal G (n) according to the clock signal HC (n), wherein the rising edge of the scan signal G (n) is substantially aligned with the rising edge of the corresponding clock signal HC (n).

The coupling relationship and operation principle of each stage of shift registers SR1 SRN will be further described below.

Fig. 2 is a schematic circuit diagram of an nth stage shift register according to an embodiment of the invention. Referring to fig. 2 in conjunction with fig. 1, the embodiment of fig. 2 describes a circuit structure and an operation principle of the nth stage shift register SR (n) of fig. 1, where n is an integer greater than or equal to 3. The circuit structure and operation principle of the rest of the shift registers in fig. 1 are similar to those of the embodiment in fig. 2, and therefore are not described again.

In fig. 2, the nth stage shift register SR (n) includes at least a driving transistor DT, a pull-up circuit 130, a pull-up control transistor T3, and a pull-down control transistor T4. In the present embodiment, the pull-up circuit 130 is composed of a first pull-up transistor T1 and a second pull-up transistor T2. The driving transistor DT is controlled by the driving signal Q (n) of the current stage, and has a gate receiving the driving signal Q (n) from the (n-2) th stage shift register SR (n-2), a first terminal receiving the nth clock signal HC (n), and a second terminal outputting the corresponding nth scanning signal G (n). The pull-up circuit 130 is controlled by the driving signal Q (n) and coupled to the reference high voltage VGH. The pull-up circuit 130 outputs the driving signal Q (n + 2) to the (n + 2) th stage shift register SR (n + 2) and starts to pull up the driving signal Q (n + 2) based on the reference high voltage VGH during the enable time of the nth clock signal HC (n). The reference high voltage VGH is, for example, a dc high voltage.

The pull-down control transistor T4 is coupled to the pull-up circuit 130 and controlled by the scan signal G (n + 4) of the (n + 4) th stage of the shift register. The pull-down control transistor T4 may control the pull-up circuit 130 to stop the output of the driving signal Q (n + 2) to the (n + 2) th stage shift register SR (n + 2). The pull-up control transistor T3 is controlled by the scan signal G (n-2) of the (n-2) th shift register SR (n-2), and has a first terminal coupled to the pull-up circuit 130 and a second terminal coupled to the reference low voltage VSS.

In the pull-up circuit 130, the first pull-up transistor T1 is controlled by the driving signal Q (n), and has a first terminal coupled to the reference high voltage VGH and a second terminal providing the start-up voltage ST (n). The first terminal and the gate terminal of the second pull-up transistor T2 are coupled together and also coupled to the second terminal of the first pull-up transistor T1 to receive the start-up voltage ST (n). The gate terminal of the second pull-up transistor T2 is also coupled to the first terminal of the pull-up control transistor T3. The second terminal of the second pull-up transistor T2 outputs the driving signal Q (n + 2) to the (n + 2) th shift register SR (n + 2).

In particular, the pull-up control transistor T3 may have a different size than the first pull-up transistor T1. For example, the channel width of the pull-up control transistor T3 may be greater than the channel width of the first pull-up transistor T1. In this way, when the first pull-up transistor T1 and the pull-up control transistor T3 are turned on simultaneously, the start-up voltage ST (n) is pulled down by the reference low voltage VSS to be maintained at the voltage level of the reference low voltage VSS, so that the second pull-up transistor T2 is not turned on early.

Fig. 3 is a circuit diagram of an nth stage shift register according to another embodiment of the present invention. The nth stage shift register 300 of fig. 3 may be applied to the nth stage shift register SR (n) of fig. 2. The shift register 300 further includes a pull-down circuit 140, a first regulator 150 and a second regulator 160.

The pull-down circuit 140 is coupled between the reference low voltage VSS and the second terminal of the driving transistor DT. The pull-down circuit 140 is controlled by the scan signal G (n + 4) of the (n + 4) th shift register stage to pull down the scan signal G (n) of the nth shift register stage 300.

The pull-down circuit 140 includes a first pull-down transistor T5 and a second pull-down transistor T6. The first pull-down transistor T5 is controlled by the scan signal G (n + 4) of the (n + 4) th stage shift register, and has a first terminal coupled to the gate terminal of the driving transistor DT and a second terminal coupled to the reference low voltage VSS. The second pull-down transistor T6 is also controlled by the scan signal G (n + 4) of the (n + 4) th stage of shift register, and has a first terminal coupled to the second terminal of the driving transistor DT and a second terminal coupled to the reference low voltage VSS.

The first regulator circuit 150 includes a plurality of transistors T7 to T12. A first terminal and a gate terminal of the transistor T7 are coupled together and receive the first regulated clock signal LC1. The transistor T8 is coupled between the second terminal of the transistor T7 and the reference low voltage VSS, and is controlled by the driving signal Q (n). The first terminal and the gate terminal of the transistor T9 are coupled to the first terminal and the second terminal of the transistor T7, respectively, and the second terminal of the transistor T9 is connected to the transistor T10 in series. The other terminal of the transistor T10 is coupled to the reference low voltage VSS, wherein a gate terminal of the transistor T10 also receives the driving signal Q (n). The transistors T11 and T12 are controlled by the voltage level of the second terminal of the transistor T9, and the second terminals thereof are coupled to the reference low voltage VSS. However, the first terminal of the transistor T11 receives the driving signal Q (n), the first terminal of the transistor T12 is coupled to the second terminal of the driving transistor DT to receive the scanning signal G (n), and is also coupled to the capacitor C, and the other terminal of the capacitor C receives the driving signal Q (n). That is, the potential difference between the two ends of the capacitor C reflects the potential difference between the driving signal Q (n) and the scanning signal G (n). When the transistor T12 is turned on, the scan signal G (n) is pulled down to the reference low voltage VSS.

The second stabilizing circuit 160 includes a plurality of transistors T13 to T18. The circuit configuration of the second stabilizing circuit 160 is similar to that of the first stabilizing circuit 150. A first terminal and a gate terminal of the transistor T13 are coupled together and receive the second regulated clock signal LC2. The transistor T14 is coupled between the second terminal of the transistor T13 and the reference low voltage VSS, and is controlled by the driving signal Q (n). A first terminal and a gate terminal of the transistor T15 are respectively coupled to the first terminal and the second terminal of the transistor T13, and a second terminal of the transistor T15 is serially connected to the transistor T16. The other terminal of the transistor T16 is coupled to the reference low voltage VSS, wherein a gate terminal of the transistor T16 also receives the driving signal Q (n). The gate terminals of the transistor T17 and the transistor T18 are both coupled between the second terminal of the transistor T15 and the first terminal of the transistor T16, and the second terminals of the transistor T17 and the transistor T18 are both coupled to the reference low voltage VSS. A first terminal of the transistor T17 receives the driving signal Q (n). The first terminal of the transistor T18 is coupled to the second terminal of the driving transistor DT. When the transistor T18 is turned on, the scan signal G (n) is pulled down to the reference low voltage VSS.

Further, the first regulation circuit 150 and the second regulation circuit 160 are both coupled to the second terminal of the driving transistor DT and receive the driving signal Q (n). The first and second stabilizing

circuits

150 and 160 may alternately operate with each other according to the first and second stabilized clock signals LC1 and LC2 to stabilize the scan signal G (n) according to the driving signal Q (n).

FIG. 4 is a timing diagram illustrating operation of the nth shift register stage according to an embodiment of the present invention. Referring to fig. 1, fig. 3 and fig. 4, in the present embodiment, the scan signal G (n) provided by the shift register device 110 can be set to precharge or not precharge the scan lines in the display panel 120. However, in the embodiment of fig. 4, the scan signal G (n) provided by the shift register device 110 is an example of a timing sequence without precharging the display panel 120, and fig. 4 only uses the 3 rd stage shift register SR3 as an illustration (n = 3). In addition, since the transistors in this specification are all implemented as NMOS transistors, a logic High level (High or 1) of a signal indicates that the signal is enabled. The invention is not limited to the implementation of transistors.

In the present embodiment, the driving method of the display panel 120 is a non-precharge mode, so the enabling times of the clock signals HC1 to HC6 shown in fig. 4 do not overlap with each other, and the enabling times of the scan signals G (1) to G (6) provided by the shift register 110 do not overlap with each other.

During the enabling time of the clock signal HC1, i.e. the time t 1-t 2, the shift register SR1 of the 1 st stage is enabled, the output scan signal G (1) is also in the enabled state, and the driving signal Q (3) is changed from the low level, i.e. the voltage level V1 shown in fig. 4, to the high level, i.e. the voltage level V2 shown in fig. 4. Accordingly, the first pull-up transistor T1 and the pull-up control transistor T3 in the 3 rd stage shift register SR3 are turned on. Since the size of the first pull-up transistor T1 is smaller than the size of the pull-up control transistor T3, even though both are turned on at the same time, the start-up voltage ST (3) on the gate terminal of the second pull-up transistor T2 is pulled down by the reference low voltage VSS, causing the second pull-up transistor T2 to be non-conductive.

During the enabling time of the clock signal HC2 (time T2-T3), the pull-up control transistor T3 is turned off by the scan signal G (1), the driving signal Q (3) is maintained at the voltage level V21 not less than the voltage level V2 (in the present embodiment, the voltage level V21 is greater than the voltage level V2), the first pull-up transistor T1 is still maintained on, the gate terminal of the second pull-up transistor T2 starts to be charged by the reference high voltage VGH, but the start-up voltage ST (3) still does not exceed the threshold voltage of the second pull-up transistor T2 at this time, and the second pull-up transistor T2 is still in the off state.

In the enable time of the clock signal HC3 (time T3 to time T4), the pull-up control transistor T3 is kept off, the first pull-up transistor T1 is kept on, and the start-up voltage ST (3) is charged to a high level state by the reference high voltage VGH to turn on the second pull-up transistor T2. The turned-on second pull-up transistor T2 starts to pull up the driving signal Q (5) of the 5 th stage shift register SR5 according to the start voltage ST (3). As shown in fig. 4, the driving signal Q (5) starts to be pulled up from the low level (voltage level V1) to the high level (voltage level V2).

During this time, the clock signal HC3 is in a high state, the scan signal G (3) outputted by the driving transistor DT is also in a high state, and the driving signal Q (3) is coupled to a higher voltage level, such as the voltage level V3 indicated in fig. 4. In addition, the first pull-up transistor T1 and the pull-up control transistor T3 in the 5 th stage shift register SR5 are respectively turned on by the driving signal Q (5) and the scan signal G (3), please refer to the above description about the time T1-T2.

During the enable time of the clock signal HC4 (time T4 to T5), the pull-up control transistor T3 remains off, the voltage level of the driving signal Q (3) decreases, returns to the voltage level V21, and the first pull-up transistor T1 remains on. The start voltage ST (3) is maintained at a high level by the reference high voltage VGH, and the second pull-up transistor T2 is kept turned on, so the driving signal Q (5) is not in a Floating state (Floating), but is continuously maintained at a high level by the start voltage ST (3).

Until time T7 (the rising edge of the 7 th stage scan signal G (7)), the pull-down circuit 140 and the pull-down control transistor T4 are enabled by the scan signal G (7). After the pull-down control transistor T4 is turned on, the start-up voltage ST (3) is pulled down by the reference low voltage VSS to turn off the second pull-up transistor T2. In addition, the drive signal Q (3) is switched back to the voltage level V1. After the first pull-down transistor T5 and the second pull-down transistor T6 in the pull-down circuit 140 are turned on, the driving transistor DT is also turned off accordingly, and the scan signal G (3) is stabilized at the reference low voltage VSS.

In short, for the 3 rd stage shift register SR3, the driving signal Q (3) and the scanning signal G (3) control the 3 rd stage shift register SR3 to output the driving signal Q (5) to the next two stages of shift registers SR5, and so on. In the enable time of the clock signal HC1, the driving signal Q (3) is changed from a first level (e.g., voltage level V1) to a second level (e.g., voltage level V2), where the second level is greater than the first level. In the enable time of the clock signal HC2, the drive signal Q (3) is held in a state not less than the second level (e.g., voltage level V21); in the enable time of the clock signal HC3, the drive signal Q (3) is changed to a third level (e.g., voltage level V3), where the third level is greater than the second level; in the enable time (time t4 to t 7) of the clock signal HC4 to HC6, the drive signal Q (3) is switched from the third level to a voltage level not less than the second level (for example, back to the voltage level V21); in the enable time of the scanning signal G (7) of the (n + 4) th stage shift register, the driving signal Q (3) is switched back to the first level.

It is to be noted that, in the present embodiment, when the enable times of the clock signals HC1 to HCN do not overlap each other and the nth stage shift register outputs the driving signal Q (n + 2) to the (n + 2) th stage shift register, the driving signal Q (n + 2) is precharged during the enable time of the clock signal HC (n) and the driving signal Q (n + 2) is precharged during the enable time of the clock signal HC (n + 1) for the nth stage shift registerIn the on time, the pull-up control transistor T3 is controlled to enable the pull-up circuit 130 to maintain the voltage level of the drive signal Q (n + 2) pulled up. During this time, the driving signal Q (n + 2) can continue to be charged instead of being in a floating state, so that the voltage across the first and second terminals of the second pull-up transistor T2 (the drain-source voltage, V) _DS ) The effective reduction can be achieved, the leakage current can be reduced, and the driving force of the shift register can be increased.

FIG. 5 is a timing diagram illustrating operation of an nth shift register stage according to another embodiment of the present invention. Referring to fig. 1, fig. 3 and fig. 5, in the present embodiment, the scan signal G (n) provided by the shift register device 110 is set to precharge the scan lines in the display panel 120. Hereinafter, the 3 rd stage shift register SR3 will be described (n = 3).

The enable times of these clock signals HC1 to HC6 in fig. 5 may partially overlap due to the precharge of the scan lines in the display panel 120. Similarly, since the rising edge of the scan signal G (n) is substantially aligned with the rising edge of the corresponding clock signal HC (n), the enabling times of the scan signals G (1) -G (6) may also partially overlap. In the present embodiment, the nth clock signal HC (n) overlaps the next clock signal HC (n + 1) by 1/2 of the enable time.

As shown in fig. 5, in the 3 rd stage shift register SR3, the pull-up control transistor T3 is in an off state and the pull-up circuit 130 is enabled at time T9 to time T10, and the voltage level of the driving signal Q (5) is precharged to a high level until time T12, wherein the driving signal Q (5) is coupled to a higher voltage level since the scan signal G (5) is at an enable level at time T10 to time T11.

According to the embodiments of fig. 4 and 5, the shift register 300 can drive the scan lines of the display panel 110 to be precharged or not precharged by changing the timings of the clock signals HC1 to HCN. Particularly, in the non-precharge driving mode, the shift register device 110 comprising the shift register 300 can prevent the internal driving signal Q (n) from being in a floating state, thereby effectively reducing the leakage current.

FIG. 6 is a circuit diagram of an nth stage shift register according to another embodiment of the present invention. The nth stage shift register 300' of fig. 6 may be applied to the nth stage shift register SR (n) of fig. 2 and is similar to the nth stage shift register 300 of fig. 3. The shift register 300' is slightly different from the shift register 300 in the internal structure of the pull-up circuit 130.

In the embodiment of fig. 6, the first terminal and the gate terminal of the second pull-up transistor T2 are not coupled together, and the first terminal is coupled to the first terminal of the first pull-up transistor T1 to receive the reference high voltage VGH. Other circuit architectures and associated driving schemes will be apparent to those skilled in the art from the foregoing description, and will not be described herein.

In summary, the shift register device of the present invention further introduces the reference high voltage, so that the pull-up circuit can maintain the voltage level of the driving signal of the shift register according to the reference high voltage, thereby avoiding the floating window period. Therefore, the leakage current of the shift register device can be reduced, and the driving capability and stability of the shift register can be increased. The display device provided by the invention can adopt the shift register device to improve the stability of the scanning signal.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A shift register device comprising:

a plurality of stages of shift registers connected in series to each other, for outputting a plurality of scan signals to a display panel according to a plurality of clock signals, wherein an nth stage of shift register outputs the scan signals according to an nth clock signal, and comprises:

a driving transistor controlled by a current-stage driving signal, a first end of the driving transistor receiving the nth clock signal, and a second end of the driving transistor outputting a scanning signal of the nth-stage shift register;

a pull-up circuit, controlled by the current-stage driving signal and coupled to a reference high voltage, for outputting a driving signal to the (n + 2) th-stage shift register, wherein the pull-up circuit is configured to start to pull up the driving signal of the (n + 2) th-stage shift register based on the reference high voltage during an enabling time of the nth clock signal;

a pull-down control transistor coupled to the pull-up circuit and controlled by a scan signal of the (n + 4) th stage shift register, for controlling the pull-up circuit to stop outputting a driving signal to the (n + 2) th stage shift register; and

a pull-up control transistor controlled by the scanning signal of the (n-2) th stage shift register, having a first terminal coupled to the pull-up circuit and a second terminal coupled to a reference low voltage,

wherein n is an integer greater than or equal to 3.

2. The shift register device of claim 1, wherein the pull-up control transistor is controlled to make the pull-up circuit maintain the voltage level of the (n + 2) th stage shift register after the pull-up of the driving signal during the enable time of the (n + 1) th clock signal when the enable times of the clock signals do not overlap each other.

3. The shift register device of claim 1, wherein the pull-up circuit comprises:

a first pull-up transistor controlled by the current-stage driving signal, having a first terminal coupled to the reference high voltage and a second terminal providing a start-up voltage; and

a second pull-up transistor having a gate terminal coupled to the second terminal of the first pull-up transistor and the first terminal of the pull-up control transistor, and receiving the start-up voltage, a first terminal coupled to the gate terminal thereof or a first terminal coupled to the reference high voltage, and a second terminal outputting the driving signal to the (n + 2) th stage shift register.

4. The shift register device as claimed in claim 3, wherein the pull-up control transistor has a size different from that of the first pull-up transistor.

5. The shift register device of claim 4, wherein the channel width of the pull-up control transistor is larger than the channel width of the first pull-up transistor.

6. The shift register device of claim 3, wherein during the enabling time of the (n + 1) th clock signal, the pull-up control transistor is turned off, the first pull-up transistor and the second pull-up transistor are turned on, and the driving signal of the (n + 2) th stage shift register is continuously pulled up by the reference high voltage.

7. The shift register device of claim 1, wherein the nth stage shift register further comprises:

a pull-down circuit coupled between the reference low voltage and the second terminal of the driving transistor and controlled by the scan signal of the (n + 4) th stage shift register for pulling down the scan signal of the nth stage shift register.

8. The shift register device of claim 7, wherein the pull-down circuit comprises:

a first pull-down transistor controlled by the scan signal of the (n + 4) th stage shift register, having a first terminal coupled to the gate terminal of the driving transistor and a second terminal coupled to the reference low voltage; and

a second pull-down transistor controlled by the scan signal of the (n + 4) th stage shift register, having a first terminal coupled to the second terminal of the driving transistor and a second terminal coupled to the reference low voltage.

9. The shift register apparatus of claim 1, further comprising:

and the first voltage stabilizing circuit and the second voltage stabilizing circuit are coupled to the second end of the driving transistor and receive the current-stage driving signal, wherein the first voltage stabilizing circuit and the second voltage stabilizing circuit are used for stabilizing the scanning signal of the nth-stage shift register according to the current-stage driving signal.

10. The shift register apparatus of claim 1,

during the enabling time of the (n-2) th clock signal, the current stage driving signal is changed from a first level to a second level, wherein the second level is greater than the first level;

in the enabling time of the (n-1) th clock signal, the present stage driving signal is kept at a state not less than the second level; and

during the enabling time of the nth clock signal, the present driving signal is changed to a third level, wherein the third level is greater than the second level.

11. The shift register device of claim 1, wherein the reference high voltage is a DC high voltage.

12. A display device, comprising:

a display panel; and

a shift register device, comprising a plurality of stages of shift registers connected in series, for respectively outputting a scan signal to the display panel according to a plurality of clock signals, wherein the nth stage of shift register outputs the scan signal according to the nth clock signal, and comprising:

a pull-up circuit controlled by the current-stage driving signal and coupled to a reference high voltage for outputting a driving signal to the (n + 2) th-stage shift register, wherein the pull-up circuit starts to pull up the driving signal of the (n + 2) th-stage shift register based on the reference high voltage during an enable time of the nth clock signal;

wherein n is an integer greater than or equal to 3.