CN110456616A - With the defect inspection method of litho machine linkage - Google Patents

Abstract

The invention discloses a kind of defect inspection methods with litho machine linkage, wafer is in the exposure process after litho machine film, the apparent height of silicon wafer is scanned, generate the file of apparent height 3 dimensional drawing, big data analysis is carried out to measured data and obtains the risk class per a piece of silicon wafer, high risk silicon wafer ID (identity number) is added in the sampling of Yield lmproved department.The present invention can prejudge the superiority and inferiority situation of silicon wafer in advance, optimize the sampling of Yield lmproved department.

Description

With the defect inspection method of litho machine linkage

Technical field

The present invention relates to semiconductor integrated circuit fields, join more particularly to a kind of sampling of Yield lmproved department with litho machine Dynamic defect inspection method.

Background technique

In chip manufacturing field, the height of yield means the maturity of advanced process, passes through constantly changing for all kinds of techniques Into so that yield is controlled.On ordinary meaning, Yield lmproved department needs to be sampled silicon wafer detection, cannot be to all Product piece carry out defects detection.In view of reasons such as process query times, some loops are without opening station detection, so that not The situation of chip entirety can be counted, monolithic can only be derived using part silicon wafer situation using certain mathematical relationship Condition, this just has certain randomness and uncertainty.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of defect inspection methods with litho machine linkage, can be pre- in advance Sentence the superiority and inferiority situation of silicon wafer, optimizes the sampling of Yield lmproved department.

In order to solve the above technical problems, the defect inspection method of the invention with litho machine linkage is using following technical side What case was realized:

Wafer is scanned the apparent height of silicon wafer in the exposure process after litho machine film, and it is high to generate surface The file for spending 3 dimensional drawing carries out big data analysis to measured data and obtains the risk class per a piece of silicon wafer, by high risk Silicon wafer ID (identity number) is added in the sampling of Yield lmproved department.

Yield lmproved department needs to be sampled silicon wafer, cannot carry out defects detection, Zhi Nengli to all product pieces Integral status is derived using part silicon wafer situation with certain mathematical relationship, this just has certain randomness and uncertainty. Using method of the invention.Big data analysis is carried out using apparent height 3 D stereo map file, judges the wind per a piece of silicon wafer Dangerous grade can prejudge the superiority and inferiority situation of silicon wafer in advance, and high risk silicon wafer ID is added in the sampling of Yield lmproved department, The income of Yield lmproved department sampling is improved to greatest extent.

Detailed description of the invention

Present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:

Fig. 1 is the smooth time line reflection figure of silicon chip surface；

Fig. 2 is the raised time line reflection figure of silicon chip surface；

Fig. 3 is silicon chip surface recess time line reflection figure；

Fig. 4 is the control flow chart.

Specific embodiment

Each flake products piece silicon wafer all has to pass through scanning by lithographic section, and all data of silicon chip surface height are all remembered Record on record, different colours can indicate the height change of silicon wafer part.

It is recessed that Fig. 1-3 respectively indicates the raised time line reflection of the smooth time line reflection of silicon chip surface, silicon chip surface, silicon chip surface Fall into time line reflection, wherein label 1 indicates that sensor, 2 indicate that feux rouges, 3 indicate silicon wafer.For the silicon wafer of different concave-convex states The reflection path on surface, light is different, and the position that sensor receives light just has deviation, and the mode of this deviation numerical value becomes Reveal and.The sample standard deviation for calculating these numerical value will obtain the judgement of silicon wafer risk class.

As shown in connection with fig. 4, the defect inspection method with litho machine linkage, is using as follows in the following embodiments What mode was realized:

Step 1: file exports.Each flake products piece silicon wafer all can litho machine Jing Guo photoetching, the exposure after wafer film There can be a scanning process in photoreduction process to the apparent height of silicon wafer, generate the file of apparent height 3 dimensional drawing.In photoetching Board end exports the scan data file of exposure process, i.e. Focus Leveling Map (apparent height 3 dimensional drawing) text Part.

Step 2: data are analyzed.Surface height data is counted to every a piece of silicon wafer.

Step 3: result counts.Mark the risk class of silicon wafer.

Step 4: data linkage.High risk silicon wafer ID is added in sampling YE (Yield lmproved department).

It changes, can be showed in a manner of numerical value when sensor perceives reflection optical position.If StdDev is silicon wafer The sample standard deviation of unit.

As StdDev < 0.010, it is judged as low-risk silicon wafer unit.When all silicon wafer units are all low-risk, silicon wafer It is determined as low-risk silicon wafer.

As StdDev >=0.030, it is judged as high risk silicon wafer unit.When there are high risk silicon wafer unit, silicon wafer is sentenced It is set to high risk silicon wafer.

As 0.030 > StdDev > 0.010, it is judged as risk silicon wafer unit.When all silicon wafer units are all apoplexy When danger and low-risk, silicon wafer is determined as risk silicon wafer.

Height change lane database is recorded in high risk silicon wafer data, sends Yield lmproved department change corresponding product to High risk silicon wafer ID is added in sampling for the sampling of lot number.

Silicon wafer as following table is denoted as X is high risk silicon wafer, will increase corresponding silicon into the sampling of Yield lmproved department website Piece ID.Wherein layer, that is, processing procedure where product piece progress, Lot ID, that is, product piece number, M1 refer to the first time of back end of line Sedimentary, M2 refer to second of sedimentary of back end of line, and V1 refers to the second layer opening step of back end of line, and V indicates non-high risk Label, 1-25 indicate product piece number.

Lot ID

Layer

01

02

03

04

05

06

07

08

09

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

Product piece A

M1

X

X

V

V

V

X

X

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

Product piece B

M2

X

X

V

V

V

X

X

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

Product piece C

V1

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

Product piece D

M2

V

X

V

X

V

V

V

V

V

V

V

V

V

X

X

V

V

V

V

V

V

V

X

V

X

The present invention determines silicon wafer risk class, the silicon applied to defect checking machine platform by establishing height change database Piece sampling optimization.

Above by specific embodiment, invention is explained in detail, but these are not constituted to of the invention Limitation.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these It should be regarded as protection scope of the present invention.

Claims (2)

1. a kind of defect inspection method with litho machine linkage, which is characterized in that wafer is exposed after litho machine film Cheng Zhong is scanned the apparent height of silicon wafer, generates the file of apparent height 3 dimensional drawing, count greatly to measured data The risk class per a piece of silicon wafer is obtained according to analysis, high risk silicon wafer ID is added in the sampling of Yield lmproved department.

2. the method as described in claim 1, it is characterised in that:

Enabling StdDev is the sample standard deviation of silicon wafer unit；

As StdDev < 0.010, it is judged as low-risk silicon wafer unit；When all silicon wafer units are all low-risk, silicon wafer determines For low-risk silicon wafer；

As StdDev >=0.030, it is judged as high risk silicon wafer unit；When there are high risk silicon wafer unit, silicon wafer is determined as High risk silicon wafer；

As 0.030 > StdDev > 0.010, it is judged as risk silicon wafer unit；When all silicon wafer units be all risk and When low-risk, silicon wafer is determined as risk silicon wafer；

Height change lane database is recorded in high risk silicon wafer data, sends Yield lmproved department change corresponding product lot number to Sampling, will high risk silicon wafer ID be added sampling in.