CN110444177A - Shift register, gate driving circuit and display device - Google Patents
Shift register, gate driving circuit and display device Download PDFInfo
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- CN110444177A CN110444177A CN201910753541.4A CN201910753541A CN110444177A CN 110444177 A CN110444177 A CN 110444177A CN 201910753541 A CN201910753541 A CN 201910753541A CN 110444177 A CN110444177 A CN 110444177A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Crystallography & Structural Chemistry (AREA)
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Abstract
The present invention provides a kind of shift register, gate driving circuit and display device, belongs to field of display technology.The first pull-down control module in shift register of the invention is used under the control of first control signal, by the first supply voltage, controls the current potential of the first pull-down node；First pull-down node is the connecting node between the first control pull-down module and the first pull-down module；Second pull-down control module is used under the control of second control signal, by second source voltage, controls the current potential of the second pull-down node；Connecting node of the current potential of second pull-down node between the second pull-down module and the second pull-down module；First pull-down module is used under the control of the current potential of pull-up node, and the current potential of the first pull-down node is pulled down by inoperative level signal；Second pull-down module is used under the control of the current potential of pull-up node, and the current potential of the second pull-down node is pulled down by inoperative level signal.
Description
Technical field
The invention belongs to field of display technology, and in particular to a kind of shift register, gate driving circuit and display device.
Background technique
(Thin Film Transistor-Liquid Crystal Display, tft liquid crystal are aobvious by TFT-LCD
Showing device) realize that the basic principle that a frame picture is shown is to drive by grid (gate) from top to bottom successively to every one-row pixels
The square wave of input one fixed width is gated, then by signal needed for the every one-row pixels of source electrode (source) driving successively from upper
It exports down.The display device of currently manufactured such a structure is usually that gate driving circuit and source electrode drive circuit pass through
COF (Chip On Film, flip chip) or COG (Chip On Glass, chip are directly anchored on glass) technique are produced on
On glass panel, but when resolution ratio is higher, the output of gate driving circuit and source electrode drive circuit is more, driving electricity
The length on road will also increase, this will be unfavorable for pressure welding (Bonding) technique of mould group driving circuit.
In order to overcome the above problems, the manufacture of existing display device is using GOA (Gate Drive On Array) circuit
Design compares existing COF or COG technique, has not only saved cost, but also can accomplish that the symmetrical beauty in panel both sides is set
Meter, while the region Bonding and the periphery wiring space of gate driving circuit can also be saved, so that it is narrow to realize display device
The design of frame improves the production capacity and yield of display device.In order to enhance GOA pull-up node (PU point) noise reduction capability,
Pull-down node (PD point) is usually introduced, after signal output end (Output) output services level, Output and PU point is carried out
Continuous discharge, PU point and PD point are competitive relation, and in the PU charging stage, charging current is greater than discharge current, realize the charge of PU
Accumulation, PU voltage drag down PD point after increasing.But in direct current GOA noise reduction model, when due to the switching of VDD generating positive and negative voltage, under
Pull-up voltage does not drag down rapidly, causes PU that cannot normally raise, and is formed bad.
Summary of the invention
The present invention is directed at least solve one of the technical problems existing in the prior art, a kind of shift register, grid are provided
Pole driving circuit and display device.
Solving technical solution used by present invention problem is a kind of shift register, comprising: input module, output
Module, the first pull-down control module, the second pull-down control module, the first pull-down module, the second pull-down module；Wherein,
The input module, for controlling the current potential of pull-up node according to input signal；The pull-up node is input mould
Connecting node between block, output module, the first pull-down module and the second pull-down module；
The output module, for being exported by clock signal pull up signal defeated under the control of pull-up node current potential
Out；
First pull-down control module, for passing through the first supply voltage, control under the control of first control signal
The current potential of first pull-down node；First pull-down node is between the first control pull-down module and first pull-down module
Connecting node；
Second pull-down control module, for passing through second source voltage, control under the control of second control signal
The current potential of second pull-down node；The current potential of second pull-down node is between the second pull-down module and second pull-down module
Connecting node；
First pull-down module, for being pulled down by inoperative level signal under the control of the current potential of pull-up node
The current potential of first pull-down node；
Second pull-down module, for being pulled down by inoperative level signal under the control of the current potential of pull-up node
The current potential of second pull-down node.
Optionally, the shift register further include: reseting module, for passing through non-work under the control of reset signal
Make level signal to reset the current potential of the pull-up node and the signal output end.
Optionally, the reseting module includes: second transistor and the 4th transistor；Wherein,
First pole of the second transistor connects the pull-up node, and the second pole connects inoperative level terminal, control electrode
Connect reset signal end；
First pole of the 4th transistor connects the signal output end, and the second pole connects the inoperative level signal
End, control electrode connect the reset signal end.
Optionally, the shift register further includes the first noise reduction module and the second noise reduction module；Wherein,
First noise reduction module, for passing through inoperative level signal under the control of the current potential of the first pull-down node
Noise reduction is carried out to the current potential of pull-up node and signal output end；
Second noise reduction module, for passing through inoperative level signal under the control of the current potential of the second pull-down node
Noise reduction is carried out to the current potential of pull-up node and signal output end.
Optionally, first noise reduction module includes: the 9th transistor and the 11st transistor；Wherein,
First pole of the 9th transistor connects the pull-up node, and the second pole connects inoperative level terminal, control electrode
Connect first pull-down node；
First pole of the 11st transistor connects the signal output end, and the second pole connects the inoperative level
End, control electrode connect first pull-down node.
Optionally, second noise reduction module includes: the tenth transistor and the tenth two-transistor；Wherein,
First pole of the tenth transistor connects the pull-up node, and the second pole connects inoperative level terminal, control electrode
Connect first pull-down node；
First pole of the tenth two-transistor connects the signal output end, and the second pole connects the inoperative level
End, control electrode connect first pull-down node.
Optionally, the input module includes: the first transistor；Wherein,
First pole of the first transistor and control electrode are all connected with signal input part, and the second pole connects the pull-up section
Point.
Optionally, the output module includes: third transistor and storage capacitance；Wherein,
First pole of the third transistor connects clock signal terminal, the second pole connect the storage capacitance second end and
The signal output end, control electrode connect the first end and pull-up node of the storage capacitance.
Optionally, first pull-down control module includes: the 5th transistor；Wherein,
First pole of the 5th transistor connects the first power voltage terminal, and the second pole connects the first pull-down node, control
Pole connects first control signal end.
Optionally, second pull-down control module includes: the 6th transistor；Wherein,
First pole of the 6th transistor connects second source voltage end, and the second pole connects the first pull-down node, control
Pole connects second control signal end.
Optionally, first pull-down module includes: the 7th transistor；Wherein,
First pole of the 7th transistor connects first pull-down node, and the second pole connects inoperative level signal
End, control electrode connect the pull-up node.
Optionally, second pull-down module includes: the 8th transistor；Wherein,
First pole of the 8th transistor connects second pull-down node, and the second pole connects inoperative level signal
End, control electrode connect the pull-up node.
Solving technical solution used by present invention problem is a kind of gate driving circuit, including it is multiple it is cascade on
The shift register stated.
Solving technical solution used by present invention problem is a kind of display device, including above-mentioned gate driving electricity
Road.
Detailed description of the invention
Fig. 1 is the structural block diagram of the shift register of the embodiment of the present invention；
Fig. 2 is the circuit diagram of the shift register of the embodiment of the present invention.
Specific embodiment
Technical solution in order to enable those skilled in the art to better understand the present invention, with reference to the accompanying drawing and specific embodiment party
Present invention is further described in detail for formula.
Unless otherwise defined, the technical term or scientific term that the disclosure uses should be tool in disclosure fields
The ordinary meaning for thering is the personage of general technical ability to be understood." first ", " second " used in the disclosure and similar word are simultaneously
Any sequence, quantity or importance are not indicated, and are used only to distinguish different component parts.Equally, "one", " one " or
The similar word such as person's "the" does not indicate that quantity limits yet, but indicates that there are at least one." comprising " or "comprising" etc. are similar
Word mean to occur element or object before the word cover the element for appearing in the word presented hereinafter or object and its
It is equivalent, and it is not excluded for other elements or object.The similar word such as " connection " or " connected " be not limited to physics or
The connection of person's machinery, but may include electrical connection, it is either direct or indirect."upper", "lower", " left side ",
" right side " etc. is only used for indicating relative positional relationship, after the absolute position for being described object changes, then the relative positional relationship
May correspondingly it change.
Used transistor in the embodiment of the present invention can be thin film transistor (TFT) or field-effect tube or other characteristics
Identity unit, since the source electrode and drain electrode of the transistor of use is symmetrical, so its source electrode, drain electrode are not different.In
In the embodiment of the present invention, for the source electrode and drain electrode for distinguishing transistor, wherein it will be known as the first pole in a pole, another pole is known as second
Pole, grid are known as control electrode.Furthermore transistor can be divided into N-type and p-type, following embodiment according to the characteristic differentiation of transistor
In be to be illustrated with N-type transistor, when using N-type transistor, the source electrode of the first extremely N-type transistor, the second extremely N
The drain electrode of transistor npn npn, when grid input high level, source-drain electrode conducting, p-type is opposite.It is conceivable that using P-type transistor
Realization is that those skilled in the art can readily occur under that premise of not paying creative labor, therefore is also in the present invention
In the protection scope of embodiment.
It should be noted that operation level refers to that high level, inoperative level then refer to low level in the present embodiment；Phase
It answers, operation level signal end refers to that high level signal end, inoperative level signal end then refer to low level signal end VGL.
In a first aspect, as illustrated in fig. 1 and 2, it may include input mould that the present embodiment provides a kind of structures of shift register
Block, output module, reseting module, the first control pull-down module, the second pull-down control module, the first pull-down module, the second drop-down
Module, the first noise reduction module, the second noise reduction module.
Wherein, input module is used under the control of input signal, is pre-charged to pull-up node PU；Pull-up node PU
Between input module, output module, the first pull-down module, the second pull-down module, the first noise reduction module, the second noise reduction module
Connecting node.
Specifically, input module may include the first transistor M1；The grid of the first transistor M1 connects letter with source electrode
Number input terminal Input, drain electrode connection pull-up node PU.In input phase, high level signal is written to signal input part Input,
Pull-up node PU is pre-charged at this time.
Wherein, output module is used to draw high signal output end by clock signal when pull-up node PU is high level
The output of Output.
Specifically, output module may include third transistor M3 and storage capacitance C1；The source electrode of third transistor M3
Connect clock signal terminal CLK, the second end and signal output end Output of drain electrode connection storage capacitance C1, grid connection pull-up section
The first end of point PU and storage capacitance C1.When the current potential of pull-up node PU is high level, third transistor M3 is opened, clock
The clock signal that control signal end is written into is high level, at this time draws high the current potential of signal output end Output.
Wherein, reseting module is used under the control of reset signal, by low level signal by pull-up node PU and signal
The current potential of output end Output is resetted.
Specifically, reseting module includes: second transistor M2 and the 4th transistor M4；The source electrode of second transistor M2 connects
Pull-up node PU, drain electrode connection low level signal end VGL are met, grid connects reset signal end Reset；4th transistor M4's
Source electrode connection signal output end Output, drain electrode connection low level signal end VGL, grid connection signal output end Output.
When reset signal end, Reset is written into high level signal, second transistor M2 and the 4th transistor M4 are opened,
The low level signal being written by LOW signal end drags down the current potential of pull-up node PU and signal output end Output, with
Complete the reset to pull-up node PU and signal output end Output.
Wherein, the first pull-down control module is used under first control signal control, by the first supply voltage to first
The current potential of pull-down node PDA is controlled；Second pull-down control module is used under the control of second control signal, passes through second
Supply voltage controls the current potential of the second pull-down node PDB.
First pull-down module is used under the control of the current potential of pull-up node PU, is saved the first pull-up by low level signal
The current potential of point PU drags down；Second pull-down module is used under the control of pull-up node PU, is pulled down by low level signal by second
The current potential of node PDB drags down.
It should be noted that the first pull-down control module and the second pull-down control module in the present embodiment will not be same
Shi Jinhang work, usually in the gate driving circuit of application the present embodiment after the default frame of every scanning, the first drop-down control mould
Block and the second pull-down control module switch operating are primary, so, can effectively improve the service life of shift register.By
In pull-up node PU and pull-down node (the first pull-down node PDA and the second pull-down node PDB), there are competitive relation namely the two
When one high potential, another one is then low potential, therefore in the present embodiment, in input phase, the first pull-down control module and
When two pull-down control module switch operatings, such as: it will be used to control the first control signal of the first pull-down control module by high electricity
Truncation change to low level (such as: when -8V), first by the first supply voltage input low level signal (such as: -15V), will be under first
It draws the current potential of node PDA to drag down rapidly, influences being raised for pull-up node PU current potential to avoid drop-down current potential, cause undesirable ask
Topic.Similarly, when the second control signal of the second pull-down control module is switched to low level by high level, and in this way, herein
It is not described in detail.
Specifically, the first pull-down control module may include the 5th transistor M5, the second pull-down control module may include
6th transistor M6, the first pull-down module may include the 7th transistor M7, and the second pull-down module may include the 8th transistor
M8.Wherein, the source electrode of the 5th transistor M5 connects the first power voltage terminal VDDA', drain electrode the first pull-down node PDA of connection, grid
Pole connects first control signal end VDDA；The source electrode of 6th transistor M6 connects second source voltage end VDDB', drain electrode connection the
Two pull-down node PDB, grid connect second control signal end VDDB；The source electrode of 7th transistor M7 connects the first pull-down node
PDA, drain electrode connection low level signal end VGL, grid connect pull-up node PU；The second drop-down of source electrode connection of 8th transistor M8
Node PDB, drain electrode connection low level signal end VGL, grid connect pull-up node PU.When the first pull-down control module is switched to
When two pull-down modules work, in input phase, it is switched to the first control signal input terminal Input high level signal inputted
Low level signal (such as: -8V), to the first power voltage terminal VDDA' input the first supply voltage (such as: -15), at this time the 5th
Transistor M5 is opened, and rapidly drags down the current potential of the first pull-down node PDA, and so, signal input part Input is written at this time
High level signal, can be very good to charge to pull-up node PU, so that the electric position of pull-up node PU is high.Similarly, when
When second pull-down control module is switched to the work of the first pull-down module, in input phase, second control signal input terminal Input is given
The high level signal of input be switched to low level signal (such as: -8V), to second source voltage end VDDB' input second electricity
Source voltage (such as: -15), the 6th transistor M6 is opened at this time, is rapidly dragged down the current potential of the second pull-down node PDB, such one
Coming, the high level signal of signal input part Input write-in at this time can be very good to charge to pull-up node PU, so that on
Draw the electric position of node PU high.
Wherein, the first noise reduction module is used under the control of the first pull-down node PDA current potential, reduces pull-up node PU and letter
The output noise of number output end Output.
Second noise reduction module is used under the control of the current potential of the second pull-down node PDB, reduces pull-up node PU and signal
The output noise of output end Output.
It should be noted that because the first noise reduction module is controlled by the first pull-down node PDA, the second noise reduction mould
Block be controlled by the second pull-down node PDB, and the current potential of the first pull-down node PDA and the second pull-down node PDB be respectively by
What the first pull-down control module and the second pull-down control module controlled；Wherein, the first pull-down control module and the second drop-down control
Module does not work at the same time, and therefore, the first noise reduction module and the second noise reduction module are also different work.So, have
Help extend the service life of electronic device in each functional module.
Specifically, the first noise reduction module may include the 9th transistor M9 and the 11st transistor M11；Second noise reduction module
It may include the tenth transistor M10 and the tenth two-transistor M12；Wherein, the source electrode of the 9th transistor M9 connects pull-up node PU,
Drain electrode connection low level signal end VGL, grid connect the first pull-down node PDA；The source electrode connection pull-up section of tenth transistor M10
Point PU, drain electrode connection low level signal end VGL, grid connect the second pull-down node PDB；The source electrode of 11st transistor M11 connects
Signal output end Output, drain electrode connection low level signal end VGL are met, grid connects the first pull-down node PDA；12nd crystal
The source electrode connection signal output end Output of pipe M12, drain electrode connection low level signal end VGL, grid connect the second pull-down node
PDB。
Specifically, when the first pull-down node PDA is high level signal, the 9th transistor M9 and the 11st transistor M11
It is opened, the low level signal of low level signal end VGL input at this time is by the 9th transistor M9 to the current potential of pull-up node PU
Noise reduction is carried out, while noise reduction is carried out to the output of signal output end Output by the 11st transistor M11.
Similarly, when the first pull-down node PDA is high level signal, the tenth transistor M10 and the 12nd is opened, at this time
The low level signal of low level signal end VGL input carries out noise reduction by current potential of the tenth transistor M10 to pull-up node PU, together
When noise reduction carried out to the output of signal output end Output by the tenth two-transistor M12.
Second aspect, as shown in Fig. 2, the present embodiment also provides a kind of shift register, comprising: input module, output mould
Block, reseting module, the first control pull-down module, the second pull-down control module, the first pull-down module, the second pull-down module, first
Noise reduction module, the second noise reduction module.Wherein, input module includes the first transistor M1；Output module includes third transistor M3
With storage capacitance C1；Reseting module includes second transistor M2 and the 4th transistor M4；First pull-down control module includes the 5th
Transistor M5；Second pull-down control module includes the 6th transistor M6；First pull-down module includes the 7th transistor M7；Under second
Drawing-die block includes the 8th transistor M8；First noise reduction module includes the 9th transistor M9 and the 11st transistor M11；Second noise reduction
Module includes the tenth transistor M10 and the tenth two-transistor M12.
Specifically, the grid and source electrode connection signal input terminal Input of the first transistor M1, drain electrode connection pull-up node
PU.The source electrode of third transistor M3 connects clock signal terminal CLK, the second end and signal output end of drain electrode connection storage capacitance C1
Output, grid connect the first end of pull-up node PU and storage capacitance C1.The source electrode of second transistor M2 connects pull-up node
PU, drain electrode connection low level signal end VGL, grid connect reset signal end Reset；The source electrode of 4th transistor M4 connects letter
Number output end Output, drain electrode connection low level signal end VGL, grid connection signal output end Output.5th transistor M5
Source electrode connect the first power voltage terminal VDDA', drain electrode connection the first pull-down node PDA, grid connect first control signal end
VDDA；The source electrode of 6th transistor M6 connects second source voltage end VDDB', drain electrode the second pull-down node PDB of connection, and grid connects
Meet second control signal end VDDB；The source electrode of 7th transistor M7 connects the first pull-down node PDA, drain electrode connection low level signal
VGL is held, grid connects pull-up node PU；The source electrode of 8th transistor M8 connects the second pull-down node PDB, drain electrode connection low level
Signal end VGL, grid connect pull-up node PU.The source electrode of 9th transistor M9 connects pull-up node PU, drain electrode connection low level
Signal end VGL, grid connect the first pull-down node PDA；The source electrode of tenth transistor M10 connects pull-up node PU, drain electrode connection
Low level signal end VGL, grid connect the second pull-down node PDB；The source electrode connection signal output end of 11st transistor M11
Output, drain electrode connection low level signal end VGL, grid connect the first pull-down node PDA；The source electrode of tenth two-transistor M12
Connection signal output end Output, drain electrode connection low level signal end VGL, grid connect the second pull-down node PDB.
Wherein, it should be noted that the first pull-down control module and the second pull-down control module in the present embodiment
It will not work simultaneously, usually in the gate driving circuit of application the present embodiment after the default frame of every scanning, the first drop-down
Control module and the second pull-down control module switch operating are primary, so, can effectively improve the use of shift register
Service life.
The course of work of shift register in the present embodiment is illustrated, wherein cut with the first pull-down control module
It shifts to for the second pull-down module.
Input phase: low level signal is switched to the first control signal input terminal Input high level signal inputted
(such as: -8V), to the first power voltage terminal VDDA' input the first supply voltage (such as: -15), the 5th transistor M5 is beaten at this time
It opens, rapidly drags down the current potential of the first pull-down node PDA.At the same time, the high level signal of signal input part Input write-in,
It can be very good to charge to pull-up node PU, so that the electric position of pull-up node PU is high.
Output stage: due to being electrically charged in input phase storage capacitance C1, the current potential of pull-up node PU is further pulled up,
Third transistor M3 is opened at this time, and the clock signal of high level is written in the first clock signal terminal CLK, and passes through signal output end
Output is exported, and at the same time, since pull-up node PU is high potential, the 7th transistor M7 and the 8th transistor M8 are beaten
It opens, the first pull-down node PDA and the second pull-down node PDB are pulled low.
Reseting stage: the reset signal that reset signal end Reset is written is high level signal, second transistor M2 and the
Four transistor M4 are opened, the low level signal being written at this time by LOW signal end, by pull-up node PU and signal output end
The current potential of Output drags down, to complete the reset to pull-up node PU and signal output end Output.At the same time, the first control
Signal end VDDA input high level signal is pulled up by the first supply voltage of the first power voltage terminal VDDA' write-in by first
Node PU is drawn high, at this point, the 9th transistor M9 and the 11st transistor M11 are opened, passes through low level signal end VGL input
Low level signal carries out noise reduction to the output of pull-up node PU and signal output end Output.
The third aspect, the present embodiment also provide a kind of gate driving circuit and display device, wherein gate driving circuit packet
Include multiple cascade above-mentioned any shift registers.Display device includes above-mentioned gate driving circuit.
Wherein, the display device in the present embodiment can be Electronic Paper, oled panel, mobile phone, tablet computer, television set,
Any products or components having a display function such as display, laptop, Digital Frame, navigator.
It is understood that the principle that embodiment of above is intended to be merely illustrative of the present and the exemplary implementation that uses
Mode, however the present invention is not limited thereto.For those skilled in the art, essence of the invention is not being departed from
In the case where mind and essence, various changes and modifications can be made therein, these variations and modifications are also considered as protection scope of the present invention.
Claims (14)
1. a kind of shift register characterized by comprising input module, output module, the first pull-down control module, second
Pull-down control module, the first pull-down module, the second pull-down module；Wherein,
The input module, for controlling the current potential of pull-up node according to input signal；The pull-up node is input module, defeated
Connecting node between module, the first pull-down module and the second pull-down module out；
The output module, the output for being exported by clock signal pull up signal under the control of pull-up node current potential；
First pull-down control module, for passing through the first supply voltage, control first under the control of first control signal
The current potential of pull-down node；First pull-down node is the connection between the first control pull-down module and first pull-down module
Node；
Second pull-down control module, for passing through second source voltage, control second under the control of second control signal
The current potential of pull-down node；Company of the current potential of second pull-down node between the second pull-down module and second pull-down module
Connect node；
First pull-down module, for passing through inoperative level signal drop-down first under the control of the current potential of pull-up node
The current potential of pull-down node；
Second pull-down module, for passing through inoperative level signal drop-down second under the control of the current potential of pull-up node
The current potential of pull-down node.
2. shift register according to claim 1, which is characterized in that the shift register further include: reseting module,
For under the control of reset signal, by inoperative level signal by the current potential of the pull-up node and the signal output end
It is resetted.
3. shift register according to claim 2, which is characterized in that the reseting module include: second transistor and
4th transistor；Wherein,
First pole of the second transistor connects the pull-up node, and the second pole connects inoperative level terminal, control electrode connection
Reset signal end；
First pole of the 4th transistor connects the signal output end, and the second pole connects inoperative level signal end,
Control electrode connects the reset signal end.
4. shift register according to claim 1, which is characterized in that the shift register further includes the first noise reduction mould
Block and the second noise reduction module；Wherein,
First noise reduction module, under the control of the current potential of the first pull-down node, by inoperative level signal to upper
The current potential of node and signal output end is drawn to carry out noise reduction；
Second noise reduction module, under the control of the current potential of the second pull-down node, by inoperative level signal to upper
The current potential of node and signal output end is drawn to carry out noise reduction.
5. shift register according to claim 4, which is characterized in that first noise reduction module includes: the 9th crystal
Pipe and the 11st transistor；Wherein,
First pole of the 9th transistor connects the pull-up node, and the second pole connects inoperative level terminal, control electrode connection
First pull-down node；
First pole of the 11st transistor connects the signal output end, and the second pole connects the inoperative level terminal, control
Pole processed connects first pull-down node.
6. shift register according to claim 4, which is characterized in that second noise reduction module includes: the tenth crystal
Pipe and the tenth two-transistor；Wherein,
First pole of the tenth transistor connects the pull-up node, and the second pole connects inoperative level terminal, control electrode connection
First pull-down node；
First pole of the tenth two-transistor connects the signal output end, and the second pole connects the inoperative level terminal, control
Pole processed connects first pull-down node.
7. shift register according to claim 1, which is characterized in that the input module includes: the first transistor；Its
In,
First pole of the first transistor and control electrode are all connected with signal input part, and the second pole connects the pull-up node.
8. shift register according to claim 1, which is characterized in that the output module include: third transistor and
Storage capacitance；Wherein,
First pole of the third transistor connects clock signal terminal, and the second pole connects the second end of the storage capacitance and described
Signal output end, control electrode connect the first end and pull-up node of the storage capacitance.
9. shift register according to claim 1, which is characterized in that first pull-down control module includes: the 5th
Transistor；Wherein,
First pole of the 5th transistor connects the first power voltage terminal, and the second pole connects the first pull-down node, and control electrode connects
Connect first control signal end.
10. shift register according to claim 1, which is characterized in that second pull-down control module includes: the 6th
Transistor；Wherein,
First pole of the 6th transistor connects second source voltage end, and the second pole connects the first pull-down node, and control electrode connects
Connect second control signal end.
11. shift register according to claim 1, which is characterized in that first pull-down module includes: the 7th crystal
Pipe；Wherein,
First pole of the 7th transistor connects first pull-down node, and the second pole connects inoperative level signal end, control
Pole processed connects the pull-up node.
12. shift register according to claim 1, which is characterized in that second pull-down module includes: the 8th crystal
Pipe；Wherein,
First pole of the 8th transistor connects second pull-down node, and the second pole connects inoperative level signal end, control
Pole processed connects the pull-up node.
13. a kind of gate driving circuit, which is characterized in that including multiple cascade as of any of claims 1-12
Shift register.
14. a kind of display device, which is characterized in that including the gate driving circuit described in claim 13.
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