CN110444141B - Grid drive circuit of display panel and display device - Google Patents
Grid drive circuit of display panel and display device Download PDFInfo
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- CN110444141B CN110444141B CN201910564583.3A CN201910564583A CN110444141B CN 110444141 B CN110444141 B CN 110444141B CN 201910564583 A CN201910564583 A CN 201910564583A CN 110444141 B CN110444141 B CN 110444141B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Abstract
The application discloses a gate driving circuit of a display panel and a display device. The display panel is provided with a plurality of scanning lines, and the grid driving circuit comprises a multi-stage grid driving sub-circuit, a multi-stage buffer and a plurality of protection circuits; the multi-stage grid driving sub-circuits are connected with the scanning lines in a one-to-one correspondence manner; the multi-stage buffers are respectively arranged in one-to-one correspondence with the grid driving sub-circuits; a plurality of protection circuits provided in one-to-one correspondence with the scanning lines; the protection circuit comprises an error amplification unit, a comparison unit and a control module; the error amplification unit detects and amplifies a voltage difference value between the input end and the output end of the buffer to obtain an error amplification difference voltage; the comparison unit outputs a comparison result signal according to the error amplification difference voltage; and the control module outputs a control signal according to the comparison result signal to control the buffer to be opened or disconnected with the scanning line. The protection circuit can prevent the situation that the grid driving circuit is burnt out due to short circuit between the scanning lines.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to a gate driving circuit of a display panel and a display device.
Background
With the development of large-scale, high-resolution, and high-resolution display panels and the improvement of display quality requirements, high PPI (Pixels Per Inch) enables thinner and thinner signal lines and smaller line pitches, and greatly increases the probability of short circuit between signal lines.
For example, the display panel includes a gate driving circuit, which is respectively connected to each scan line of the display panel, and the gate driving circuit needs to output a high level signal or a low level signal to the scan line according to a timing sequence to control the active switch connected to the scan line to be turned on or off, so that when a short circuit occurs between adjacent scan lines, the high level voltage signal and the low level voltage signal are turned on, and the gate driving circuit is at risk of being burned out after long-time operation. Therefore, how to detect the short circuit of the scan line is a technical problem to be solved by those skilled in the art
Disclosure of Invention
The application aims to provide a grid driving circuit of a display panel and a display device, and the grid driving circuit is prevented from being burnt out due to short circuit between scanning lines.
The application discloses display panel's gate drive circuit, display panel is provided with many scanning lines, gate drive circuit includes: the circuit comprises a multi-stage grid electrode driving sub-circuit, a multi-stage buffer and a plurality of protection circuits; the multi-stage grid driving sub-circuits are connected with the scanning lines in a one-to-one correspondence manner; the multistage buffers are respectively arranged in one-to-one correspondence with the grid driving sub-circuits, one end of each buffer is connected to the output end of each grid driving sub-circuit, and the other end of each buffer is connected to the scanning line; the protection circuits are arranged in one-to-one correspondence with the scanning lines; the protection circuit includes: the device comprises an error amplifying unit, a comparing unit and a control module; the error amplification unit detects and amplifies a voltage difference value between the input end and the output end of the buffer to obtain an error amplification difference voltage; the input end of the comparison unit is connected with the output end of the error amplification circuit, the output end of the comparison unit is connected with the control module, and the comparison unit receives the error amplification difference voltage and outputs a comparison result signal according to the error amplification difference voltage; and the input end of the control module is connected to the output end of the comparison unit, and the control module receives the comparison result signal and outputs a control signal according to the comparison result signal so as to control the buffer to be opened or disconnected from the scanning line.
Optionally, the error amplifying unit includes: a first error amplifier and a second error amplifier; the positive phase input end is connected with the input end of the buffer, the negative phase input end is connected with the output end of the buffer, and the voltage difference value between the input end and the output end of the buffer is calculated and amplified to output a first error amplification difference voltage; the positive phase input end of the second error amplifier is connected with the output end of the buffer, the negative phase input end of the second error amplifier is connected with the input end of the buffer, and the voltage difference value between the output end and the input end of the buffer is calculated and amplified to output a second error amplification difference voltage; the comparison unit includes: a first comparator and a second comparator; the positive phase input end of the first comparator is connected to the output end of the first error amplifier to receive the first error amplification difference voltage, and the output end of the first comparator is connected to the control module; a positive phase input end of the second comparator is connected to an output end of the second error amplifier to receive the second error amplified difference voltage, and an output end of the second comparator is connected to the control module; the inverting input ends of the first comparator and the second comparator are connected to a preset voltage; the first comparator outputs a first comparison result signal to the control module according to a comparison result of the first error amplification difference voltage and a preset voltage, and the second comparator outputs a second comparison result signal to the control module according to a comparison result of the second error amplification difference voltage and the preset voltage; and the control module outputs a control signal according to the comparison result signal to control the buffer to be opened or disconnected with the scanning line.
Optionally, the preset voltage satisfies the following formula:
VGL＜ADJ＜VGH；
the voltage regulator comprises a gate driving circuit, an ADJ, a VGH, and a VGL, wherein the ADJ is a preset voltage, the VGH is a high level voltage output by the gate driving circuit, and the VGL is a low level voltage output by the gate driving circuit.
Optionally, the preset voltage satisfies the following formula:
ADJ＝(VGH+VGL)/2。
optionally, the control module includes an or gate device and a control unit, and input ends of the or gate device are respectively connected to output ends of the first comparator and the second comparator; the control end of the control unit is connected to the output end of the OR gate device, the input end of the control unit is connected to the output end of the buffer, the output end of the control unit is connected to the scanning line, and the control unit is a low-level conducting switch; when one of the first comparison result signal and the second comparison result signal is a high level signal, the or gate device outputs a high level control signal to the control unit to control disconnection of the buffer from the scan line; and when the first comparison result signal and the second comparison result signal are both low-level signals, the OR gate device outputs a low-level control signal to the control unit to control the buffer to be opened to be connected with the scanning line.
Optionally, the control module includes a first switch, a second switch and a control unit; the first switch and the second switch are high-level conducting switches, and the control unit is a low-level conducting switch; the grid electrode of the first switch is connected to the output end of the first comparator, the source end of the first switch is connected with a high-level signal, and the drain end of the first switch is connected with the control unit; the grid electrode of the second switch is connected with the output end of the second comparator, the source end of the second switch is connected with a high-level signal, and the drain end of the second switch is connected with the control unit.
Optionally, the control unit includes a transmission gate.
Optionally, the buffer includes 2n stages of inverters, where n is a natural number greater than or equal to 1.
The application also discloses display panel's gate drive circuit, display panel is provided with many scanning lines, gate drive circuit includes: the circuit comprises a multi-stage grid electrode driving sub-circuit, a multi-stage buffer and a protection circuit; the multi-stage grid driving sub-circuits are connected with the scanning lines in a one-to-one correspondence manner; the multistage buffers are respectively arranged in one-to-one correspondence with the grid driving sub-circuits, one end of each buffer is connected to the output end of each grid driving sub-circuit, and the other end of each buffer is connected to the scanning line; the protection circuits are arranged in one-to-one correspondence with the scanning lines; the protection circuit includes: a first error amplifier, a second error amplifier, a first comparator, a second comparator, an OR gate device, and a transmission gate; the positive phase input end of the first error amplifier is connected with the input end of the buffer, the negative phase input end of the first error amplifier is connected with the output end of the buffer, and the voltage difference value between the input end and the output end of the buffer is calculated and amplified to output a first error amplification difference voltage; the positive phase input end of the second error amplifier is connected with the output end of the buffer, the negative phase input end of the second error amplifier is connected with the input end of the buffer, and the voltage difference value between the output end and the input end of the buffer is calculated and amplified to output a second error amplification difference voltage; the positive phase input end of the first comparator is connected to the output end of the first error amplifier to receive the first error amplification difference voltage, the negative phase input end of the first comparator is connected to a preset voltage, and the output end of the first comparator is connected to the control module; a positive phase input end of the second comparator is connected to an output end of the second error amplifier to receive the second error amplified difference voltage, a negative phase input end of the second comparator is connected to the preset voltage, and an output end of the second comparator is connected to the control module; the input end of the OR gate device is respectively connected with the output ends of the first comparator and the second comparator, and outputs a control signal according to the received first comparison result signal and the second comparison result signal; the transmission gate receives the control signal and controls to open or disconnect the connection between the buffer and the scanning line; when the voltage of the input end of the buffer is the same as that of the output end of the buffer, and both the first error amplification difference voltage and the second error amplification difference voltage are smaller than the preset voltage, both the first comparison result signal and the second comparison result signal output by the first comparator and the second comparator are at a low level, the or gate device outputs the control signal at the low level, the transmission gate is opened after receiving the control signal at the low level, and the buffer is connected with the scanning line; when the voltage of the input end of the buffer is different from the voltage of the output end of the buffer, the first error amplification difference voltage and the second error amplification difference voltage are both smaller than the preset voltage, the first comparison result signal and the second comparison result signal output by the first comparator and the second comparator are both at a low level, the OR gate device outputs a control signal at a low level, the transmission gate receives the control signal at a high level and then is closed, and the buffer is disconnected with the scanning line.
The application also discloses a display device which comprises the grid drive circuit of the display panel.
When a short circuit occurs between adjacent scanning lines in a display panel, a high level signal and a low level signal are in short circuit in a gate driving circuit, so that the gate driving circuit is burnt, a protection circuit is required to be arranged in the gate driving circuit and is arranged between a buffer and the scanning lines to control whether signals of the buffer are transmitted to the scanning lines, wherein an error amplification unit obtains voltages of an input end and an output end of the buffer, when the voltages of the input end and the output end of the buffer are output, the error amplification unit can still work and output an error amplification difference voltage, a comparison result signal is obtained and output to a control module after comparison of the comparison unit, therefore, when the voltage does not exist at the input end of the buffer or the voltage does not exist at the output end of the buffer, the protection circuit protects the gate driving circuit to ensure that no voltage exists at the input end or the output end, the protection circuit can still work to prevent a row of high level signals conducted by the grid drive circuit from being transmitted to a row of scanning lines which are not conducted, so that the high level signals of the low level signals are in short circuit, and the grid drive circuit is ensured to be fully protected.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
FIG. 1 is a schematic diagram of an exemplary scan line distribution within a display panel;
FIG. 2 is a schematic diagram of an exemplary scan line short circuit in a display panel;
FIG. 3 is a schematic diagram of an exemplary gate drive circuit short circuit;
FIG. 4 is a schematic diagram of an exemplary gate drive circuit turning on a corresponding row;
FIG. 5 is a schematic diagram of an exemplary gate drive circuit turning off a corresponding row;
FIG. 6 is a waveform diagram of an exemplary gate drive circuit normal output;
FIG. 7 is a waveform diagram of an exemplary gate drive circuit short circuit output;
FIG. 8 is a schematic diagram of a display device according to an embodiment of the present application;
FIG. 9 is a diagram of a gate driving circuit according to an embodiment of the present application;
FIG. 10 is a schematic diagram of a protection circuit according to an embodiment of the present application;
FIG. 11 is a schematic diagram of another protection circuit according to an embodiment of the present application;
fig. 12 is a schematic diagram of a protection circuit according to another embodiment of the present application.
100, a gate driving circuit; 110. a buffer; 111. an inverter; 120. a protection circuit; 130 an error amplification unit; 140. a comparison unit; 150. a control module; 151. a control unit; 200. a display panel; 210. scanning a line; 300. a display device.
Detailed Description
It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or combinations thereof may be present or added.
Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.
Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, fixed connections, removable connections, and integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
Fig. 1 is a schematic diagram of distribution of scan lines in a display panel, fig. 2 is a schematic diagram of short circuit of scan lines in the display panel, fig. 3 is a schematic diagram of short circuit of a gate driving circuit, and fig. 4 is a schematic diagram of opening corresponding rows of the gate driving circuit; FIG. 5 is a schematic diagram of the gate drive circuit turning off the corresponding row; as shown in fig. 1 to 5, the display panel employs a gate driving circuit as panel scan driving, and the gate driving circuit 100 is connected to the scan lines 210 in the panel display area of the display panel 200 using the buffer 110. The gate driving circuit 100 is connected to the scan lines 210, and when a short circuit occurs between adjacent scan lines 210, a conduction path exists between adjacent scan lines 210.
As shown in fig. 6 and 7, the solid line in the figure is the waveform output from the input terminal of the buffer, the dotted line is the waveform output from the output terminal of the buffer, fig. 6 is the waveform diagram of the normal output of the gate driving circuit, and the waveforms of the input terminal and the output terminal of the buffer are the same; FIG. 7 is a waveform of a gate driving circuit short-circuited output, wherein when the Gn row and the Gn +1 row scan lines are short-circuited, the waveforms output by the input and output terminals of the Gn row and Gn +1 row buffers are different, and when the Gn row is opened, the waveform at the G 'n output terminal of the Gn row is pulled low, the waveform at the G' n +1 position corresponding to the Gn +1 row is pulled high, and the waveform at Gn is kept unchanged; when Gn +1 row is opened, the waveform at the position of G 'n +1 is pulled down, the waveform at the position of G' n is pulled up, the waveform at the position of Gn +1 is kept unchanged, and because the voltage output by the gate driving circuit 100 is a high-level voltage signal VGH and a low-level voltage signal VGL, when a short circuit condition exists, the high-level voltage signal VGH output by the Gn row is in short circuit with the low-level voltage signal VGL output by the Gn +1 row, so that the gate driving circuit has the risk of being burnt
The present application is described in detail below with reference to the figures and alternative embodiments.
Fig. 8 is a schematic diagram of a display device according to an embodiment of the present application, and fig. 9 is a schematic diagram of a gate driving circuit according to an embodiment of the present application; as shown in fig. 8 and 9, as an embodiment of the present application, a display device 100 is disclosed, which includes a display panel 200 and a gate driving circuit 100 of the display panel 200, wherein the gate driving circuit 100 includes: a multi-stage gate driving sub-circuit, a multi-stage buffer 110, and a plurality of protection circuits 120; the multiple stages of gate driving sub-circuits are connected with the scanning lines 210 in a one-to-one correspondence manner; the multiple stages of buffers 110 are respectively arranged in one-to-one correspondence with the gate driving sub-circuits, one end of each buffer is connected to the output end of the gate driving sub-circuit, and the other end of each buffer is connected to the scanning line 210; the plurality of protection circuits 120 are arranged in one-to-one correspondence with the scan lines 210; the protection circuit 120 includes: an error amplifying unit 130, a comparing unit 140 and a control module 150; the error amplifying unit 130 detects and amplifies a voltage difference between an input terminal and an output terminal of the buffer 110 to obtain an error amplified difference voltage; the input end of the comparing unit 140 is connected to the output end of the error amplifying circuit, the output end of the comparing unit 140 is connected to the control module 150, and the comparing unit 140 receives the error amplified difference voltage and outputs a comparison result signal according to the error amplified difference voltage; the input terminal of the control module 150 is connected to the output terminal of the comparison unit 140, and the control module 150 receives the comparison result signal and outputs a control signal CTRL according to the comparison result signal to control the buffer 110 to be opened or disconnected from the scan line 210.
When a short circuit occurs between adjacent scan lines 210 in the display panel 200, a short circuit of a high level signal and a low level signal occurs in the gate driving circuit 100, which results in a situation that the gate driving circuit 100 is burned out, but in the present application, a protection circuit 120 is disposed inside the gate driving circuit 100, the protection circuit 120 is disposed between the buffer 110 and the scan lines 210, and controls whether a signal of the buffer 110 is transmitted to the scan lines 210, wherein the error amplification unit 130 obtains voltages of an input end and an output end of the buffer 110, when there is no voltage output at the input end and the output end of the buffer 110, the error amplification unit 130 can still work and output an error amplification difference voltage, and a comparison result signal obtained by comparison by the comparison unit 140 is output to the control module 150, therefore, when there is no voltage at the input end or no voltage at the output end of the buffer 110, the protection circuit 120 protects the gate driving circuit 100, the protection circuit 120 can still work to prevent the high level signal of one row that the gate driving circuit 100 is turned on from being transmitted to the scan line 210 of one row that is turned off, so that the high level signal of the low level signal is shorted, and the gate driving circuit 100 is fully protected. In particular, compared with a scheme that only the comparator is arranged, when no voltage is output at the input end and the output end of the buffer 110, the comparator has no output, the application range is wider, and the accuracy is higher.
Fig. 10 is a schematic diagram of a protection circuit 120 according to an embodiment of the present application, and as shown in fig. 10, the error amplifying unit 130 includes: a first error amplifier EA1 and a second error amplifier EA 2; a non-inverting input terminal of the first error amplifier EA1 is connected to the input terminal of the buffer 110, an inverting input terminal thereof is connected to the output terminal of the buffer 110, and a voltage difference between the input terminal and the output terminal of the buffer 110 is calculated and amplified to output a first error amplified difference voltage; a non-inverting input terminal of the second error amplifier EA2 is connected to the output terminal of the buffer 110, an inverting input terminal of the second error amplifier EA2 is connected to the input terminal of the buffer 110, and a voltage difference between the output terminal and the input terminal of the buffer 110 is calculated and amplified to output a second error amplified difference voltage;
the comparison unit 140 includes: a first comparator COMP1 and a second comparator COMP 2; a non-inverting input terminal of the first comparator COMP1 is connected to an output terminal of the first error amplifier EA1 to receive the first error amplified difference voltage, and an output terminal is connected to the control module 150; a non-inverting input terminal of the second comparator COMP2 is connected to the output terminal of the second error amplifier EA2 to receive the second error amplified difference voltage, and an output terminal is connected to the control module 150; the inverting input ends of the first comparator COMP1 and the second comparator COMP2 are connected to a preset voltage ADJ; the first comparator COMP1 outputs a first comparison result signal to the control module 150 according to a comparison result between the first error amplified difference voltage and a preset voltage ADJ, and the second comparator COMP2 outputs a second comparison result signal to the control module 150 according to a comparison result between the second error amplified difference voltage and the preset voltage ADJ; the control module 150 outputs a control signal CTRL to control the buffer 110 to be opened or disconnected from the scan line 210 according to the comparison result signal.
The opposite positions of the detection buffers 110 of the first error amplifier EA1 and the second error amplifier EA 2; when the voltage at the input end of the buffer 110 is higher than the voltage at the output end, the voltage calculated by the first error amplifier EA1 is a positive difference voltage, the voltage calculated by the second error amplifier EA2 is a negative difference voltage, and both the difference voltages are output to the comparing unit 140 to be compared with the preset voltage ADJ. Of course, only one error amplifier may be used in the present application, and an absolute value circuit is disposed at the next stage of the error amplifier, and when receiving a positive voltage, the absolute value circuit passes through the positive circuit normally, and when receiving a negative voltage, the absolute value circuit converts the electrical property into a positive polarity, and the voltage value is unchanged, and then is output to the comparison unit 140.
The comparing unit 140 is provided with two, the non-inverting input terminal of the first comparator COMP1 receives the first error amplified difference voltage, comparing with the preset voltage ADJ, the non-inverting input terminal of the second comparator COMP2 receives the second error amplified difference voltage and compares with the preset voltage ADJ, the first error amplified difference voltage and the second error amplified difference voltage have the same voltage value but opposite polarity, at least one of the difference voltages is less than the preset voltage ADJ, so that one of the first comparator COMP1 and the second comparator COMP2 outputs a high-level comparison result signal, the other outputs a low-level comparison result signal, or both output low level comparison result signals to ensure that the voltage at any one of the two ends of the buffer 110 is lower than the voltage at the other end, one of the two comparators must output a high level comparison result signal, when the voltages of both ends of the buffer 110 are equal, both comparators output low level comparison result signals.
Wherein, the preset voltage satisfies the following formula:
VGL＜ADJ＜VGH；
ADJ is a predetermined voltage, VGH is a high level voltage output by the gate driving circuit 100, and VGL is a low level voltage output by the gate driving circuit 100. Of course, the preset voltage may also set the following formula:
ADJ＝(VGH+VGL)/2。
since the voltage obtained by the error amplifier is the voltage of the output end and the input end of the buffer 110, and the output voltage is the difference amplified voltage of the input end and the output end, the value of the error amplified difference voltage can be between the high level voltage and the low level voltage output by the gate driving circuit 100, and of course, an intermediate value can also be taken, so that the comparator can accurately compare the difference voltage of the output end and the input end of the buffer 110, and the comparison result signal output after comparison is ensured to be correct.
The control module 150 comprises an OR gate device OR and a control unit 151, wherein input ends of the OR gate device OR are respectively connected to output ends of the first comparator COMP1 and the second comparator COMP 2; a control terminal of the control unit 151 is connected to an output terminal of the OR gate device OR, an input terminal of the control unit 151 is connected to an output terminal of the buffer 110, an output terminal of the control unit is connected to the scan line 210, and the control unit 151 is a low-level conducting switch; when one of the first comparison result signal and the second comparison result signal is a high level signal, the OR gate device OR outputs the high level signal to the control unit 151 to control to disconnect the buffer 110 from the scan line 210; when both the first comparison result signal and the second comparison result signal are low level signals, the OR gate device OR outputs a low level to the control unit 151 to control to open the connection of the buffer 110 and the scan line 210.
The OR gate device OR disposed in the control module 150 receives the first comparison result signal and the second comparison result signal, outputs a high level control signal CTRL as long as the OR gate device OR receives the high level control signal CTRL, and outputs a low level control signal CTRL only when the received signals are all low level signals; that is, when the voltages at the two ends of the buffer 110 are different, one of the first comparison result signal and the second comparison result signal must be a high-level comparison signal, and the OR gate device OR outputs a high-level control signal CTRL accordingly, the control signal CTRL is transmitted to the control unit 151 to control the connection OR disconnection between the buffer 110 and the scan line 210.
FIG. 11 is a schematic diagram of another protection circuit 120 according to an embodiment of the present application; as shown in fig. 11, the control module 150 of the present application may also be provided as a first switch M1, a second switch M2, and a control unit 151; the first switch M1 and the second switch M2 are high-level conducting switches, and the control unit 151 is a low-level conducting switch; a gate of the first switch M1 is connected to an output terminal of the first comparator COMP1, a source terminal is connected to a high level signal, and a drain terminal is connected to the control unit 151; a gate of the second switch M2 is connected to an output terminal of the second comparator COMP2, a source terminal is connected to a high level signal, and a drain terminal is connected to the control unit 151. The first switch M1 and the second switch M2 of the present application are both N-type switches, that is, the first switch M1 and the second switch M2 receive a high level signal to turn on, and receive a low level signal to turn off, the source terminals of the first switch M1 and the second switch M2 are both connected to a high level, the drain terminals of the first switch M1 and the second switch M2 are both connected to the control unit 151, when the first switch M1 and the second switch M2 are turned on, the first switch M1 and the second switch M2 both output a high level signal, and the function of the OR gate device OR is the same. Of course, other circuits may be provided in the present application, and the function of the OR gate device OR may be the same.
The control module 150 further includes a first resistor R1, one end of the first resistor R1 is grounded, and the other end is connected between the drain terminals of the first switch M1 and the second switch M2 and the control unit 151, and the first resistor R1 enables the control unit 151 to receive a low-level signal when the first switch M1 and the second switch M2 are both turned off, and does not affect the transmission of the high-level signal to the control unit 151 when turned on.
Unlike the previous embodiment, this embodiment uses only one error amplifier, and an absolute value circuit is provided at the next stage of the error amplifier, and the absolute value circuit normally passes when receiving a positive voltage, when receiving negative voltage, the electric property is converted into positive polarity, the voltage value is unchanged, and then the positive difference voltage is output to the comparator, the comparator receives the positive difference voltage and compares the positive difference voltage with the preset voltage ADJ, when the positive difference voltage is greater than the preset voltage ADJ, the comparator outputs a high level control signal CTRL, when the positive delta voltage is less than the preset voltage ADJ, the comparator outputs a low level comparison result signal, the comparison result signal is directly output to the control unit 151, the buffer 110 is controlled to be connected or disconnected with the scan line 210 by the control unit 151, by such an arrangement, an error amplifier, a comparator and an OR gate device OR can be reduced, and an absolute value circuit is added, so that the voltage across the buffer 110 can be detected. Of course, the present application is not limited to these two embodiments, and other methods may be used to protect the short circuit of the scan line 210.
The control unit 151 of the present application includes a transmitter, and the transmission gate TG controls the connection between the buffer 110 and the scan line 210 after receiving the control signal CTRL, turns on the connection between the buffer 110 and the scan line 210 when receiving a low-level signal, and turns off the connection between the buffer 110 and the scan line 210 when receiving a high-level signal. The application can also be provided with a third switch to replace the transmission gate TG, the third switch is a P-type MOS and the like, the receiving low-level signal is turned on, and the receiving high-level signal is turned off.
The buffer 110 includes a2 n-stage inverter 111, where n is a natural number greater than or equal to 1. In the present application, for example, n is 1, and even though two inverters 111 are used, the voltages output from the input terminal and the output terminal of the buffer 110 are ensured to be the same, but n may be larger and may be applied.
FIG. 12 is a schematic diagram of a protection circuit 120 according to another embodiment of the present application; as shown in fig. 12, as another embodiment of the present application, a gate driving circuit 100 of a display panel 200 is disclosed, the display panel 200 is provided with a plurality of scan lines 210, and the gate driving circuit 100 includes: a multi-stage gate driving sub-circuit, a multi-stage buffer 110, and a protection circuit 120; the multiple stages of gate driving sub-circuits are connected with the scanning lines 210 in a one-to-one correspondence manner; the multiple stages of buffers 110 are respectively arranged in one-to-one correspondence with the gate driving sub-circuits, one end of each buffer is connected to the output end of the gate driving sub-circuit, and the other end of each buffer is connected to the scanning line 210; the plurality of protection circuits 120 are arranged in one-to-one correspondence with the scan lines 210; the protection circuit 120 includes: a first error amplifier EA1, a second error amplifier EA2, a first comparator COMP1, a second comparator COMP2, an OR gate device OR, and a transmission gate TG; a non-inverting input terminal of the first error amplifier EA1 is connected to the input terminal of the buffer 110, an inverting input terminal thereof is connected to the output terminal of the buffer 110, and a voltage difference between the input terminal and the output terminal of the buffer 110 is calculated and amplified to output a first error amplified difference voltage; a second error amplifier EA2 having a non-inverting input terminal connected to the output terminal of the buffer 110 and an inverting input terminal connected to the input terminal of the buffer 110, and calculating and amplifying a voltage difference between the output terminal and the input terminal of the buffer 110 to output a second error amplified difference voltage; a positive phase input end of the first comparator COMP1 is connected to an output end of the first error amplifier EA1 to receive the first error amplified difference voltage, an inverted phase input end of the first comparator COMP1 is connected to a preset voltage ADJ, and an output end of the first comparator COMP1 is connected to the control module 150; a positive-phase input end of the second comparator COMP2 is connected to the output end of the second error amplifier EA2 to receive the second error amplified difference voltage, an inverted-phase input end of the second comparator COMP2 is connected to the preset voltage ADJ, and an output end of the second comparator COMP2 is connected to the control module 150; the input end of the OR gate device OR is respectively connected to the output ends of the first comparator COMP1 and the second comparator COMP2, and receives and outputs a control signal CTRL according to the first comparison result signal and the second comparison result signal; the transmission gate TG receives the control signal CTRL to control the buffer 110 to be opened or disconnected from the scan line 210; when the voltage at the input end of the buffer 110 is the same as the voltage at the output end of the buffer 110, and both the first error amplification difference voltage and the second error amplification difference voltage are smaller than the preset voltage ADJ, both the first comparison result signal and the second comparison result signal output by the first comparator COMP1 and the second comparator COMP2 are at a low level, the OR gate device OR outputs the control signal CTRL at a low level, the transmission gate TG is opened after receiving the control signal CTRL at the low level, and the buffer 110 is connected to the scan line 210; when the voltage at the input end of the buffer 110 is different from the voltage at the output end of the buffer 110, and both the first error amplification difference voltage and the second error amplification difference voltage are smaller than the preset voltage ADJ, both the first comparison result signal and the second comparison result signal output by the first comparator COMP1 and the second comparator COMP2 are at a low level, the OR gate device OR outputs the control signal CTRL at a low level, the transmission gate TG is closed after receiving the control signal CTRL at a high level, and the buffer 110 is disconnected from the scan line 210.
When a short circuit occurs between adjacent scan lines 210, the current scan line 210 is opened, the buffer 110 outputs a high level, after the short circuit occurs, the next scan line 210 has a high level signal, and the next buffer 110 outputs a low level signal, so that the voltages at the input end and the output end of the next buffer 110 are different, the high level signal and the low level signal are shorted, and the gate driving circuit 100 is burned out.
A non-inverting input terminal of the first error amplifier EA1 is connected to the output terminal of the buffer 110, and an inverting input terminal thereof is connected to the output terminal of the buffer 110; the non-inverting input terminal of the second error amplifier EA2 is connected to the output terminal of the buffer 110, the inverting input terminal of the second error amplifier EA2 is connected to the input terminal of the buffer 110, and the first error amplifier EA1 and the second error amplifier EA2 ensure that when the voltages at the output terminal and the input terminal of the buffer 110 are different, a difference of positive output polarity is always generated between the two error amplifiers; a positive phase input end of the first comparator COMP1 receives the first error amplified difference voltage, and a negative phase input end is connected with a preset voltage ADJ; the positive phase input end of the second comparator COMP2 receives the second error amplified difference voltage, the negative phase input end is connected to the preset voltage ADJ, when the voltages at the output end and the input end of the buffer 110 are different, there must be a difference voltage higher than the preset voltage ADJ in the first error amplified difference voltage and the second error amplified difference voltage, so that the corresponding comparator outputs a high level signal, when passing through the OR gate device OR, as long as a signal has a high level, the OR gate device OR will output a high level signal, after the output gate receives the high level signal, the connection between the buffer 110 and the scan line 210 is disconnected, the high level signal output by the current row is prevented from being shorted with the low level signal output by the next row, and the gate driving circuit 100 is prevented from being burnt out. When the voltages of the output terminal and the input terminal of the buffer 110 are the same, both the error amplifiers output low level signals, correspondingly, both the comparators output low level control signals CTRL, the OR gate device OR outputs low level control signals CTRL, the transmission gate TG receives the low level control signals CTRL and then turns on the buffer 110 and the scan lines 210, so that the buffer 110 outputs normally, when the next scan line 210 is opened and the previous scan line 210 is closed, the protection circuit 120 in the current row repeats the above steps, and the gate driving circuit 100 is protected.
The technical solution of the present application can be widely applied to various display panels, such as TN (Twisted Nematic) display panel, IPS (In-Plane Switching) display panel, VA (Vertical Alignment) display panel, MVA (Multi-Domain Vertical Alignment) display panel, and of course, other types of display panels, such as OLED (Organic Light-Emitting Diode) display panel, and the above solution can be applied thereto.
The foregoing is a more detailed description of the present application in connection with specific alternative embodiments, and the specific implementations of the present application are not to be considered limited to these descriptions. For those skilled in the art to which the present application pertains, several simple deductions or substitutions may be made without departing from the concept of the present application, and all should be considered as belonging to the protection scope of the present application.
Claims (9)
1. A gate driving circuit of a display panel provided with a plurality of scanning lines, the gate driving circuit comprising:
the multi-stage grid electrode driving sub-circuits are connected with the scanning lines in a one-to-one corresponding mode;
the multi-stage buffers are respectively arranged in one-to-one correspondence with the grid driving sub-circuits, one end of each multi-stage buffer is connected to the output end of the corresponding grid driving sub-circuit, and the other end of each multi-stage buffer is connected to the corresponding scanning line; and
a plurality of protection circuits provided in one-to-one correspondence with the scanning lines;
the protection circuit includes:
the error amplification unit is used for detecting and amplifying the voltage difference value between the input end and the output end of the buffer to obtain error amplification difference voltage and outputting the error amplification difference voltage;
the input end of the comparison unit is connected with the output end of the error amplification unit, and the comparison unit receives the error amplification difference voltage and outputs a comparison result signal according to the error amplification difference voltage; and
the input end of the control module is connected with the output end of the comparison unit, and the control module receives the comparison result signal and controls the buffer to be opened or disconnected from the scanning line according to the comparison result signal;
the error amplification unit includes:
the positive phase input end of the first error amplifier is connected with the input end of the buffer, the negative phase input end of the first error amplifier is connected with the output end of the buffer, and the voltage difference value between the input end and the output end of the buffer is calculated and amplified to obtain a first error amplification difference voltage which is output; and
the positive phase input end of the second error amplifier is connected with the output end of the buffer, the negative phase input end of the second error amplifier is connected with the input end of the buffer, and the voltage difference value between the output end and the input end of the buffer is calculated and amplified to obtain a second error amplification difference voltage which is output;
the comparison unit includes:
a positive phase input end of the first comparator is connected to the output end of the first error amplifier so as to receive the first error amplified difference voltage, and an output end of the first comparator is connected to the control module;
a positive phase input end of the second comparator is connected to the output end of the second error amplifier to receive the second error amplified difference voltage, and an output end of the second comparator is connected to the control module;
the inverting input ends of the first comparator and the second comparator are connected to a preset voltage; the first comparator outputs a first comparison result signal to the control module according to a comparison result of the first error amplification difference voltage and a preset voltage, and the second comparator outputs a second comparison result signal to the control module according to a comparison result of the second error amplification difference voltage and the preset voltage; and the control module outputs a control signal according to the comparison result signal to control the buffer to be opened or disconnected with the scanning line.
2. The gate driving circuit of the display panel according to claim 1, wherein the preset voltage satisfies the following formula:
VGL＜ADJ＜VGH；
the voltage regulator comprises a gate driving circuit, an ADJ, a VGH, and a VGL, wherein the ADJ is a preset voltage, the VGH is a high level voltage output by the gate driving circuit, and the VGL is a low level voltage output by the gate driving circuit.
3. The gate driving circuit of claim 2, wherein the predetermined voltage satisfies the following condition
The formula:
ADJ＝(VGH+VGL)/2。
4. the gate driving circuit of the display panel of claim 1, wherein the control module comprises:
the input end of the OR gate device is respectively connected with the output ends of the first comparator and the second comparator;
the control end of the control unit is connected with the output end of the OR gate device, the input end of the control unit is connected with the output end of the buffer, the output end of the control unit is connected with the scanning line, and the control unit is a low-level conducting switch;
when one of the first comparison result signal and the second comparison result signal is a high level signal, the or gate device outputs a high level control signal to the control unit to control disconnection of the buffer from the scan line; and when the first comparison result signal and the second comparison result signal are both low-level signals, the OR gate device outputs a low-level control signal to the control unit to control the buffer to be opened to be connected with the scanning line.
5. The gate driving circuit of the display panel according to claim 1, wherein the control module comprises a first switch, a second switch and a control unit, the first switch and the second switch are high-level conducting switches, and the control unit is a low-level conducting switch;
the grid electrode of the first switch is connected to the output end of the first comparator, the source end of the first switch is connected with a high-level signal, and the drain end of the first switch is connected with the control unit;
the grid electrode of the second switch is connected with the output end of the second comparator, the source end of the second switch is connected with a high-level signal, and the drain end of the second switch is connected with the control unit.
6. A gate drive circuit of a display panel according to claim 4 or 5, wherein the control unit comprises a transfer gate.
7. The gate driving circuit of the display panel according to claim 1, wherein the buffer includes 2n stages of inverters, where n is a natural number equal to or greater than 1.
8. A gate driving circuit of a display panel provided with a plurality of scanning lines, the gate driving circuit comprising:
the multi-stage grid electrode driving sub-circuits are connected with the scanning lines in a one-to-one corresponding mode;
the multi-stage buffers are respectively arranged in one-to-one correspondence with the grid driving sub-circuits, one end of each multi-stage buffer is connected to the output end of the corresponding grid driving sub-circuit, and the other end of each multi-stage buffer is connected to the corresponding scanning line; and
a plurality of protection circuits provided in one-to-one correspondence with the scanning lines;
the protection circuit includes:
the positive phase input end of the first error amplifier is connected with the input end of the buffer, the negative phase input end of the first error amplifier is connected with the output end of the buffer, and the voltage difference value between the input end and the output end of the buffer is calculated and amplified to output a first error amplification difference voltage;
the positive phase input end of the second error amplifier is connected with the output end of the buffer, the negative phase input end of the second error amplifier is connected with the input end of the buffer, and the voltage difference value between the output end and the input end of the buffer is calculated and amplified to output a second error amplification difference voltage;
a positive phase input end of the first comparator is connected to the output end of the first error amplifier so as to receive the first error amplified difference voltage, a negative phase input end of the first comparator is connected to a preset voltage, and an output end of the first comparator is connected to the control module;
a positive phase input end of the second comparator is connected to the output end of the second error amplifier to receive the second error amplified difference voltage, a negative phase input end of the second comparator is connected to the preset voltage, and an output end of the second comparator is connected to the control module;
the control module comprises an OR gate device and a transmission gate:
an input end of the OR gate device is respectively connected with output ends of the first comparator and the second comparator, and outputs a control signal according to the received first comparison result signal and the second comparison result signal; and
the transmission gate receives the control signal and controls to open or disconnect the connection between the buffer and the scanning line;
when the voltage of the input end of the buffer is the same as that of the output end of the buffer, and both the first error amplification difference voltage and the second error amplification difference voltage are smaller than the preset voltage, both the first comparison result signal and the second comparison result signal output by the first comparator and the second comparator are at a low level, the or gate device outputs the control signal at the low level, the transmission gate is opened after receiving the control signal at the low level, and the buffer is connected with the scanning line;
when the voltage of the input end of the buffer is different from the voltage of the output end of the buffer, the first error amplification difference voltage and the second error amplification difference voltage are both smaller than the preset voltage, the first comparison result signal and the second comparison result signal output by the first comparator and the second comparator are both at a low level, the OR gate device outputs a control signal at a low level, the transmission gate receives the control signal at a high level and then is closed, and the buffer is disconnected with the scanning line.
9. A display device comprising the gate driver circuit of the display panel according to any one of claims 1 to 8, and a display panel.
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