CN110418230B - Earphone shutdown circuit - Google Patents
Earphone shutdown circuit Download PDFInfo
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- CN110418230B CN110418230B CN201810404814.XA CN201810404814A CN110418230B CN 110418230 B CN110418230 B CN 110418230B CN 201810404814 A CN201810404814 A CN 201810404814A CN 110418230 B CN110418230 B CN 110418230B
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- 230000005669 field effect Effects 0.000 claims abstract description 106
- 239000003990 capacitor Substances 0.000 claims abstract description 46
- 230000006872 improvement Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 5
- 229910052744 lithium Inorganic materials 0.000 description 5
- 230000009471 action Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R1/00—Details of transducers, loudspeakers or microphones
- H04R1/10—Earpieces; Attachments therefor ; Earphones; Monophonic headphones
- H04R1/1041—Mechanical or electronic switches, or control elements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R2201/00—Details of transducers, loudspeakers or microphones covered by H04R1/00 but not provided for in any of its subgroups
- H04R2201/10—Details of earpieces, attachments therefor, earphones or monophonic headphones covered by H04R1/10 but not provided for in any of its subgroups
Abstract
The invention discloses an earphone shutdown circuit, which relates to the field of earphones, and comprises a main chip U1, a triode Q1, a field effect tube Q2, a field effect tube Q3, a switch key SW1, a microphone mute key SW2, a battery BAT, a diode D1 and a diode D2; the circuit also comprises a logic NOT chip U2 for turning the input high level to the low level or turning the input low level to the high level, a resistor R6 and a capacitor C1 for charging the circuit and storing electric energy, a resistor R7 for providing a circuit for releasing the electric energy of the circuit and a field effect transistor Q4. The technical scheme provided by the invention can realize normal open and shut down or subsequent other functional operations by touching the switch after the whole circuit is forcibly disconnected when the whole circuit is down.
Description
Technical Field
The invention relates to the field of earphones, in particular to an earphone shutdown circuit.
Background
At present, the wireless earphone is mainly powered by a lithium battery with the specification of 3.7V and realized by a single-chip scheme, and functions of on-off, microphone silence and the like are realized by a tact switch.
The touch switch is pressed down normally, so that when the wireless earphone completes the starting action, the wireless earphone obtains a reset signal and initializes the executable program, and the interaction between software and hardware can be realized; at this time, the user can perform related operations on the wireless earphone function through the touch switch, and when the touch switch is pressed again, the shutdown action of the wireless earphone can be completed. However, sometimes, problems occur in the hardware or software level inside the wireless earphone, so that the hardware and the software cannot interact with each other, and the whole wireless earphone system cannot respond, that is, the phenomenon that the wireless earphone is down occurs.
When the wireless earphone is down, the user cannot realize functions such as on-off and microphone silence by touching the switch.
For the problem, one solution is to keep the wireless earphone in a down state until the electric quantity of the built-in lithium battery is completely consumed and then the wireless earphone is recharged, and the method seriously affects the user experience. Another solution is to restart the wireless earphone by powering up the wireless earphone after power-off, and when the wireless earphone is down, the lithium battery is required to be disconnected from the wireless earphone casing and then connected to the circuit, so that the method is not practical.
Therefore, the inventor solves the above technical problem by providing a new shutdown circuit to solve the downtime problem by forcibly shutting down the wireless earphone, thereby improving the use experience of the user on the wireless earphone.
Disclosure of Invention
The invention aims to solve the technical problems in the prior art, provides an earphone shutdown circuit, and solves the problem that after the existing wireless earphone is down, a user cannot forcedly shutdown the wireless earphone by touching a switch lightly, so that the down problem is solved.
In order to solve the problems, the invention adopts the following technical scheme:
the invention provides an earphone shutdown circuit, which comprises a main chip U1, a triode Q1, a field effect tube Q2, a field effect tube Q3, a switch key SW1, a microphone mute key SW2, a battery BAT, a diode D1 and a diode D2;
the pin 1 of the main chip U1 is connected with the D electrode of the field effect tube Q2, the S electrode of the field effect tube Q2 is connected with the positive electrode of the battery BAT, the G electrode of the field effect tube Q2 is connected with the D electrode of the field effect tube Q3, and the negative electrode of the battery BAT is grounded after being connected with the S electrode of the field effect tube Q3; the pin 2 of the main chip U1 is connected with the C electrode of the triode Q1, and the E electrode of the triode Q1 is connected between the negative electrode of the battery BAT and the S electrode of the field effect transistor Q3; pin 3 of the main chip U1 is connected with pin 1 of the diode D2, pin 2 of the diode D2 is connected with the G pole of the field effect transistor Q3 after being connected together with pin 2 of the diode D1, pin 1 of the diode D1, the B pole of the triode Q1 and one end of the switch SW1 are connected together, and the other end of the switch SW1 is connected between the S pole of the field effect transistor Q2 and the positive pole of the battery BAT; the pin 4 of the main chip U1 and the pin 5 of the main chip U1 are connected together and then connected with one end of the microphone mute key SW2, and the other end of the microphone mute key SW2 is grounded;
the circuit also comprises a logic NOT chip U2 for turning the input high level to low level or turning the input low level to high level, a resistor R6 and a capacitor C1 for charging the circuit and storing electric energy, a resistor R7 for providing a circuit for releasing electric energy of the circuit and a field effect transistor Q4;
the pin 1 of the logic NOT gate chip U2 is connected with the pin 4 of the main chip U1, the pin 1 of the logic NOT gate chip U2 is connected with one end of a resistor R7, the other end of the resistor R7 is connected with the G pole of a field effect transistor Q4, and the S pole of the field effect transistor Q4 is grounded after being connected with the pin 2 of the logic NOT gate chip U2;
the pin 4 of the logic NOT chip U2 is connected with one end of a resistor R6, the other end of the resistor R6 is connected with one end of a capacitor C1, and the other end of the capacitor C1 is connected between the S pole of the field effect transistor Q4 and the pin 2 of the logic NOT chip U2;
the pin 3 of the logic NOT gate chip U2 and the D electrode of the field effect transistor Q4 are both connected between the resistor R6 and the capacitor C1, the pin 5 of the logic NOT gate chip U2 is connected with the pin 5 of the main chip U1, and the pin 6 of the logic NOT gate chip U2 is connected with the G electrode of the field effect transistor Q3;
after downtime occurs, a microphone mute key SW2 is pressed for a long time, a circuit is charged through a resistor R6 and a capacitor C1, so that the voltage at two ends of the capacitor C1 rises, the two ends of the capacitor C1 are at a high level, after level inversion is performed through a logic NOT chip U2, the level of a field effect tube Q2 and the level of a field effect tube Q3 are at a low level, the field effect tube Q2 and the field effect tube Q3 are in a cut-off state, and a battery BAT is disconnected from a main chip U1;
when the microphone mute key SW2 is released, the pin 1 of the logic NOT chip U2 is at a high level and the fet Q4 is in a conducting state through the resistor R7, and at this time, the electric energy stored in the capacitor C1 is released through the D pole and the S pole of the fet Q4.
As a further improvement of the invention, the pin 1 and the pin 4 of the logic NOT chip U2 are a group of corresponding input and output ports, and the pin 3 and the pin 6 of the logic NOT chip U2 are another group of corresponding input and output ports;
when the pin 1 of the logic NOT chip U2 inputs a high level, the pin 4 of the logic NOT chip U2 outputs a low level; or, when the pin 1 of the logic not gate chip U2 inputs a low level, the pin 4 of the logic not gate chip U2 outputs a high level;
when pin 3 of the logic not gate chip U2 inputs a high level, pin 6 of the logic not gate chip U2 outputs a low level; alternatively, when pin 3 of the logic not gate chip U2 inputs a low level, pin 6 of the logic not gate chip U2 outputs a high level.
As a further improvement of the invention, the earphone shutdown circuit further comprises a resistor R1 for providing bias voltage for the field effect transistor Q2, and two ends of the resistor R1 are respectively connected with the G pole and the S pole of the field effect transistor Q2.
As a further improvement of the present invention, the earphone shutdown circuit further includes a resistor R2 and a resistor R3 for providing a bias voltage to the fet Q3, where after the resistor R2 and the resistor R3 are connected in series, one end of the resistor R2 is connected to the pin 2 of the diode D2 or the pin 2 of the diode D1, the other end of the resistor R2 is connected to the S pole of the fet Q3, and a G pole of the fet Q3 and the pin 6 of the logic non-gate chip U2 are connected between the resistor R2 and the resistor R3, respectively.
As a further improvement of the present invention, the earphone shutdown circuit includes a resistor R4 for providing a bias voltage to the B pole of the triode Q1, one end of the resistor R4 is connected to the B pole of the triode Q1, and the other end of the resistor R4 is connected between the on-off key SW1 and the pin 1 of the diode D1.
As a further improvement of the present invention, the earphone shutdown circuit includes a resistor R5 for providing a pull-up bias voltage to the pin 4 of the main chip U1, two ends of the resistor R5 are respectively connected to the microphone mute key SW2 and the pin 5 of the main chip U1, and the resistor R5 and the microphone mute key SW2 are respectively connected to the pin 4 of the main chip U1 and the pin 1 of the logic non-gate chip U2.
As a further improvement of the invention, the resistor R6 and the capacitor C1 form a charging network, and the values of the resistor R6 and the capacitor C1 determine the charging time of the circuit, the resistor R6 is used for limiting the charging current of the circuit, and the capacitor C1 is used for storing electric energy.
As a further improvement of the invention, the triode Q1 is an NPN triode, the field effect transistor Q2 is a P-channel field effect transistor, and the field effect transistor Q3 and the field effect transistor Q4 are both N-channel field effect transistors.
Compared with the prior art, the invention has the beneficial effects that:
in the embodiment of the invention, the function of level inversion is realized by arranging the logic NOT chip U2, the resistor R6 and the capacitor C1 for charging the circuit and storing electric energy are arranged, the resistor R7 and the field effect transistor Q4 for providing a circuit for releasing electric energy are matched with the function control of the main chip U1, so that when the whole circuit is down, the circuit can be restarted by pressing the microphone mute key SW2 for a long time, and the normal switching or subsequent other functional operation can be realized by touching the switch key SW 1. The technical scheme provided by the invention can realize normal open and shut down or subsequent other functional operations by touching the switch after the whole circuit is forcibly disconnected when the whole circuit is down.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic block diagram of a headset shutdown circuit according to an embodiment of the invention.
Detailed Description
In order to enable those skilled in the art to better understand the present invention, the following description will make clear and complete descriptions of the technical solutions according to the embodiments of the present invention with reference to the accompanying drawings. It is apparent that the described embodiments are only some embodiments of the invention, but not all embodiments, and that the preferred embodiments of the invention are shown in the drawings. This invention may be embodied in many different forms and is not limited to the embodiments described herein, but rather is provided to provide a more thorough understanding of the present disclosure. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "having" and any variations thereof in the description and claims of the invention and in the foregoing drawings is intended to cover non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
Referring to fig. 1, a schematic block diagram of an earphone shutdown circuit according to an embodiment of the invention is shown, where the earphone shutdown circuit includes a main chip U1, a triode Q1, a field effect transistor Q2, a field effect transistor Q3, a switch SW1, a microphone mute key SW2, a battery BAT, a diode D1 and a diode D2. Specifically, pin 1 of main chip U1 is connected to the D pole of field effect transistor Q2, the S pole of field effect transistor Q2 is connected to the positive pole of battery BAT, the G pole of field effect transistor Q2 is connected to the D pole of field effect transistor Q3, and the negative pole of battery BAT is grounded after being connected to the S pole of field effect transistor Q3; the pin 2 of the main chip U1 is connected with the C electrode of the triode Q1, and the E electrode of the triode Q1 is connected between the negative electrode of the battery BAT and the S electrode of the field effect transistor Q3; pin 3 of the main chip U1 is connected with pin 1 of the diode D2, pin 2 of the diode D2 is connected with the G pole of the field effect transistor Q3 after being connected together with pin 2 of the diode D1, pin 1 of the diode D1, the B pole of the triode Q1 and one end of the switch SW1 are connected together, and the other end of the switch SW1 is connected between the S pole of the field effect transistor Q2 and the positive pole of the battery BAT; the pin 4 of the main chip U1 and the pin 5 of the main chip U1 are connected together and then connected with one end of the microphone mute key SW2, and the other end of the microphone mute key SW2 is grounded.
In the embodiment of the invention, a main control unit, a power management unit, a microphone unit, an input/output unit and the like are integrated in the main chip U1; the triode Q1 is an NPN triode and is mainly used for controlling the current passing through the triode Q1, the field effect tube Q2 is a P-channel field effect tube, the field effect tube Q3 is an N-channel field effect tube and is used for switching on a circuit or switching off the circuit, specifically, when the field effect tube Q2 is switched on or the field effect tube Q3 is switched on, the whole earphone shutdown circuit is switched on, and when the field effect tube Q2 is switched off or the field effect tube Q3 is switched off, the whole earphone shutdown circuit is switched off; the on/off key SW1 is used for turning on/off the entire earphone off circuit, and the microphone mute key SW2 is used for turning on/off the earphone microphone. In addition, battery BAT is a lithium battery, and is used to transmit electric energy from its positive electrode into main chip U1 through field effect transistor Q2. In this embodiment, when the level of the input fet Q3 is turned from low to high, the high level is prevented from flowing through the diode D1, so that the transistor Q1 is turned on; when the on-off key SW1 is pressed, the diode D2 may prevent the power of the lithium battery BAT from flowing through the diode D1 from the positive electrode thereof, thereby being transferred into the main chip U1.
Of course, the earphone shutdown circuit further includes a logic not gate chip U2 for inverting the input high level to the low level or inverting the input low level to the high level, a resistor R6 and a capacitor C1 for charging the circuit and storing electric energy, a resistor R7 for providing a circuit for discharging electric energy, and a field effect transistor Q4. Specifically, pin 1 of the logic non-gate chip U2 is connected with pin 4 of the main chip U1, pin 1 of the logic non-gate chip U2 is connected with one end of a resistor R7, the other end of the resistor R7 is connected with the G pole of a field effect transistor Q4, and the S pole of the field effect transistor Q4 is grounded after being connected with pin 2 of the logic non-gate chip U2; the pin 4 of the logic NOT chip U2 is connected with one end of a resistor R6, the other end of the resistor R6 is connected with one end of a capacitor C1, and the other end of the capacitor C1 is connected between the S pole of the field effect transistor Q4 and the pin 2 of the logic NOT chip U2; the pin 3 of the logic NOT chip U2 and the D electrode of the field effect transistor Q4 are both connected between the resistor R6 and the capacitor C1, the pin 5 of the logic NOT chip U2 is connected with the pin 5 of the main chip U1, and the pin 6 of the logic NOT chip U2 is connected with the G electrode of the field effect transistor Q3. Of course, the field effect transistors Q4 are all N-channel field effect transistors, and are mainly used for switching on or off a circuit.
In the embodiment of the invention, after downtime occurs, a microphone mute key SW2 is pressed for a long time, a circuit is charged through a resistor R6 and a capacitor C1, so that the voltage at two ends of the capacitor C1 rises, the two ends of the capacitor C1 are at a high level, after level inversion is performed through a logic NOT chip U2, the level of a field effect transistor Q2 and the level of a field effect transistor Q3 are at a low level, the field effect transistor Q2 and the field effect transistor Q3 are in a cut-off state, a battery BAT is disconnected from a main chip U1, the effect of forced shutdown and disconnection of the whole circuit is achieved, and normal switching or subsequent other functional operation can be realized by touching the switch key SW 1. When the microphone mute key SW2 is released, the pin 1 of the logic NOT chip U2 is at a high level and the fet Q4 is in a conducting state through the resistor R7, and at this time, the electric energy stored in the capacitor C1 is released through the D pole and the S pole of the fet Q4.
In one embodiment of the present invention, pin 1 and pin 4 of the logic not gate chip U2 are a set of corresponding input and output ports, and pin 3 and pin 6 of the logic not gate chip U2 are another set of corresponding input and output ports; when the pin 1 of the logic NOT chip U2 inputs a high level, the pin 4 of the logic NOT chip U2 outputs a low level; or, when the pin 1 of the logic not gate chip U2 inputs a low level, the pin 4 of the logic not gate chip U2 outputs a high level; when pin 3 of the logic not gate chip U2 inputs a high level, pin 6 of the logic not gate chip U2 outputs a low level; alternatively, when pin 3 of the logic not gate chip U2 inputs a low level, pin 6 of the logic not gate chip U2 outputs a high level. Of course, in other embodiments of the present invention, the logic not gate chip U2 may include, but is not limited to, setting three or four sets of corresponding logic not operation ports, and only setting multiple sets of corresponding ports on the logic not gate chip U2 is required.
Specifically, the resistor R6 and the capacitor C1 form a charging network of the circuit, and the values of the resistor R6 and the capacitor C1 determine the charging time of the circuit, the resistor R6 is used for limiting the charging current of the circuit, and the capacitor C1 is used for storing electric energy. Specifically, the charging time is the product of the values of the resistor R6 and the capacitor C1, and the value of the resistor R6 and the capacitor C1 is larger in the scheme, so that the required charging time is longer, and in the embodiment of the invention, the required charging time is set to be between 8s and 10 s.
After normal start-up, the direct-current voltage output by the pin 5 of the main chip U1 is transmitted to the logic NOT chip U2, at this time, the pin 4 of the main chip U1 is output to be at a high level, the pin 4 of the main chip U1 is connected with the pin 1 of the logic NOT chip U2, and the pin 4 of the logic NOT chip U2 is output to be at a low level according to the level inversion rule of the logic NOT chip U2; while the output of the pin 4 of the logic not gate chip U2 is low, and the output is transmitted to the pin 3 of the logic not gate chip U2 through the resistor R6 and the capacitor C1, the output of the pin 6 of the logic not gate chip U2 is high, and the output is transmitted to the G pole of the fet Q3, so that the fet Q3 and the fet Q2 are turned on, and at this time, the battery BAT can normally supply power to the main chip U1. Therefore, when the microphone mute button SW2 is pressed for 1 second or 2 seconds, that is, when the microphone mute button SW2 is pressed for a short time, the output of the pin 1 of the logic non-gate chip U2 is at a low level, and the output of the pin 4 of the corresponding logic non-gate chip U2 is at a high level and charges the capacitor C1 through the resistor R6, and because the resistor R6 and the capacitor C1 have larger values, the required charging time is long, the two ends of the capacitor C1 are still kept at a low level, so that the output of the pin 3 of the logic non-gate chip U2 is also at a low level, and the output of the pin 6 of the corresponding logic non-gate chip U2 is still at a high level and is led into the field effect transistor Q2 and the field effect transistor Q3, so that the battery BAT is connected with the main chip U1 and provides electric energy to the main chip U1, and the normal operation of the whole circuit is not affected.
After downtime, the pin 5 of the main chip U1 still outputs a dc voltage to the logic non-gate chip U2, so that the level output by the pin 4 of the main chip U1 remains high. At this time, when the microphone mute key SW2 is pressed for a long time, the resistor R6 and the capacitor C1 have enough charging time, the voltage at two ends of the capacitor C1 will rise, that is, the pin 3 of the logic non-gate chip U2 outputs a high level, the pin 6 of the corresponding logic non-gate chip U2 outputs a low level, and the low level is transmitted to the G pole of the field effect transistor Q3, so as to force the level of the G pole of the field effect transistor Q3 to be pulled down, so that the G pole of the field effect transistor Q3 is turned off, and meanwhile, the field effect transistor Q2 is also turned off, so that the electric energy transmission between the positive pole of the battery BAT and the main chip U2 is disconnected, thereby achieving the effect of forced shutdown disconnection, and being able to realize normal switching or subsequent other functional operations by touching the switch key SW 1.
When releasing the power, when releasing or releasing the microphone mute key SW2, the pin 1 of the logic NOT chip U2 outputs a high level, and the high level is turned over by the logic NOT chip U2 on one hand and the pin 4 of the logic NOT chip U2 outputs a low level; on the other hand, the field effect transistor Q4 is in a conducting state through the resistor R7, and at this time, because the resistance value of the resistor R6 is larger, the electric energy of the capacitor C1 can only be discharged through the D pole and the S pole of the field effect transistor Q4, and the preparation is made for the next forced shutdown. When the fet Q4 is turned on, the internal resistance between the D pole and the S pole of the fet Q4 is very small, so that the electric energy stored in the capacitor C1 can be released through the D pole and the S pole of the fet Q4.
In one or more possible implementations of the present invention, the earphone shutdown circuit further includes a resistor R1 for providing a bias voltage to the fet Q2, and two ends of the resistor R1 are connected to the G pole and the S pole of the fet Q2, respectively. The earphone shutdown circuit further comprises a resistor R2 and a resistor R3 for providing bias voltage for the field effect transistor Q3, one end of the resistor R2 and one end of the resistor R3 are connected in series and then connected to the pin 2 of the diode D2 or the pin 2 of the diode D1, the other end of the resistor R2 and the other end of the resistor R3 are connected with the S pole of the field effect transistor Q3, and the G pole of the field effect transistor Q3 and the pin 6 of the logic NOT gate chip U2 are respectively connected between the resistor R2 and the resistor R3. The earphone shutdown circuit comprises a resistor R4 for providing bias voltage for the B pole of the triode Q1, one end of the resistor R4 is connected with the B pole of the triode Q1, and the other end of the resistor R4 is connected between the switch key SW1 and the pin 1 of the diode D1. The earphone shutdown circuit comprises a resistor R5 for providing a pull-up bias voltage for the pin 4 of the main chip U1, wherein two ends of the resistor R5 are respectively connected to the microphone mute key SW2 and the pin 5 of the main chip U1, and the pin 4 of the main chip U1 and the pin 1 of the logic NOT chip U2 are respectively connected between the resistor R5 and the microphone mute key SW 2.
In the embodiment of the present invention, the values of the resistor R1, the resistor R2, the resistor R3, the resistor R4, and the resistor R5 are not limited. In other embodiments of the present invention, the resistances may be not only 5, but also 6, 7, etc., and the present invention is not limited thereto.
In the embodiment of the invention, the function of level inversion is realized by arranging the logic NOT chip U2, the resistor R6 and the capacitor C1 for charging the circuit and storing electric energy are arranged, the resistor R7 and the field effect transistor Q4 for providing a circuit for releasing electric energy are matched with the function control of the main chip U1, so that when the whole circuit is down, the circuit can be restarted by pressing the microphone mute key SW2 for a long time, and the normal switching or subsequent other functional operation can be realized by touching the switch key SW 1. The technical scheme provided by the invention can realize normal open and shut down or subsequent other functional operations by touching the switch after the whole circuit is forcibly disconnected when the whole circuit is down.
In this embodiment, it will be understood by those skilled in the art that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that elements are not expressly listed but may include other elements not; the terms front, rear, upper, lower, etc. are defined by the positions of the structures in the drawings and the structures relative to each other, only for the sake of clarity and convenience in expressing the technical solution. It should be understood that the use of such orientation terms should not limit the scope of the protection sought herein.
The technical features of the above-described embodiments may be arbitrarily combined, and for brevity of description, all of the possible combinations of the technical features of the above-described embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be regarded as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (6)
1. An earphone shutdown circuit comprises a main chip U1, a triode Q1, a field effect tube Q2, a field effect tube Q3, a switch key SW1, a microphone mute key SW2, a battery BAT, a diode D1 and a diode D2;
the pin 1 of the main chip U1 is connected with the D electrode of the field effect tube Q2, the S electrode of the field effect tube Q2 is connected with the positive electrode of the battery BAT, the G electrode of the field effect tube Q2 is connected with the D electrode of the field effect tube Q3, and the negative electrode of the battery BAT is grounded after being connected with the S electrode of the field effect tube Q3; the pin 2 of the main chip U1 is connected with the C electrode of the triode Q1, and the E electrode of the triode Q1 is connected between the negative electrode of the battery BAT and the S electrode of the field effect transistor Q3; pin 3 of the main chip U1 is connected with pin 1 of the diode D2, pin 2 of the diode D2 is connected with the G pole of the field effect transistor Q3 after being connected together with pin 2 of the diode D1, pin 1 of the diode D1, the B pole of the triode Q1 and one end of the switch SW1 are connected together, and the other end of the switch SW1 is connected between the S pole of the field effect transistor Q2 and the positive pole of the battery BAT; the pin 4 of the main chip U1 and the pin 5 of the main chip U1 are connected together and then connected with one end of the microphone mute key SW2, and the other end of the microphone mute key SW2 is grounded;
the circuit is characterized by further comprising a logic NOT chip U2 for turning an input high level to a low level or turning an input low level to a high level, a resistor R6 and a capacitor C1 for charging a circuit and storing electric energy, a resistor R7 for providing a circuit for releasing electric energy of the circuit and a field effect transistor Q4;
the pin 1 of the logic NOT gate chip U2 is connected with the pin 4 of the main chip U1, the pin 1 of the logic NOT gate chip U2 is connected with one end of a resistor R7, the other end of the resistor R7 is connected with the G pole of a field effect transistor Q4, and the S pole of the field effect transistor Q4 is grounded after being connected with the pin 2 of the logic NOT gate chip U2;
the pin 4 of the logic NOT chip U2 is connected with one end of a resistor R6, the other end of the resistor R6 is connected with one end of a capacitor C1, and the other end of the capacitor C1 is connected between the S pole of the field effect transistor Q4 and the pin 2 of the logic NOT chip U2;
the pin 3 of the logic NOT gate chip U2 and the D electrode of the field effect transistor Q4 are both connected between the resistor R6 and the capacitor C1, the pin 5 of the logic NOT gate chip U2 is connected with the pin 5 of the main chip U1, and the pin 6 of the logic NOT gate chip U2 is connected with the G electrode of the field effect transistor Q3;
after downtime occurs, a microphone mute key SW2 is pressed for a long time, a circuit is charged through a resistor R6 and a capacitor C1, so that the voltage at two ends of the capacitor C1 rises, the two ends of the capacitor C1 are at a high level, after level inversion is performed through a logic NOT chip U2, the level of a field effect tube Q2 and the level of a field effect tube Q3 are at a low level, the field effect tube Q2 and the field effect tube Q3 are in a cut-off state, and a battery BAT is disconnected from a main chip U1;
when the electric energy is released, the microphone mute key SW2 is released, the pin 1 of the logic NOT gate chip U2 is in a high level, the field effect transistor Q4 is in a conducting state through the resistor R7, and at the moment, the electric energy stored in the capacitor C1 is released through the D pole and the S pole of the field effect transistor Q4;
the pin 1 and the pin 4 of the logic NOT gate chip U2 are a group of corresponding input and output ports, and the pin 3 and the pin 6 of the logic NOT gate chip U2 are another group of corresponding input and output ports;
when the pin 1 of the logic NOT chip U2 inputs a high level, the pin 4 of the logic NOT chip U2 outputs a low level; or, when the pin 1 of the logic not gate chip U2 inputs a low level, the pin 4 of the logic not gate chip U2 outputs a high level;
when pin 3 of the logic not gate chip U2 inputs a high level, pin 6 of the logic not gate chip U2 outputs a low level; alternatively, when pin 3 of the logic not gate chip U2 inputs a low level, pin 6 of the logic not gate chip U2 outputs a high level;
the earphone shutdown circuit further comprises a resistor R1 for providing bias voltage for the field effect transistor Q2, and two ends of the resistor R1 are respectively connected with the G pole and the S pole of the field effect transistor Q2.
2. The earphone shutdown circuit of claim 1, wherein: the earphone shutdown circuit further comprises a resistor R2 and a resistor R3 for providing bias voltage for the field effect transistor Q3, one end of the resistor R2 and one end of the resistor R3 are connected in series and then connected to the pin 2 of the diode D2 or the pin 2 of the diode D1, the other end of the resistor R2 and the other end of the resistor R3 are connected with the S pole of the field effect transistor Q3, and the G pole of the field effect transistor Q3 and the pin 6 of the logic NOT gate chip U2 are respectively connected between the resistor R2 and the resistor R3.
3. The earphone shutdown circuit of claim 1, wherein: the earphone shutdown circuit comprises a resistor R4 for providing bias voltage for the B pole of the triode Q1, one end of the resistor R4 is connected with the B pole of the triode Q1, and the other end of the resistor R4 is connected between the switch key SW1 and the pin 1 of the diode D1.
4. The earphone shutdown circuit of claim 1, wherein: the earphone shutdown circuit comprises a resistor R5 for providing a pull-up bias voltage for the pin 4 of the main chip U1, wherein two ends of the resistor R5 are respectively connected to the microphone mute key SW2 and the pin 5 of the main chip U1, and the pin 4 of the main chip U1 and the pin 1 of the logic NOT chip U2 are respectively connected between the resistor R5 and the microphone mute key SW 2.
5. The earphone shutdown circuit of claim 1, wherein: the resistor R6 and the capacitor C1 form a charging network, the values of the resistor R6 and the capacitor C1 determine the charging time of the circuit, the resistor R6 is used for limiting the charging current of the circuit, and the capacitor C1 is used for storing electric energy.
6. The earphone shutdown circuit of claim 1, wherein: the triode Q1 is an NPN triode, the field effect transistor Q2 is a P channel field effect transistor, and the field effect transistor Q3 and the field effect transistor Q4 are N channel field effect transistors.
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| CN201810404814.XA CN110418230B (en) | 2018-04-28 | 2018-04-28 | Earphone shutdown circuit |
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| CN201810404814.XA CN110418230B (en) | 2018-04-28 | 2018-04-28 | Earphone shutdown circuit |
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| CN110418230B true CN110418230B (en) | 2024-03-29 |
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