CN110416228A - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN110416228A CN110416228A CN201910699956.8A CN201910699956A CN110416228A CN 110416228 A CN110416228 A CN 110416228A CN 201910699956 A CN201910699956 A CN 201910699956A CN 110416228 A CN110416228 A CN 110416228A
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- 239000010408 film Substances 0.000 claims abstract description 217
- 239000000463 material Substances 0.000 claims abstract description 38
- 230000007704 transition Effects 0.000 claims abstract description 20
- 239000002131 composite material Substances 0.000 claims abstract description 13
- 239000010409 thin film Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 51
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 51
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 47
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 47
- 238000000151 deposition Methods 0.000 claims description 30
- 230000004888 barrier function Effects 0.000 claims description 24
- 238000002161 passivation Methods 0.000 claims description 24
- 230000008021 deposition Effects 0.000 claims description 20
- 239000010703 silicon Substances 0.000 claims description 20
- 229910052710 silicon Inorganic materials 0.000 claims description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 229910003978 SiClx Inorganic materials 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims 2
- 230000007547 defect Effects 0.000 abstract description 10
- 238000010586 diagram Methods 0.000 description 14
- 239000013078 crystal Substances 0.000 description 13
- 238000009825 accumulation Methods 0.000 description 9
- 230000005611 electricity Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 240000002853 Nelumbo nucifera Species 0.000 description 1
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 1
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
The present invention provides a kind of display panel and display device, display panel includes the substrate and thin film transistor (TFT) being cascading, wherein, the thin film transistor (TFT) includes multiple first film layers and multiple second film layers being stacked, first film layer is homogenous material film layer, second film layer is the composite film that a variety of different material layers are laminated, first film layer includes the low temperature that is arranged between film layer adjacent thereto into nucleon film layer, transition zone is equipped in second film layer between two kinds of adjacent material layers, the composite layer that the transition zone is made of the atom in two kinds of adjacent material layers.The present invention can effectively reduce the grain boundary defects between film layer different in display panel, to reduce the probability of electrostatic generation, improve the service life of display panel.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of display panel and display devices.
Background technique
Static discharge be cause Organic Light Emitting Diode (Organic Light-Emitting Diode, OLED) device by
To the principal element of destruction, thin film transistor (TFT) (Thin Film Transistor, TFT) in organic light emitting diode device by
A variety of different film layers are stacked, and due to the difference of material between adjacent film layer, can be deposited in the adjacent interface of the two
In a large amount of grain boundary defects, so that a large amount of positive and negative charge and introduced contaminants ion are gathered in the adjacent interface of the two, so as to cause
The accumulation of charge, and then lead to electrostatic.
Summary of the invention
In order to overcome the drawbacks described above under the prior art, the purpose of the present invention is to provide a kind of display panel and display dresses
It sets, display panel of the invention can effectively reduce the grain boundary defects between different film layers, to reduce electrostatic generation
Probability improves the service life of display panel.
One embodiment of the invention provides a kind of display panel, including the substrate and thin film transistor (TFT) being cascading,
In, the thin film transistor (TFT) includes multiple first film layers and multiple second film layers being stacked, and first film layer is single
Film layer, second film layer are the composite film that a variety of different material layers are laminated, and first film layer includes setting
Low temperature between film layer adjacent thereto is set in second film layer between two kinds of adjacent material layers at nucleon film layer
There are transition zone, the composite layer that the transition zone is made of the atom in two kinds of adjacent material layers.
The first film layer of the present embodiment includes the low temperature that is arranged between film layer adjacent thereto into nucleon film layer, low temperature nucleation
The material of sub- film layer is identical as the material of the first film layer, since atom is weaker at the transfer ability of nucleon film surface in low temperature,
Therefore low temperature can effectively reduce the grain boundary defects between the first film layer and film layer adjacent thereto at nucleon film layer, reduce electricity
Lotus reduces the probability that electrostatic generates in the accumulation of interface；Further, the present embodiment two kinds of materials adjacent in the second film layer
Equipped with transition zone between the bed of material, the composite layer that transition zone is made of the atom in two kinds of adjacent material layers, so as to
To reduce the crystal lattice difference between two adjacent film layers, to reduce grain boundary defects, charge is reduced in the accumulation of interface, is reduced
The probability that electrostatic generates.Through the above scheme, the present embodiment can guarantee the normal display significant raising simultaneously of display panel
The service life of display panel.
Display panel as described above, optionally, first film layer includes membranous layer of silicon oxide or silicon nitride film layer, described
Membranous layer of silicon oxide includes barrier layer and gate insulating layer, and the silicon nitride film layer includes dielectric layer and passivation layer.
Display panel as described above, optionally, the barrier layer are included in the first barrier layer made of deposition at 200 DEG C
With at 370 DEG C deposit made of the second barrier layer, first barrier layer with a thickness of 30-50 nanometer, it is described second blocking
Layer with a thickness of 550-570 nanometers.
Display panel as described above, optionally, the gate insulating layer are included in the first grid made of deposition at 200 DEG C
Pole insulating layer and the second grid insulating layer made of deposition at 420 DEG C, the first grid insulating layer are received with a thickness of 30-50
Rice, the second grid insulating layer with a thickness of 90-110 nanometers.
Display panel as described above, optionally, the dielectric layer are included at 200 DEG C the first electricity made of deposition and are situated between
Matter layer and at 420 DEG C deposit made of the second dielectric layer, first dielectric layer with a thickness of 30-50 nanometers, it is described
Second dielectric layer with a thickness of 70-90 nanometers.
Display panel as described above, optionally, the passivation layer are included in the first passivation layer made of deposition at 100 DEG C
With at 270 DEG C deposit made of the second passivation layer, first passivation layer with a thickness of 30-50 nanometer, it is described second be passivated
Layer with a thickness of 220-240 nanometers.
Display panel as described above, optionally, second film layer include at least one membranous layer of silicon oxide and silicon nitride
Film layer, second film layer include the first inorganic film and the second inorganic film.
Display panel as described above, optionally, second inorganic film include the silicon nitride film layer stacked gradually, nitrogen
Membranous layer of silicon oxide and membranous layer of silicon oxide；Wherein, the silicon nitride film layer is included in the first silicon nitride film made of deposition at 200 DEG C
Layer and at 420 DEG C deposit made of the second silicon nitride film layer, first silicon nitride film layer with a thickness of 5-15 nanometers, it is described
Second silicon nitride film layer with a thickness of 30-40 nanometers；The depositing temperature of the silicon oxynitride film is 420 DEG C, the nitrogen oxidation
Silicon film with a thickness of 90-110 nanometers；The membranous layer of silicon oxide is included in the first membranous layer of silicon oxide made of deposition at 200 DEG C
With at 420 DEG C deposit made of the second membranous layer of silicon oxide, first membranous layer of silicon oxide with a thickness of 30-50 nanometers, it is described
Second membranous layer of silicon oxide with a thickness of 200-220 nanometers.
Display panel as described above, optionally, first inorganic film include the membranous layer of silicon oxide stacked gradually, nitrogen
Membranous layer of silicon oxide and silicon nitride film layer；Wherein, the membranous layer of silicon oxide is included in third silicon oxide film made of deposition at 200 DEG C
Layer and the 4th membranous layer of silicon oxide made of being deposited at 370 DEG C, the third membranous layer of silicon oxide with a thickness of 30-50 nanometers, institute
State the 4th membranous layer of silicon oxide with a thickness of 220-240 nanometers；The depositing temperature of the silicon oxynitride film is 370 DEG C, the nitrogen
Membranous layer of silicon oxide with a thickness of 90-110 nanometers；The silicon nitride film layer is included in third silicon nitride made of deposition at 200 DEG C
Film layer and at 370 DEG C deposit made of the 4th silicon nitride film layer, the third silicon nitride film layer with a thickness of 30-50 nanometers,
4th silicon nitride film layer with a thickness of 170-190 nanometers.
Another embodiment of the present invention provides a kind of display devices, including as above any display panel.
Display device provided in this embodiment, the first film layer of display panel include be arranged in film layer adjacent thereto it
Between low temperature at nucleon film layer, low temperature is identical as the material of the first film layer at the material of nucleon film layer, due to atom low temperature at
The transfer ability of nucleon film surface is weaker, therefore low temperature can effectively reduce the first film layer and adjacent thereto at nucleon film layer
Film layer between grain boundary defects, reduce charge interface accumulation, reduce electrostatic generate probability；Further, aobvious
Show and be equipped with transition zone between two kinds of material layers adjacent in the second film layer of panel, transition zone is in two kinds of adjacent material layers
The composite layer that atom is constituted is lacked so as to reduce the crystal lattice difference between two adjacent film layers with reducing crystal boundary
It falls into, reduces charge in the accumulation of interface, reduce the probability that electrostatic generates.The present embodiment can guarantee the normal aobvious of display device
Show while significantly improving the service life of display device.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is this hair
Bright some embodiments for those of ordinary skill in the art without creative efforts, can be with root
Other attached drawings are obtained according to these attached drawings.
Fig. 1 is the structure diagram for the display panel that one embodiment of the invention provides；
Fig. 2 is the structure diagram on the barrier layer that one embodiment of the invention provides；
Fig. 3 is the structure diagram for the gate insulating layer that one embodiment of the invention provides；
Fig. 4 is the structure diagram for the dielectric layer that one embodiment of the invention provides；
Fig. 5 is the structure diagram for the passivation layer that one embodiment of the invention provides；
Fig. 6 is the structure diagram for the second inorganic film that one embodiment of the invention provides；
Fig. 7 is the structure diagram for the first inorganic film that one embodiment of the invention provides.
Appended drawing reference:
100- substrate；
The first film layer of 200-；
The barrier layer 210-；
The first barrier layer 211-；
The second barrier layer 212-；
220- gate insulating layer；
221- first grid insulating layer；
222- second grid insulating layer；
230- dielectric layer；
The first dielectric layer of 231-；
The second dielectric layer of 232-；
240- passivation layer；
The first passivation layer of 241-；
The second passivation layer of 242-；
The second film layer of 300-；
The second inorganic film of 310-；
The first silicon nitride film layer of 311-；
The second silicon nitride film layer of 312-；
313- silicon oxynitride film；
The first membranous layer of silicon oxide of 314-；
The second membranous layer of silicon oxide of 315-；
The first inorganic film of 320-；
321- third membranous layer of silicon oxide；
The 4th membranous layer of silicon oxide of 322-；
323- silicon oxynitride film；
324- third silicon nitride film layer；
The 4th silicon nitride film layer of 325-.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.
Based on the embodiments of the present invention, those of ordinary skill in the art are obtained without making creative work
The every other embodiment obtained, shall fall within the protection scope of the present invention.In the absence of conflict, following embodiment and implementation
Feature in example can be combined with each other.
Embodiment one
Fig. 1 is the structure diagram for the display panel that one embodiment of the invention provides；Fig. 2 is what one embodiment of the invention provided
The structure diagram on barrier layer；Fig. 3 is the structure diagram for the gate insulating layer that one embodiment of the invention provides；Fig. 4 is the present invention one
The structure diagram for the dielectric layer that embodiment provides；Fig. 5 is the structure diagram for the passivation layer that one embodiment of the invention provides；Fig. 6
For the structure diagram for the second inorganic film that one embodiment of the invention provides；Fig. 7 is the first nothing that one embodiment of the invention provides
The structure diagram of machine film layer；Please refer to Fig. 1-Fig. 7.
The present embodiment provides a kind of display panels, including the substrate 100 being cascading and thin film transistor (TFT), wherein
Thin film transistor (TFT) includes multiple first film layers 200 and multiple second film layers 300 being stacked, and the first film layer 200 is single material
Expect film layer, the second film layer 300 is the composite film that is laminated of a variety of different material layers, the first film layer 200 include setting with
Low temperature between its adjacent film layer is equipped with transition zone between two kinds of adjacent material layers in the second film layer 300 at nucleon film layer,
The composite layer that transition zone is made of the atom in two kinds of adjacent material layers.
Specifically, first film layer 200 and the second film layer 300 of the present embodiment are the non-metallic layer in thin film transistor (TFT),
First film layer 200 can be membranous layer of silicon oxide or silicon nitride film layer, and the second film layer is by least one membranous layer of silicon oxide and at least one
A silicon nitride film layer is laminated.
First film layer 200 includes that low temperature between film layer adjacent thereto is arranged in into nucleon film layer, and low temperature is at nucleon film
The material of layer is identical as the material of the first film layer 200, which is at a lower temperature, to be sunk with faster speed at nucleon film layer
Film layer made of product, for low temperature at the thinner thickness of nucleon film layer, surface is conducive to subsequent material in shape structure is led with lower speed
Rate deposition, so as to improve the film quality of the first film layer 200.After the completion of low temperature is at nucleon film deposition, the first film layer 200 can be improved
Temperature, with other layer of structure in lower the first film layer of deposition rate 200.
Transition zone is equipped in second film layer 300 between two kinds of adjacent material layers, transition zone is two kinds of adjacent material layers
In the composite layer that is constituted of atom, transition zone deposits with higher rate, is located at transition zone so as to reduce
Crystal lattice difference between two kinds of different material layers of two sides.
In the present embodiment, the method that chemical vapor deposition can be used in above-mentioned first film layer 200 and the second film layer 300 is carried out
Manufacture.
Through the above scheme, first film layer 200 of the present embodiment includes the low temperature being arranged between film layer adjacent thereto
At nucleon film layer, low temperature is identical as the material of the first film layer 200 at the material of nucleon film layer, due to atom in low temperature at nucleon
The transfer ability of film surface is weaker, therefore low temperature can effectively reduce the first film layer 200 and adjacent thereto at nucleon film layer
Film layer between grain boundary defects, reduce charge interface accumulation, reduce electrostatic generate probability；Further, this reality
It applies example and is equipped with transition zone between two kinds of material layers adjacent in the second film layer 300, transition zone is in two kinds of adjacent material layers
The composite layer that is constituted of atom, so as to reduce the crystal lattice difference between two adjacent film layers, to reduce crystal boundary
Defect reduces charge in the accumulation of interface, reduces the probability that electrostatic generates.
Further, in this embodiment membranous layer of silicon oxide include barrier layer 210 and gate insulating layer 220, silicon nitride film
Layer includes dielectric layer 230 and passivation layer 240.
Specifically, as shown in Fig. 2, barrier layer 210 be included in deposited at 200 DEG C made of the first barrier layer 211 and 370
Second barrier layer 212 made of being deposited at DEG C, the first barrier layer 211 with a thickness of 30-50 nanometers, the thickness on the second barrier layer 212
Degree is 550-570 nanometers.Barrier layer can be effectively reduced by the first barrier layer 211 for depositing relatively thin at a lower temperature
Crystal lattice difference between 210 and adjacent film layers, and then reduce the probability that electrostatic generates.
As shown in figure 3, gate insulating layer 220 be included at 200 DEG C deposit made of first grid insulating layer 221 and
Second grid insulating layer 222 made of being deposited at 420 DEG C, first grid insulating layer 221 with a thickness of 30-50 nanometers, second gate
Pole insulating layer 222 with a thickness of 90-110 nanometers.It can by the first grid insulating layer 221 for depositing relatively thin at a lower temperature
The crystal lattice difference between gate insulating layer 220 and adjacent film layers is effectively reduced, and then reduces the probability that electrostatic generates.
As shown in figure 4, dielectric layer 230 be included in deposited at 200 DEG C made of the first dielectric layer 231 and at 420 DEG C
Second dielectric layer 232 made of lower deposition, the first dielectric layer 231 with a thickness of 30-50 nanometers, the second dielectric layer 232
With a thickness of 70-90 nanometers.Electric Jie can be effectively reduced by the first dielectric layer 231 for depositing relatively thin at a lower temperature
Crystal lattice difference between matter layer 230 and adjacent film layers, and then reduce the probability that electrostatic generates.
As shown in figure 5, passivation layer 240 is included in the first passivation layer 241 made of deposition at 100 DEG C and sinks at 270 DEG C
Second passivation layer 242 made of product, the first passivation layer 241 with a thickness of 30-50 nanometers, the second passivation layer 242 with a thickness of
220-240 nanometers.Electric passivation layer 240 can be effectively reduced by the first passivation layer 241 for depositing relatively thin at a lower temperature
Crystal lattice difference between adjacent film layers, and then reduce the probability that electrostatic generates.
Further, second film layer 300 of the present embodiment includes the second inorganic film 310 and the first inorganic film 320.
As shown in fig. 6, the second inorganic film 310 includes silicon nitride film layer, silicon oxynitride film 313 and the oxygen stacked gradually
SiClx film layer；Wherein, silicon nitride film layer is included in the first silicon nitride film layer 311 made of deposition at 200 DEG C and sinks at 420 DEG C
Second silicon nitride film layer 312 made of product, the first silicon nitride film layer 311 with a thickness of 5-15 nanometers, the second silicon nitride film layer 312
With a thickness of 30-40 nanometers；The depositing temperature of silicon oxynitride film 313 be 420 DEG C, silicon oxynitride film 313 with a thickness of 90-
110 nanometers；Membranous layer of silicon oxide is included in the first membranous layer of silicon oxide 314 made of deposition at 200 DEG C and deposits at 420 DEG C
The second membranous layer of silicon oxide 315, the first membranous layer of silicon oxide 314 with a thickness of 30-50 nanometers, the thickness of the second membranous layer of silicon oxide 315
Degree is 200-220 nanometers.
As shown in fig. 7, the first inorganic film 320 includes membranous layer of silicon oxide, silicon oxynitride film 323 and the nitrogen stacked gradually
SiClx film layer；Wherein, membranous layer of silicon oxide is included in third membranous layer of silicon oxide 321 made of deposition at 200 DEG C and sinks at 370 DEG C
4th membranous layer of silicon oxide 322 made of product, third membranous layer of silicon oxide 321 with a thickness of 30-50 nanometers, the 4th membranous layer of silicon oxide
322 with a thickness of 220-240 nanometers；The depositing temperature of silicon oxynitride film 323 is 370 DEG C, the thickness of silicon oxynitride film 323
It is 90-110 nanometers；Silicon nitride film layer is included in third silicon nitride film layer 324 made of deposition at 200 DEG C and sinks at 370 DEG C
4th silicon nitride film layer 325 made of product, third silicon nitride film layer 324 with a thickness of 30-50 nanometers, the 4th silicon nitride film layer
325 with a thickness of 170-190 nanometers.
In the second inorganic film 310 and the first inorganic film 320, nitridation can reduce by the way that silicon oxynitride film is arranged
Crystal lattice difference between silicon film and membranous layer of silicon oxide, meanwhile, low temperature is set in silicon nitride film layer or membranous layer of silicon oxide and is nucleated
Sub- film layer further reduced the crystal lattice difference between adjacent film layers, reduce the probability of electrostatic generation.
Embodiment two
The present embodiment provides a kind of display devices, including display panel described in embodiment one as above.
Display device provided in this embodiment, the first film layer of display panel include be arranged in film layer adjacent thereto it
Between low temperature at nucleon film layer, low temperature is identical as the first film layer at the material of nucleon film layer, due to atom in low temperature at nucleon film
The transfer ability of layer surface is weaker, therefore low temperature can effectively reduce the first film layer and film layer adjacent thereto at nucleon film layer
Between grain boundary defects, reduce charge interface accumulation, reduce electrostatic generate probability；Further, in display panel
The second film layer in be equipped with transition zone between adjacent two kinds of material layers, transition zone is the atom institute in two kinds of adjacent material layers
The composite layer of composition, to reduce grain boundary defects, is reduced so as to reduce the crystal lattice difference between two adjacent film layers
Charge reduces the probability that electrostatic generates in the accumulation of interface.The present embodiment can guarantee the normal display of display device simultaneously
The significant service life for improving display device.
In the description of the present invention, it is to be understood that, term " center ", " longitudinal direction ", " transverse direction ", " length ", " width ",
" thickness ", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outside", " up time
The orientation or positional relationship of the instructions such as needle ", " counterclockwise ", " axial direction ", " radial direction ", " circumferential direction " be orientation based on the figure or
Positional relationship is merely for convenience of description of the present invention and simplification of the description, rather than the device or element of indication or suggestion meaning must
There must be specific orientation, be constructed and operated in a specific orientation, therefore be not considered as limiting the invention.
In the present invention unless specifically defined or limited otherwise, term " installation ", " connected ", " connection ", " fixation " etc.
Term shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integral；It can be direct phase
Even, can also indirectly connected through an intermediary, the interaction that can be connection or two elements inside two elements is closed
System.For the ordinary skill in the art, above-mentioned term in the present invention specific can be understood as the case may be
Meaning.
It should be noted that in the description of the present invention, term " first ", " second ", which are only used for facilitating, describes different portions
Part is not understood to indicate or imply ordinal relation, relative importance or the number for implicitly indicating indicated technical characteristic
Amount." first " is defined as a result, the feature of " second " can explicitly or implicitly include at least one of the features.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (10)
1. a kind of display panel, which is characterized in that including the substrate and thin film transistor (TFT) being cascading, wherein described thin
Film transistor includes multiple first film layers and multiple second film layers being stacked, and first film layer is homogenous material film layer,
Second film layer is the composite film that a variety of different material layers are laminated, and first film layer includes being arranged adjacent thereto
Film layer between low temperature at nucleon film layer, transition zone is equipped in second film layer between two kinds of adjacent material layers,
The composite layer that the transition zone is made of the atom in two kinds of adjacent material layers.
2. display panel according to claim 1, which is characterized in that first film layer includes membranous layer of silicon oxide or nitridation
Silicon film, the membranous layer of silicon oxide include barrier layer and gate insulating layer, and the silicon nitride film layer includes dielectric layer and passivation
Layer.
3. display panel according to claim 2, which is characterized in that the barrier layer, which is included at 200 DEG C, to be deposited
The first barrier layer and at 370 DEG C deposit made of the second barrier layer, first barrier layer with a thickness of 30-50 nanometers,
Second barrier layer with a thickness of 550-570 nanometers.
4. display panel according to claim 2, which is characterized in that the gate insulating layer, which is included at 200 DEG C, to be deposited
Made of first grid insulating layer and at 420 DEG C deposit made of second grid insulating layer, the first grid insulating layer
With a thickness of 30-50 nanometers, the second grid insulating layer with a thickness of 90-110 nanometers.
5. display panel according to claim 2, which is characterized in that the dielectric layer be included at 200 DEG C deposit and
At the first dielectric layer and at 420 DEG C deposit made of the second dielectric layer, first dielectric layer with a thickness of 30-
50 nanometers, second dielectric layer with a thickness of 70-90 nanometers.
6. display panel according to claim 2, which is characterized in that the passivation layer, which is included at 100 DEG C, to be deposited
The first passivation layer and at 270 DEG C deposit made of the second passivation layer, first passivation layer with a thickness of 30-50 nanometers,
Second passivation layer with a thickness of 220-240 nanometers.
7. display panel according to claim 1, which is characterized in that second film layer includes at least one silicon oxide film
Layer and silicon nitride film layer, second film layer include the first inorganic film and the second inorganic film.
8. display panel according to claim 7, which is characterized in that second inorganic film includes the nitrogen stacked gradually
SiClx film layer, silicon oxynitride film and membranous layer of silicon oxide；Wherein, the silicon nitride film layer is included at 200 DEG C made of deposition
First silicon nitride film layer and at 420 DEG C deposit made of the second silicon nitride film layer, first silicon nitride film layer with a thickness of
5-15 nanometers, second silicon nitride film layer with a thickness of 30-40 nanometers；The depositing temperature of the silicon oxynitride film is 420
DEG C, the silicon oxynitride film with a thickness of 90-110 nanometers；The membranous layer of silicon oxide is included in deposited at 200 DEG C made of the
Silicon monoxide film layer and at 420 DEG C deposit made of the second membranous layer of silicon oxide, first membranous layer of silicon oxide with a thickness of 30-
50 nanometers, second membranous layer of silicon oxide with a thickness of 200-220 nanometers.
9. display panel according to claim 7, which is characterized in that first inorganic film includes the oxygen stacked gradually
SiClx film layer, silicon oxynitride film and silicon nitride film layer；Wherein, the membranous layer of silicon oxide is included at 200 DEG C made of deposition
Third membranous layer of silicon oxide and at 370 DEG C deposit made of the 4th membranous layer of silicon oxide, the third membranous layer of silicon oxide with a thickness of
30-50 nanometers, the 4th membranous layer of silicon oxide with a thickness of 220-240 nanometers；The depositing temperature of the silicon oxynitride film is
370 DEG C, the silicon oxynitride film with a thickness of 90-110 nanometers；The silicon nitride film layer, which is included at 200 DEG C, to be deposited
Third silicon nitride film layer and at 370 DEG C deposit made of the 4th silicon nitride film layer, the thickness of the third silicon nitride film layer
Be 30-50 nanometers, the 4th silicon nitride film layer with a thickness of 170-190 nanometers.
10. a kind of display device, which is characterized in that including the display panel as described in any in claim 1-9.
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Application publication date: 20191105 |