CN110391796B - Self-adaptive time sequence dynamic comparator - Google Patents
Self-adaptive time sequence dynamic comparator Download PDFInfo
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- CN110391796B CN110391796B CN201910474197.5A CN201910474197A CN110391796B CN 110391796 B CN110391796 B CN 110391796B CN 201910474197 A CN201910474197 A CN 201910474197A CN 110391796 B CN110391796 B CN 110391796B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
- H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
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Abstract
The invention provides a self-adaptive time sequence dynamic comparator, which comprises an input sampling and holding circuit (100), a preamplifier (101), an output latch (102) and a conversion completion signal pulse width locking feedback path (103); the conversion completion signal pulse width locking feedback path (103) comprises a latch output effective detection circuit (104), a conversion completion pulse width generation circuit (105), a pulse width current conversion circuit (106) and a latch clock generation circuit (107). Compared with the prior art, the self-adaptive time sequence dynamic comparator has the following advantages: the clock signal for controlling the working time of the latch can be automatically generated, and the signal width is determined by the working speed of the latch. Meanwhile, the comparator adjusts the output voltage establishment time of the preamplifier of the comparator through the time interval from the effective output of the loop locking comparator to the next sampling, so that the highest working frequency of the comparator is improved, and the influences of the process, the power supply voltage and the working temperature are overcome.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a self-adaptive timing dynamic comparator.
Background
Comparators are widely used in the field of integrated circuits for converting analog signals to digital signals. In modern high-speed low-power circuit design, dynamic comparators are widely used in various analog-to-digital conversion circuits due to low power consumption. Along with the rapid increase of signal bandwidth and analog-to-digital conversion operating frequency in modern integrated circuits, higher requirements are also put on the operating speed of comparators.
In the prior art, the chinese invention patent "a positive feedback isolated dynamic latch comparator" (application number: 201610381483.3) discloses a positive feedback isolated dynamic latch comparator, which comprises a cross-coupled input unit, an input reset unit, a CMOS isolation switch unit, a cross-coupled latch structure unit, a latch reset unit, an output shaping unit, and a positive feedback unit. The cross-coupling input converts an input voltage signal into current, and the cross-coupling latch structure and the latch reset complete a comparison function; the CMOS isolating switch isolates the cross-coupling input and the cross-coupling latch structure in a reset stage, so that the influence of kickback noise is reduced; input reset resets the cross-coupled input output terminal in a reset phase; the positive feedback is controlled by the output of the output shaping, and the discharge current is increased in the comparison stage; CLK and NCLK are two-phase non-overlapping clocks providing timing for the entire dynamic latch comparator. The invention can obviously improve the speed and the precision of the dynamic latch comparator and improve the power consumption.
However, the conventional dynamic comparator in the prior art fixedly allocates the sampling, amplifying and latching time, and a large time margin needs to be reserved in each interval in order to cope with the changes of the process, the power supply voltage and the working temperature, so that the maximum working frequency of the comparator is limited.
Disclosure of Invention
In view of the shortcomings in the prior art, the present invention is directed to a dynamic comparator with adaptive timing that effectively allocates time within one comparator duty cycle.
In order to solve the technical problem, the invention provides a self-adaptive time sequence dynamic comparator, which comprises an input sampling and holding circuit (100), a preamplifier (101), an output latch (102) and a conversion completion signal pulse width locking feedback path (103); the conversion completion signal pulse width locking feedback path (103) comprises a latch output effective detection circuit (104), a conversion completion pulse width generation circuit (105), a pulse width current conversion circuit (106) and a latch clock generation circuit (107);
the input end of the latch output effective detection circuit (104) is electrically connected with the output end of the output latch (102), and the output end of the latch output effective detection circuit (104) is respectively electrically connected with the input ends of the conversion completion pulse width generation circuit (105) and the latch clock generation circuit (107);
the output end of the converted pulse width generation circuit (105) is respectively electrically connected with the input ends of the pulse width current conversion circuit (106) and the latch clock generation circuit (107);
the output end of the pulse width current conversion circuit (106) is electrically connected with the latch clock generation circuit (107);
the output end of the latch clock generating circuit (107) is respectively and electrically connected with the input end of the output latch (102) and the output effective detection circuit (104).
Preferably, the latch output valid detection circuit (104) comprises:
the output end DP and the output end DN of the output latch (102) are respectively and electrically connected with the input end of the NAND gate (1011), and the output end of the NAND gate (1011) is respectively and electrically connected with the input ends of the conversion completion pulse width generating circuit (105) and the latch clock generating circuit (107);
the output end of the latch clock generating circuit (107) is electrically connected with the input end of the first inverter (1008), and the output end of the first inverter (1008) is electrically connected with the input end of the NAND gate (1011) through the first latch output pull-up switch (1009) and the second latch output pull-up switch (1010) respectively.
Preferably, the conversion completion pulse width generating circuit (105) includes:
a second inverter (1013), an input terminal of the second inverter (1013) being electrically connected to the sampling clock CKS;
and an RN pin of the standard unit latch (1012) is electrically connected with an output end of the second inverter (1013), a CK pin of the standard unit latch (1012) is electrically connected with an output end of the NAND gate (1011), a D pin of the standard unit latch (1012) is electrically connected with a power supply VDD, and a Q pin of the standard unit latch (1012) is electrically connected with input ends of the pulse width current conversion circuit (106) and the latch clock generation circuit (107) respectively.
Preferably, the pulse width current conversion circuit (106) includes:
the Q pin of the standard unit latch (1012) is electrically connected with the input end of the RC filter;
the positive phase input end of the voltage amplifier (1016) is electrically connected with the output end of the RC filter;
one end of the voltage division component is electrically connected with the RC filter, the other end of the voltage division component is electrically connected with a power supply VDD, and the inverting input end of the voltage amplifier (1016) is electrically connected with the voltage division component;
and the source of the PMOS current output stage (1019) is electrically connected with a power supply VDD, the gate of the PMOS current output stage (1019) is electrically connected with the output end of the voltage amplifier (1016), and the drain of the PMOS current output stage (1019) is electrically connected with the latch clock generation circuit (107).
Preferably, the RC filter comprises:
the Q pin of the standard unit latch (1012) is electrically connected with one end of the filter resistor (1014), and the non-inverting input end of the voltage amplifier (1016) is electrically connected with the other end of the filter resistor (1014);
and the anode of the filter capacitor (1015) is electrically connected with the other end of the filter resistor (1014), and the cathode of the filter capacitor (1015) is grounded.
Preferably, the voltage dividing assembly comprises:
one end of the first power supply voltage-dividing resistor (1017) is electrically connected with the negative electrode of the filter capacitor (1015), and the other end of the first power supply voltage-dividing resistor (1017) is electrically connected with the inverting input end of the voltage amplifier (1016);
and one end of the second power supply voltage division resistor (1018) is electrically connected with the inverted input end of the voltage amplifier (1016), and the other end of the second power supply voltage division resistor (1018) is electrically connected with a power supply VDD.
Preferably, the latch clock generating circuit (107) comprises:
the three-input NOR gate (1020), three input ends of the three-input NOR gate (1020) are respectively and electrically connected with the Q pin of the standard unit latch (1012), the sampling clock CKS and the output end of the NAND gate (1011), and the drain electrode of the current output stage (1019) is electrically connected with the three-input NOR gate (1020);
the input end of the clock buffer (1021) is electrically connected with the output end of the three-input NOR gate (1020), and the output end of the clock buffer (1021) is electrically connected with the input ends of the output latch (102) and the first inverter (1008) respectively.
Preferably, the input sample-and-hold circuit (100) comprises:
a first input component, which connects the input signal Vip with the preamplifier (101);
a second input component, which is connected with the input signal Vin and the preamplifier (101);
and two ends of the bottom plate switch (1007) are respectively connected with the first input assembly and the second input assembly.
Preferably, the first input assembly comprises:
a first backplane sampling switch (1001), one end of the first backplane sampling switch (1001) being electrically connected to the input signal Vip;
the positive electrode of the first sampling capacitor (1005) is electrically connected with the other end of the first bottom plate sampling switch (1001), and the negative electrode of the first sampling capacitor (1005) is electrically connected with the first input end of the preamplifier (101);
a first top plate sampling switch (1003), the first top plate sampling switch (1003) connecting the fixed bias voltage VCM with a first input of the preamplifier (101);
one end of the bottom plate switch (1007) is electrically connected with the other end of the first bottom plate sampling switch (1001).
Preferably, the second input assembly comprises:
one end of the second bottom plate sampling switch (1002) is electrically connected with the input signal Vin;
the anode of the second sampling capacitor (1006) is electrically connected with the other end of the second bottom plate sampling switch (1002), and the cathode of the second sampling capacitor (1006) is electrically connected with the second input end of the preamplifier (101);
a second top plate sampling switch (1004), the second top plate sampling switch (1004) connecting the fixed bias voltage VCM to the second input of the preamplifier (101);
the other end of the bottom plate switch (1007) is electrically connected with the other end of the second bottom plate sampling switch (1002).
Compared with the prior art, the self-adaptive time sequence dynamic comparator has the following advantages: the clock signal for controlling the working time of the latch can be automatically generated, and the signal width is determined by the working speed of the latch. Meanwhile, the comparator adjusts the output voltage establishment time of the preamplifier of the comparator through the time interval from the effective output of the loop locking comparator to the next sampling, so that the highest working frequency of the comparator is improved, and the influences of the process, the power supply voltage and the working temperature are overcome.
Drawings
Other characteristic objects and advantages of the invention will become more apparent upon reading the detailed description of non-limiting embodiments with reference to the following figures.
FIG. 1 is a schematic diagram of an architecture of a self-adaptive timing dynamic comparator according to the present invention;
FIG. 2 is a schematic diagram of the working timing of the adaptive timing dynamic comparator according to the present invention.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that variations and modifications can be made by persons skilled in the art without departing from the spirit of the invention.
As shown in fig. 1 to fig. 2, the adaptive timing dynamic comparator according to the present invention comprises an input sample-and-hold circuit 100, a preamplifier AMP101, an output latch 102, and a pulse width lock feedback path 103 for a conversion completion signal (EOC), wherein: the input of the input sample-and-hold circuit 100 is the positive and negative input signals Vip, vin of the comparator, the output Vc thereof is connected to the input of the preamplifier 101, the positive and negative output terminals Vop, von of the preamplifier 101 are connected to the input of the output latch 102, and the output of the output latch 102 is connected to the input of the EOC signal pulse width locking feedback path 103. The other input of the EOC signal pulse width lock feedback path 103 is a sampling clock CKS, the output of which is connected to a clock input CK _ LAT to the output latch 102.
The EOC signal pulse width lock feedback path 103 is composed of a latch output valid detection circuit 104, an EOC pulse width generation circuit 105, a pulse width current conversion circuit 106, and a latch clock generation circuit 107. The latch output valid detection circuit 104 has its input terminals connected to the outputs DP, DN of the latch 102, and its output comparator valid signal CMP _ RDY is connected to the input terminals of both the EOC pulse width generation circuit 105 and the latch clock generation circuit 107. The EOC pulse width generating circuit 105 inputs the sampling clock CKS and the output signal CMP _ RDY of the latch output valid detection circuit 104, and its output signal EOC is connected to the input terminals of the pulse width current conversion circuit 106 and the latch clock generating circuit 107 at the same time. The current output from the pulse width current conversion circuit 106 is connected to the input terminal of the latch clock generation circuit 107. The output CK _ LAT of the latch clock generation circuit 107 is connected to the input terminals of the output latch 102 and the output valid detection circuit 104, respectively.
The input sample-and-hold circuit 100 includes bottom plate sampling switches S11001, S21002, top plate sampling switches S31003, S41004, sampling capacitors C11005, C21006, and a bottom plate switch 1007.
The bottom plate sampling switches S11001 and S21002 connect the input signals Vip and Vin with sampling capacitors C11005 and C21006; the top plate sampling switches S31003, S41004 connect the fixed bias voltage VCM to the input of the preamplifier 101.
The preamplifier 100 has an input connected to the output of the sample and hold circuit and an output connected to the input of the latch 102.
An output latch 102 whose input is the output of the preamplifier 101, and whose outputs DP, DN are connected to the output valid detection circuit 104; the latch is controlled to be on or off by the signal CK _ LAT, the output of which assumes a high-impedance state when CK _ LAT is low.
The EOC signal pulse width lock feedback path 103 is composed of a latch output valid detection circuit 104, an EOC pulse width generation circuit 105, a pulse width current conversion circuit 106, and a latch clock generation circuit 107. The latch output valid detection circuit 104 has inputs connected to the outputs DP and DN of the latch 102, and its output comparator valid signal CMP _ RDY is connected to the inputs of the EOC pulse width generation circuit 105 and the latch clock generation circuit 107 at the same time. The EOC pulse width generating circuit 105 inputs the sampling clock CKS and the output signal CMP _ RDY of the latch output valid detection circuit 104, and its output signal EOC is connected to the input terminals of the pulse width current conversion circuit 106 and the latch clock generating circuit 107 at the same time. The current output from the pulse width current conversion circuit 106 is connected to the input terminal of the latch clock generation circuit 107. The output CK _ LAT of the latch clock generation circuit 107 is connected to the input terminals of the output latch 102 and the output valid detection circuit 104, respectively.
During the operation of the EOC signal pulse width locking feedback path 103, the latch output valid detection circuit 104 monitors the outputs DP and DN of the latch 102, and when any one of the signals is low, it determines that the comparator output is valid, and sets the output signal CMP _ RDY high. The CMP _ RDY signal is provided to the nor input of the latch clock generation circuit 107, pulling its output CK _ LAT low directly. At the same time, CMP _ RDY and the sampling clock are sent to the EOC pulse width generating circuit 105, which outputs a pulse signal EOC, the width of which represents the waiting time after the comparator completes one comparison. The EOC pulse width is converted into the magnitude of the pull-up current of the nor gate 1020 in the latch clock generation circuit 107 through the pulse width current conversion circuit 106 to control the delay of the CK _ LAT rising edge. The latch clock generation circuit 107 pulls up the signal CK _ LAT at the falling edge of the sampling clock CKS, and the delay thereof is controlled by the current magnitude converted from the EOC signal width; CK _ LAT is pulled low on the rising edge of CMP _ RDY while the output signal of the comparator is pulled high.
The latch output effective detection circuit 104 consists of an inverter 1008, latch output pull-up switches 1009 to 1010 and an NAND gate 1011; CMP _ RDY is set high when either latch output signal DP, DN is low.
The EOC pulse generating circuit 105 is composed of a standard cell latch 1012 with a reset switch, an inverter 1013, and a pull-up power supply; the inputs are CMP _ RDY and the sampling clock CKS, and the pulse width for generating EOC is proportional to the interval from the rising edge of CMP _ RDY to the rising edge of CKS. The standard cell latch 1012 with the reset switch can be implemented by any circuit configuration latch, and only the implementation of the latching and resetting functions is required.
The pulse width current conversion circuit 106 is composed of RC filters 1014 to 1015, a voltage amplifier 1016, power supply voltage division resistors 1017 to 1018 and a PMOS current output stage 1019; the pulse width of the ECO signal is converted into a direct current level through filtering, the difference value between the direct current level and the output level of the power supply voltage dividing resistors 1017-1018 is amplified and then acts on the grid of the PMOS1019, and the output current of the drain of the PMOS1019 is inversely proportional to the pulse width of the EOC signal.
The latch clock generation circuit 107 is composed of a three-input nor gate 1020 and a clock buffer 1021;
the NOR gate inputs are CKS, EOC and CMP _ RDY, and outputs CK _ LAT via the buffer. The rising edge of the latch clock CK _ LAT is obtained by the time delay of the falling edge of the sampling clock CKs passing through the nor gate 1020 and the buffer 1021;
the falling edge of CK _ LAT is obtained by the time delay of the rising edge of CMP _ RDY through nor gate 1020 and buffer 1021, which is proportional to the output current of pulse width current conversion circuit 106.
Conventional dynamic comparators fix the time to distribute sampling, amplification and latching. In order to cope with the process, the variation of the power supply voltage and the operating temperature needs to reserve a large time margin in each interval, thereby limiting the highest operating frequency of the comparator. To solve this problem, the present invention proposes an adaptive timing dynamic comparator as shown in fig. 1. Besides the sample hold circuit, the preamplifier and the latch of the traditional dynamic comparator, the structure of the invention also comprises an EOC signal pulse width locking feedback path 103. The output DP and DN of the latch 102 is monitored by the latch output detection circuit 104, and when any one of the signals is low, the comparator output is determined to be valid, and the output signal CMP _ RDY is set high. The CMP _ RDY signal is provided to the nor input of the latch clock generation circuit 107, pulling its output CK _ LAT low directly. At the same time, CMP _ RDY and the sampling clock CKS are sent to the EOC pulse width generating circuit 105, which outputs a pulse signal EOC with a width representing the waiting time after the comparator completes one comparison. The EOC pulse width is converted into the magnitude of pull-up current of the nor gate in the latch clock generation circuit 107 by the pulse width current conversion circuit 106, by which the delay of the CK _ LAT rising edge is controlled. The latch clock generating circuit 107 pulls up the signal CK _ LAT at the falling edge of the sampling clock CKS, and the delay time thereof is controlled by the current magnitude converted from the EOC signal width; CK _ LAT is pulled low on the rising edge of CMP _ RDY while the comparator's output signals DP, DN are pulled high. Fig. 2 shows the operation timing of each module of the comparator in one clock cycle, where Ts represents the sampling time, ta represents the setup time of the preamplifier 101, tl represents the operation time of the latch 102, which includes the time T1 required for pulling down the latch output and the time delays T2 and T3 caused by the latch clock generation circuit 107 and the output valid detection circuit 104, te represents the width of the EOC signal, and T represents the total time of one complete cycle of the comparator. Following the equation Te = T-Ts-Ta-Tl, te is locked by the loop and the value of Te/T is determined by the reference voltage VR resulting from the voltage division of the power supply. At this time, the sum of Tl and Ta is fixed, and when the latch 102 operation time Tl is short, the output setup time Ta of the sample-and-hold circuit 100 and the preamplifier 101 becomes long, and vice versa. This feature effectively utilizes all time in each complete comparator duty cycle, which is beneficial to increasing the highest operating frequency of the comparator.
The implementation form of the pulse width locking feedback path of the EOC signal of the adaptive timing dynamic comparator provided by the invention is not limited to the way of converting the pulse width signal into the current signal to control the time delay. Any circuit form that converts the pulse width of the signal into the delay control signal can be used in the circuit structure proposed by the present invention.
Claims (7)
1. A self-adaptive time sequence dynamic comparator is characterized by comprising an input sampling and holding circuit (100), a preamplifier (101), an output latch (102) and a conversion completion signal pulse width locking feedback path (103); wherein
The conversion completion signal pulse width locking feedback path (103) comprises a latch output effective detection circuit (104), a conversion completion pulse width generation circuit (105), a pulse width current conversion circuit (106) and a latch clock generation circuit (107);
a first input end of the latch output effective detection circuit (104) is electrically connected with an output end of the output latch (102), and an output end of the latch output effective detection circuit (104) is respectively electrically connected with input ends of the conversion completion pulse width generation circuit (105) and the latch clock generation circuit (107);
the output end of the converted pulse width generation circuit (105) is respectively and electrically connected with the input ends of the pulse width current conversion circuit (106) and the latch clock generation circuit (107);
the output end of the pulse width current conversion circuit (106) is electrically connected with the latch clock generation circuit (107);
the output end of the latch clock generating circuit (107) is respectively and electrically connected with the second input ends of the output latch (102) and the output valid detection circuit (104);
a latch output valid detection circuit (104) includes:
the output end DP and the output end DN of the output latch (102) are respectively and electrically connected with the input end of the NAND gate (1011), and the output end of the NAND gate (1011) is respectively and electrically connected with the input ends of the conversion completion pulse width generating circuit (105) and the latch clock generating circuit (107);
the output end of the latch clock generating circuit (107) is electrically connected with the input end of the first inverter (1008), and the output end of the first inverter (1008) is electrically connected with the input end of the NAND gate (1011) through a first latch output pull-up switch (1009) and a second latch output pull-up switch (1010) respectively;
the conversion completion pulse width generation circuit (105) includes:
a second inverter (1013), an input terminal of the second inverter (1013) being electrically connected to the sampling clock CKS;
a standard unit latch (1012), wherein an RN pin of the standard unit latch (1012) is electrically connected with an output end of the second inverter (1013), a CK pin of the standard unit latch (1012) is electrically connected with an output end of the NAND gate (1011), a D pin of the standard unit latch (1012) is electrically connected with a power supply VDD, and a Q pin of the standard unit latch (1012) is electrically connected with input ends of the pulse width current conversion circuit (106) and the latch clock generation circuit (107) respectively;
the pulse width current conversion circuit (106) includes:
an RC filter, the Q pin of the standard cell latch (1012) being electrically connected to the input of the RC filter;
the positive phase input end of the voltage amplifier (1016) is electrically connected with the output end of the RC filter;
one end of the voltage division component is electrically connected with the RC filter, the other end of the voltage division component is electrically connected with a power supply VDD, and the inverting input end of the voltage amplifier (1016) is electrically connected with the voltage division component;
and the source of the PMOS current output stage (1019) is electrically connected with a power supply VDD, the gate of the PMOS current output stage (1019) is electrically connected with the output end of the voltage amplifier (1016), and the drain of the PMOS current output stage (1019) is electrically connected with the latch clock generation circuit (107).
2. The adaptively clocked dynamic comparator as claimed in claim 1, wherein the RC filter comprises:
the Q pin of the standard unit latch (1012) is electrically connected with one end of the filter resistor (1014), and the non-inverting input end of the voltage amplifier (1016) is electrically connected with the other end of the filter resistor (1014);
and the anode of the filter capacitor (1015) is electrically connected with the other end of the filter resistor (1014), and the cathode of the filter capacitor (1015) is grounded.
3. The adaptive timing dynamic comparator according to claim 2, wherein the voltage divider module comprises:
one end of the first power supply voltage-dividing resistor (1017) is electrically connected with the negative electrode of the filter capacitor (1015), and the other end of the first power supply voltage-dividing resistor (1017) is electrically connected with the inverting input end of the voltage amplifier (1016);
and one end of the second power supply voltage division resistor (1018) is electrically connected with the inverted input end of the voltage amplifier (1016), and the other end of the second power supply voltage division resistor (1018) is electrically connected with a power supply VDD.
4. The adaptively clocked dynamic comparator as claimed in claim 3, wherein the latch clock generation circuit (107) comprises:
the three input ends of the three-input NOR gate (1020) are respectively and electrically connected with a Q pin of the standard unit latch (1012), a sampling clock CKS and the output end of the NAND gate (1011), and the drain electrode of the current output stage (1019) is electrically connected with the three-input NOR gate (1020);
the input end of the clock buffer (1021) is electrically connected with the output end of the three-input NOR gate (1020), and the output end of the clock buffer (1021) is electrically connected with the input ends of the output latch (102) and the first inverter (1008) respectively.
5. The adaptively clocked dynamic comparator according to claim 1, wherein the input sample and hold circuit (100) comprises:
a first input component, which connects the input signal Vip with the preamplifier (101);
a second input component, which is connected with the input signal Vin and the preamplifier (101);
two ends of the bottom plate switch (1007) are respectively connected with the first input assembly and the second input assembly.
6. The adaptively timed dynamic comparator as in claim 5, wherein the first input component comprises:
the first bottom plate sampling switch (1001), one end of the first bottom plate sampling switch (1001) is electrically connected with the input signal Vip;
the positive electrode of the first sampling capacitor (1005) is electrically connected with the other end of the first bottom plate sampling switch (1001), and the negative electrode of the first sampling capacitor (1005) is electrically connected with the first input end of the preamplifier (101);
a first top plate sampling switch (1003), the first top plate sampling switch (1003) connecting the fixed bias voltage VCM with a first input of the preamplifier (101);
one end of the bottom plate switch (1007) is electrically connected with the other end of the first bottom plate sampling switch (1001).
7. The adaptively clocked dynamic comparator as claimed in claim 6, wherein the second input component comprises:
one end of the second bottom plate sampling switch (1002) is electrically connected with the input signal Vin;
the anode of the second sampling capacitor (1006) is electrically connected with the other end of the second bottom plate sampling switch (1002), and the cathode of the second sampling capacitor (1006) is electrically connected with the second input end of the preamplifier (101);
a second top plate sampling switch (1004), the second top plate sampling switch (1004) connecting the fixed bias voltage VCM to the second input of the preamplifier (101);
the other end of the bottom plate switch (1007) is electrically connected with the other end of the second bottom plate sampling switch (1002).
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