CN110391796A - The dynamic comparer of self-adaptive time sequence - Google Patents
The dynamic comparer of self-adaptive time sequence Download PDFInfo
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- CN110391796A CN110391796A CN201910474197.5A CN201910474197A CN110391796A CN 110391796 A CN110391796 A CN 110391796A CN 201910474197 A CN201910474197 A CN 201910474197A CN 110391796 A CN110391796 A CN 110391796A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
- H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
Abstract
The present invention provides a kind of dynamic comparer of self-adaptive time sequence, including input sample holding circuit (100), prime amplifier (101), output latch (102) and converts signal pulsewidth locking feedback network (103)；Wherein converting signal pulsewidth locking feedback network (103) includes that latch exports effective detection circuit (104), converts pulsewidth generation circuit (105), pulsewidth current converter circuit (106) and latch clock generation circuit (107).Compared with prior art, the dynamic comparer of self-adaptive time sequence of the present invention has the advantage that the clock signal that can automatically generate the control latch working time, the signal width are determined by the operating rate of latch.The comparator exports also by loop-locking comparator and adjusts output voltage settling time of comparator prime amplifier valid till the when interval between sampling next time simultaneously, comparator maximum operating frequency is improved to reach, overcome technique, supply voltage, the influence of operating temperature.
Description
Technical field
The invention belongs to technical field of integrated circuits, and in particular to a kind of dynamic comparer of self-adaptive time sequence.
Background technique
Comparator is widely used in conversion process of the analog signal to digital signal in integrated circuit fields.Existing
For in high-speed low-power-consumption circuit design, dynamic comparer is widely used in all kinds of analog to digital conversion circuits because of lower power consumption
In.Work along with the quick raising of signal bandwidth in modern integrated circuits and analog-to-digital conversion working frequency, to comparator
Higher requirements are also raised for rate
The prior art, Chinese invention patent " a kind of positive feedback isolation dynamic latch comparator " (application number:
201610381483.3) a kind of positive feedback isolation dynamic latch comparator is disclosed, including cross-coupling input unit, input reset
Unit, CMOS Disconnecting switch unit, cross-coupling latch structure unit, latch reset unit, output Shaping unit and positive feedback
Unit.Input voltage signal is converted into electric current by cross-coupling input, and cross-coupling latch structure and latch reset completion are compared
Function；CMOS disconnecting switch is isolated by cross-coupling input and cross-coupling latch structure in reseting stage, and reduction kicks back noise
Influence；Input resets at the output end that reseting stage inputs cross-coupling and resets；Positive feedback by output Shaping output control
System increases discharge current in comparison phase；CLK and NCLK is that two-phase does not overlap clock, is provided for entire dynamic latch comparator
Timing.The present invention can significantly improve the speed and precision of dynamic latch comparator, and power consumption is made moderate progress.
But traditional dynamic comparer fixed allocation sampling in the prior art, amplification and the time latched, in order to answer
To technique, supply voltage, the variation of operating temperature needs to retain biggish time margin in each section, to limit comparator
The maximum operating frequency of itself.
Summary of the invention
For the defects in the prior art, it is effective within a comparator duty cycle that it is an object of that present invention to provide one kind
Distribute the dynamic comparer of the self-adaptive time sequence of time.
In order to solve the above technical problems, the present invention provides a kind of dynamic comparer of self-adaptive time sequence, including input sample
Holding circuit (100), prime amplifier (101), output latch (102) and convert signal pulsewidth locking feedback network
(103)；Wherein
Converting signal pulsewidth locking feedback network (103) includes that latch exports effective detection circuit (104), conversion
Complete pulsewidth generation circuit (105), pulsewidth current converter circuit (106) and latch clock generation circuit (107)；
The input terminal that latch exports effective detection circuit (104) is electrically connected with the output end of output latch (102), is locked
Storage export the output end of effective detection circuit (104) respectively with convert pulsewidth generation circuit (105) and latch clock
The input terminal of generation circuit (107) is electrically connected；
Convert the output end of pulsewidth generation circuit (105) respectively with pulsewidth current converter circuit (106) and latch
The input terminal of clock generation circuit (107) is electrically connected；
The output end of pulsewidth current converter circuit (106) is electrically connected with latch clock generation circuit (107)；
The output end of latch clock generation circuit (107) is electric with output latch (102) and output effectively detection respectively
The input terminal on road (104) is electrically connected.
Preferably, the effective detection circuit (104) of latch output includes:
NAND gate (1011), the output end DP and output end DN of output latch (102) respectively with NAND gate (1011)
Input terminal electrical connection, the output end of NAND gate (1011) respectively with convert pulsewidth generation circuit (105) and latch clock
The input terminal of generation circuit (107) is electrically connected；
First phase inverter (1008), the output end of latch clock generation circuit (107) and the first phase inverter (1008)
Input terminal electrical connection, the output end of the first phase inverter (1008) pass through the first latch output pull-up switch (1009) and the respectively
Two latch output pull-up switch (1010) is electrically connected with the input terminal of NAND gate (1011).
Preferably, converting pulsewidth generation circuit (105) includes:
The input terminal of second phase inverter (1013), the second phase inverter (1013) is electrically connected with sampling clock CKS；
Standard block latch (1012), the RN pin of standard block latch (1012) and the second phase inverter (1013)
Output end electrical connection, the CK pin of standard block latch (1012) are electrically connected with the output end of NAND gate (1011), standard list
The D pin of first latch (1012) is electrically connected with power vd D, and the Q pin of standard block latch (1012) is electric with pulsewidth respectively
Flow the input terminal electrical connection of conversion circuit (106) and latch clock generation circuit (107).
Preferably, pulsewidth current converter circuit (106) includes:
The Q pin of RC filter, standard block latch (1012) is electrically connected with the input terminal of RC filter；
The output end of voltage amplifier (1016), the normal phase input end and RC filter of voltage amplifier (1016) is electrically connected
It connects；
Component is divided, the one end for dividing component is electrically connected with RC filter, and the other end and power vd D for dividing component are electrically connected
It connects, the inverting input terminal of voltage amplifier (1016) is electrically connected with partial pressure component；
The source electrode of PMOS circuit output stage (1019), PMOS circuit output stage (1019) is electrically connected with power vd D, PMOS electricity
The grid of stream output stage (1019) is electrically connected with the output end of voltage amplifier (1016), the leakage of PMOS circuit output stage (1019)
Pole is electrically connected with latch clock generation circuit (107).
Preferably, RC filter includes:
One end of filter resistance (1014), the Q pin and filter resistance (1014) of standard block latch (1012) is electrically connected
It connects, the normal phase input end of voltage amplifier (1016) is electrically connected with the other end of filter resistance (1014)；
The anode of filter capacitor (1015), filter capacitor (1015) is electrically connected with the other end of filter resistance (1014), is filtered
The cathode of wave capacitor (1015) is grounded.
Preferably, partial pressure component includes:
First power supply divider resistance (1017), one end and filter capacitor (1015) of the first power supply divider resistance (1017)
Cathode electrical connection, the inverting input terminal of the other end and voltage amplifier (1016) of the first power supply divider resistance (1017) are electrically connected
It connects；
Second source divider resistance (1018), one end and voltage amplifier (1016) of second source divider resistance (1018)
Inverting input terminal electrical connection, the other end of second source divider resistance (1018) is electrically connected with power vd D.
Preferably, latch clock generation circuit (107) includes:
Three input nor gate (1020), three input nor gate (1020) three input terminals respectively with standard block latch
(1012) the output end electrical connection of Q pin, sampling clock CKS and NAND gate (1011), the drain electrode of circuit output stage (1019)
It is electrically connected with three inputs nor gate (1020)；
Clock buffer (1021), the output end of the input terminal of clock buffer (1021) and three inputs nor gate (1020)
Electrical connection, the input with output latch (102) and the first phase inverter (1008) respectively of the output end of clock buffer (1021)
End electrical connection.
Preferably, input sample holding circuit (100) includes:
First input module, the first input module connect input signal Vip and prime amplifier (101)；
Second input module, the second input module connect input signal Vin and prime amplifier (101)；
Backplane switch (1007), the both ends of backplane switch (1007) connect with the first input module and the second input module respectively
It connects.
Preferably, the first input module includes:
One end of first bottom plate sampling switch (1001), the first bottom plate sampling switch (1001) is electrically connected with input signal Vip
It connects；
First sampling capacitance (1005), anode and the first bottom plate sampling switch (1001) of the first sampling capacitance (1005)
Other end electrical connection, the cathode of the first sampling capacitance (1005) are electrically connected with the first input end of prime amplifier (101)；
First top plate sampling switch (1003), the first top plate sampling switch (1003) are connected and fixed bias voltage VCM and pre-
The first input end of amplifier (101)；
One end of backplane switch (1007) is electrically connected with the other end of the first bottom plate sampling switch (1001).
Preferably, the second input module includes:
One end of second bottom plate sampling switch (1002), the second bottom plate sampling switch (1002) is electrically connected with input signal Vin
It connects；
Second sampling capacitance (1006), anode and the second bottom plate sampling switch (1002) of the second sampling capacitance (1006)
Other end electrical connection, the cathode of the second sampling capacitance (1006) are electrically connected with the second input terminal of prime amplifier (101)；
Second top plate sampling switch (1004), the second top plate sampling switch (1004) are connected and fixed bias voltage VCM and pre-
Second input terminal of amplifier (101)；
The other end of backplane switch (1007) is electrically connected with the other end of the second bottom plate sampling switch (1002).
Compared with prior art, the dynamic comparer of self-adaptive time sequence of the present invention, which has the advantage that, can automatically generate control
The clock signal of lockmaking storage working time, the signal width are determined by the operating rate of latch.The comparator also leads to simultaneously
It crosses the output of loop-locking comparator and adjusts the output voltage of comparator prime amplifier valid till the when interval between sampling next time
Settling time improves comparator maximum operating frequency to reach, overcomes technique, supply voltage, the influence of operating temperature.
Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, other feature mesh of the invention
And advantage will become more apparent upon.
Fig. 1 is the configuration diagram of the dynamic comparer of self-adaptive time sequence of the present invention；
Fig. 2 is the dynamic comparer working sequence schematic diagram of self-adaptive time sequence of the present invention.
Specific embodiment
The present invention is described in detail combined with specific embodiments below.Following embodiment will be helpful to the technology of this field
Personnel further understand the present invention, but the invention is not limited in any way.It should be pointed out that the ordinary skill of this field
For personnel, without departing from the inventive concept of the premise, several change and modification can also be made.
As shown in FIG. 1 to FIG. 2, the dynamic comparer input sample holding circuit 100 of self-adaptive time sequence proposed by the present invention,
Prime amplifier AMP101, output latch 102 lock feedback network 103 with signal (EOC) pulsewidth is converted, in which: input
The input of sampling hold circuit 100 is positive and negative input signal Vip, Vin of comparator, exports the input of Vc and prime amplifier 101
It is connected, positive-negative output end Vop, Von of prime amplifier 101 are connected with the input of output latch 102, output latch 102
It exports and is connected with the input of eoc signal pulsewidth locking feedback network 103.The another way of eoc signal pulsewidth locking feedback network 103
Input is sampling clock CKS, and output is connected to the input end of clock CK_LAT of output latch 102.
Eoc signal pulsewidth locks feedback network 103 and exports effective detection circuit 104, EOC pulsewidth generation circuit by latch
105, pulsewidth current converter circuit 106 and latch clock generation circuit 107 form.Latch exports effective detection circuit 104
Input terminal is connected to output DP, DN of latch 102, and output comparator useful signal CMP_RDY is connected to EOC pulsewidth simultaneously
The input terminal of generation circuit 105 and latch clock generation circuit 107.The input of EOC pulsewidth generation circuit 105 is sampling clock
CKS and latch export effective 104 output signal CMP_RDY of detection circuit, and output signal EOC is connected to pulsewidth electric current simultaneously
The input terminal of conversion circuit 106 and latch clock generation circuit 107.The electric current connection that pulsewidth current converter circuit 106 exports
To the input terminal of latch clock generation circuit 107.The output CK_LAT of latch clock generation circuit 107 is then connected respectively to
Output latch 102 and the input terminal for exporting effective detection circuit 104.
Input sample holding circuit 100 include bottom plate sampling switch S11001, S21002, top plate sampling switch S31003,
S41004, sampling capacitance C11005, C21006 and backplane switch 1007.
Bottom plate sampling switch S11001, S21002 is input signal Vip, Vin and sampling capacitance C11005, C21006 phase
Even；Top plate sampling switch S31003, S41004 is connected fixed bias voltage VCM with the input of prime amplifier 101.
The input of prime amplifier 100 is connected to the output of sampling hold circuit, and output is connected to the input of latch 102.
Output latch 102, input are the output of prime amplifier 101, and output DP, DN are connected to output effectively detection
Circuit 104；By opening or closing for signal CK_LAT control latch, high-impedance state is presented when CK_LAT is low in output.
Eoc signal pulsewidth locks feedback network 103 and exports effective detection circuit 104, EOC pulsewidth generation circuit by latch
105, pulsewidth current converter circuit 106 and latch clock generation circuit 107 form.Latch exports effective detection circuit 104
Input terminal is connected to output DP, DN of latch 102, and output comparator useful signal CMP_RDY is connected to EOC pulsewidth simultaneously
The input terminal of generation circuit 105 and latch clock generation circuit 107.The input of EOC pulsewidth generation circuit 105 is sampling clock
CKS and latch export effective 104 output signal CMP_RDY of detection circuit, and output signal EOC is connected to pulsewidth electric current simultaneously
The input terminal of conversion circuit 106 and latch clock generation circuit 107.The electric current connection that pulsewidth current converter circuit 106 exports
To the input terminal of latch clock generation circuit 107.The output CK_LAT of latch clock generation circuit 107 is then connected respectively to
Output latch 102 and the input terminal for exporting effective detection circuit 104.
In eoc signal pulsewidth locking 103 course of work of feedback network, latch exports effective detection circuit 104 and monitors
Output DP, DN of latch 102 judge comparator output when wherein any one signal is low effectively, by output signal
CMP_RDY sets height.CMP_RDY signal is sent to the nor gate input terminal of latch clock generation circuit 107, directly outputs it
CK_LAT is dragged down.CMP_RDY and sampling clock are sent to EOC pulsewidth generation circuit 105 simultaneously, and output pulse signal EOC is wide
Degree represents comparator and completes the waiting time after primary compare.EOC pulse width is converted by pulsewidth current converter circuit 106
The size of 1020 pull-up current of nor gate controls the delay of CK_LAT rising edge in latch clock generation circuit 107.It latches
Device clock generation circuit 107 draws high signal CK_LAT in sampling clock CKS failing edge, delay converted by eoc signal width and
The size of current control come；CK_LAT is dragged down in the rising edge of CMP_RDY, while the output signal of comparator is set into height.
Latch exports effective detection circuit 104 by phase inverter 1008, and latch exports pull-up switch 1009~1010, with
NOT gate 1011 forms；CMP_RDY is set into height when it is low that Latch output signal DP, DN are any.
EOC pulse-generating circuit 105 is by the standard block latch 1012 with reset switch, phase inverter 1013 and pull-up
Power supply composition；It is CMP_RDY and sampling clock CKS that it, which is inputted, and the pulse width for generating EOC is proportional to CMP_RDY rising edge and arrives
The interval of CKS rising edge.Standard block latch 1012 with reset switch can realize by any circuit structure latch, only
Latch and the realization of reset function need to be met.
Pulsewidth current converter circuit 106 is by RC filter 1014~1015, voltage amplifier 1016, power supply divider resistance
1017~1018 and PMOS circuit output stage 1019 forms；The pulsewidth of ECO signal is converted into DC level by filtering, and by its
With the grid for acting on PMOS1019 after the difference amplification of 1017~1018 output level of power supply divider resistance, PMOS1019 drain electrode
Output size of current inverse ratio and eoc signal pulsewidth.
Latch clock generation circuit 107 is made of three input nor gates 1020 and clock buffer 1021；
Nor gate input is CKS, EOC and CMP_RDY, exports CK_LAT by buffer.Latch clock CK_LAT's
Rising edge is obtained by the failing edge of sampling clock CKS by the time delay of nor gate 1020 and buffer 1021；The decline of CK_LAT
It is obtained along the rising edge by CMP_RDY by nor gate 1020 and the time delay of buffer 1021, which is proportional to pulsewidth electric current
The output electric current of conversion circuit 106.
Traditional dynamic comparer fixed allocation sampling, amplification and the time latched.In order to cope with technique, supply voltage,
The variation of operating temperature needs to retain biggish time margin in each section, to limit the highest work frequency of comparator itself
Rate.In order to solve this problem, the invention proposes the dynamic comparers of self-adaptive time sequence as shown in Figure 1.In addition to conventional dynamic
Except sampling hold circuit contained by comparator, prime amplifier, latch, eoc signal is further comprised in structure of the present invention
Pulsewidth locks feedback network 103.This partial circuit by latch output detection circuit 104 monitor latch 102 output DP,
DN judges comparator output when wherein any one signal is low effectively, output signal CMP_RDY is set height.CMP_RDY
Signal is sent to the nor gate input terminal of latch clock generation circuit 107, directly outputs it CK_LAT and drags down.CMP_ simultaneously
RDY and sampling clock CKS is sent to EOC pulsewidth generation circuit 105, output pulse signal EOC, and width represents comparator completion
Waiting time after once comparing.EOC pulse width is converted into latch clock by pulsewidth current converter circuit 106 and generates electricity
The size of the pull-up current of nor gate in road 107 controls the delay of CK_LAT rising edge by it.Latch clock generation circuit
107 draw high signal CK_LAT in sampling clock CKS failing edge, and be delayed the size of current control converted by eoc signal width
System；CK_LAT is dragged down in the rising edge of CMP_RDY, while output signal DP, DN of comparator is set into height.Fig. 2 is shown one
In a clock cycle, the working sequence of comparator modules represents the sampling time with Ts respectively in figure, and Ta represents pre-amplification
The settling time of device 101, Tl represent the working time of latch 102, it comprises latch output drag down the time required to t1 and
Time delay t2 and t3, Te as caused by latch clock generative circuit 107 and output effective detection circuit 104 represent eoc signal
Width, T represents the total time of one complete cycle of comparator.With according to equation Te=T-Ts-Ta-Tl, Te by loop-locking,
The value of Te/T divides resulting reference voltage VR by power supply and determines.At this point, Tl and Ta's and fixed, when latch 102 works
Between Tl it is shorter when, the output settling time Ta of sampling hold circuit 100 and prime amplifier 101 can be elongated, and vice versa.The characteristic
Institute's having time in each complete comparator duty cycle is effectively utilized, is conducive to the highest work frequency for improving comparator
Rate.
The dynamic comparer of self-adaptive time sequence proposed by the present invention, eoc signal pulsewidth lock feedback network way of realization
It is not limited to being converted to pulse width signal into the mode that current signal carrys out delay of control.It is any by signal pulse width conversion delays time to control
The circuit form of signal can be used in circuit structure proposed by the invention.
Claims (10)
1. a kind of dynamic comparer of self-adaptive time sequence, which is characterized in that including input sample holding circuit (100), pre-amplification
Device (101), output latch (102) and convert signal pulsewidth locking feedback network (103)；Wherein
Converting signal pulsewidth locking feedback network (103) includes that latch exports effective detection circuit (104), converts
Pulsewidth generation circuit (105), pulsewidth current converter circuit (106) and latch clock generation circuit (107)；
The input terminal that latch exports effective detection circuit (104) is electrically connected with the output end of output latch (102), latch
Export the output end of effective detection circuit (104) respectively with convert pulsewidth generation circuit (105) and latch clock generates
The input terminal of circuit (107) is electrically connected；
Convert the output end of pulsewidth generation circuit (105) respectively with pulsewidth current converter circuit (106) and latch clock
The input terminal of generation circuit (107) is electrically connected；
The output end of pulsewidth current converter circuit (106) is electrically connected with latch clock generation circuit (107)；
The output end of latch clock generation circuit (107) respectively with output latch (102) and the effective detection circuit of output
(104) input terminal electrical connection.
2. the dynamic comparer of self-adaptive time sequence according to claim 1, which is characterized in that latch output effectively detection
Circuit (104) includes:
NAND gate (1011), the output end DP and output end DN of output latch (102) input with NAND gate (1011) respectively
End electrical connection, the output end of NAND gate (1011) respectively with convert pulsewidth generation circuit (105) and latch clock generation
The input terminal of circuit (107) is electrically connected；
First phase inverter (1008), the input of the output end and the first phase inverter (1008) of latch clock generation circuit (107)
End electrical connection, the output end of the first phase inverter (1008) pass through the first latch output pull-up switch (1009) and the second lock respectively
Storage output pull-up switch (1010) is electrically connected with the input terminal of NAND gate (1011).
3. the dynamic comparer of self-adaptive time sequence according to claim 2, which is characterized in that convert pulsewidth and generate electricity
Road (105) includes:
The input terminal of second phase inverter (1013), the second phase inverter (1013) is electrically connected with sampling clock CKS；
Standard block latch (1012), the output of the RN pin and the second phase inverter (1013) of standard block latch (1012)
End electrical connection, the CK pin of standard block latch (1012) are electrically connected with the output end of NAND gate (1011), standard block lock
The D pin of storage (1012) is electrically connected with power vd D, and the Q pin of standard block latch (1012) turns with pulsewidth electric current respectively
Change the input terminal electrical connection of circuit (106) and latch clock generation circuit (107).
4. the dynamic comparer of self-adaptive time sequence according to claim 3, which is characterized in that pulsewidth current converter circuit
(106) include:
The Q pin of RC filter, standard block latch (1012) is electrically connected with the input terminal of RC filter；
The normal phase input end of voltage amplifier (1016), voltage amplifier (1016) is electrically connected with the output end of RC filter；
Component is divided, the one end for dividing component is electrically connected with RC filter, and the other end for dividing component is electrically connected with power vd D,
The inverting input terminal of voltage amplifier (1016) is electrically connected with partial pressure component；
The source electrode of PMOS circuit output stage (1019), PMOS circuit output stage (1019) is electrically connected with power vd D, and PMOS electric current is defeated
The grid of grade (1019) is electrically connected with the output end of voltage amplifier (1016) out, the drain electrode of PMOS circuit output stage (1019) with
Latch clock generation circuit (107) electrical connection.
5. the dynamic comparer of self-adaptive time sequence according to claim 4, which is characterized in that RC filter includes:
The Q pin of filter resistance (1014), standard block latch (1012) is electrically connected with one end of filter resistance (1014), electricity
The normal phase input end of pressure amplifier (1016) is electrically connected with the other end of filter resistance (1014)；
The anode of filter capacitor (1015), filter capacitor (1015) is electrically connected with the other end of filter resistance (1014), filtered electrical
Hold the cathode ground connection of (1015).
6. the dynamic comparer of self-adaptive time sequence according to claim 5, which is characterized in that dividing component includes:
First power supply divider resistance (1017), one end of the first power supply divider resistance (1017) and the cathode of filter capacitor (1015)
Electrical connection, the other end of the first power supply divider resistance (1017) are electrically connected with the inverting input terminal of voltage amplifier (1016)；
Second source divider resistance (1018), one end of second source divider resistance (1018) are anti-with voltage amplifier (1016)
The electrical connection of phase input terminal, the other end of second source divider resistance (1018) are electrically connected with power vd D.
7. the dynamic comparer of self-adaptive time sequence according to claim 6, which is characterized in that latch clock generation circuit
(107) include:
Three input nor gate (1020), three input nor gate (1020) three input terminals respectively with standard block latch
(1012) the output end electrical connection of Q pin, sampling clock CKS and NAND gate (1011), the drain electrode of circuit output stage (1019)
It is electrically connected with three inputs nor gate (1020)；
Clock buffer (1021), the input terminal of clock buffer (1021) and the output end of three inputs nor gate (1020) are electrically connected
It connects, the output end of clock buffer (1021) is electric with the input terminal of output latch (102) and the first phase inverter (1008) respectively
Connection.
8. the dynamic comparer of self-adaptive time sequence according to claim 1, which is characterized in that input sample holding circuit
(100) include:
First input module, the first input module connect input signal Vip and prime amplifier (101)；
Second input module, the second input module connect input signal Vin and prime amplifier (101)；
The both ends of backplane switch (1007), backplane switch (1007) are connect with the first input module and the second input module respectively.
9. the dynamic comparer of self-adaptive time sequence according to claim 8, which is characterized in that the first input module includes:
One end of first bottom plate sampling switch (1001), the first bottom plate sampling switch (1001) is electrically connected with input signal Vip；
The anode of first sampling capacitance (1005), the first sampling capacitance (1005) is another with the first bottom plate sampling switch (1001)
End electrical connection, the cathode of the first sampling capacitance (1005) are electrically connected with the first input end of prime amplifier (101)；
First top plate sampling switch (1003), the first top plate sampling switch (1003) are connected and fixed bias voltage VCM and pre-amplification
The first input end of device (101)；
One end of backplane switch (1007) is electrically connected with the other end of the first bottom plate sampling switch (1001).
10. the dynamic comparer of self-adaptive time sequence according to claim 9, which is characterized in that the second input module includes:
One end of second bottom plate sampling switch (1002), the second bottom plate sampling switch (1002) is electrically connected with input signal Vin；
The anode of second sampling capacitance (1006), the second sampling capacitance (1006) is another with the second bottom plate sampling switch (1002)
End electrical connection, the cathode of the second sampling capacitance (1006) are electrically connected with the second input terminal of prime amplifier (101)；
Second top plate sampling switch (1004), the second top plate sampling switch (1004) are connected and fixed bias voltage VCM and pre-amplification
Second input terminal of device (101)；
The other end of backplane switch (1007) is electrically connected with the other end of the second bottom plate sampling switch (1002).
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022242868A1 (en) | 2021-05-20 | 2022-11-24 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Apparatus comprising a comparator circuit |
| US11909401B2 (en) | 2019-10-11 | 2024-02-20 | University Of Washington | Input driven self-clocked dynamic comparator |
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Cited By (3)
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| US11909401B2 (en) | 2019-10-11 | 2024-02-20 | University Of Washington | Input driven self-clocked dynamic comparator |
| WO2022242868A1 (en) | 2021-05-20 | 2022-11-24 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Apparatus comprising a comparator circuit |
| DE112021007687T5 (en) | 2021-05-20 | 2024-03-07 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung eingetragener Verein | Device with a comparator circuit |
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