CN102820863B - Dual-threshold automatic gain control circuit applied to class D audio frequency amplifiers - Google Patents
Dual-threshold automatic gain control circuit applied to class D audio frequency amplifiers Download PDFInfo
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- CN102820863B CN102820863B CN201210333275.8A CN201210333275A CN102820863B CN 102820863 B CN102820863 B CN 102820863B CN 201210333275 A CN201210333275 A CN 201210333275A CN 102820863 B CN102820863 B CN 102820863B
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Abstract
The invention discloses a dual-threshold automatic gain control circuit applied to class D audio frequency amplifiers, mainly solving the problems of gain jitter and low output audio frequency quality in existing single-threshold peak detection. The control circuit comprises a programmable gain amplifier (1), a dual-threshold generating circuit (2), a dual-threshold peak detection module (3) and a feedback type gain control module (4), wherein the dual-threshold peak detection module is used for comparing the audio signal preliminarily amplified by the programmable gain amplifier with the threshold signal generated by the dual-threshold generating circuit and outputting a latch signal PD; the latch signal is used for controlling the feedback type gain control module to carry out logic judgment to output gain selection signals d23-d0; and the gain selection signals are used for controlling the programmable gain amplifier to up-regulate, down-regulate or maintain the gain as required. The control circuit disclosed by the invention effectively improves the audio output quality, realizes the accurate regulation of the gain and avoids the gain jitter.
Description
Technical field
The invention belongs to electronic circuit technology field, relate to analog integrated circuit, particularly a kind of Dual-threshold automatic gain control circuit for the obtained optimum gain in D audio frequency amplifier.
Background technology
Along with people are to the further investigation of audio-frequency power amplifier with continually develop, work in the D audio frequency amplifier of switching mode high with efficiency, the advantages such as distorted signals is little, instead of linear amplifier gradually, have captured audio frequency power amplifier market.Different from linear audio power amplifiers such as category-A, category-B and AB classes, D audio frequency amplifier is a digital audio amplifier working in switching mode, input audio signal after integral amplifier amplifies and carrier signal are compared, complete analog-to-digital conversion, obtain the pulse signal that a series of width is different, complete the conversion of audio frequency signal amplitude information to pulse width information.This pulse width information controls bridge-type load circuit works, and the output of bridge circuit completes digital-to-analogue conversion, the audio signal after being amplified after outside LC filter process.
But if for a certain reason, cause the excessive or carrier-signal amplitude of input audio signal amplitude to diminish, the output of integral amplifier can export direct current signal after analog-to-digital conversion.This direct current signal controls bridge circuit and is in unidirectional opening always, produces larger flip-flop, cause fatal damage to chip and loudspeaker load in bridge circuit and loudspeaker load.A generation that can suppress this flip-flop of visible design, can ensure that again the D audio frequency amplifier of overall output power level is imperative.
Fig. 1 gives traditional automatic gain control circuit control circuit, and its input signal is audio signal V
iN, this input signal, through the preliminary amplification of programmable amplifier circuit audio signal, outputs signal V
oUT; This output signal V
oUTbe an input signal of analog to digital converter in D audio frequency amplifier; Output signal V
oUTalso as an input signal of single threshold peak detection circuit, another input signal of single threshold peak detection circuit is threshold level V
rEF; The output of single threshold peak detection circuit connects gain control module, as its unique input signal; Comprehensive single threshold peak detection circuit in gain control module exports a series of GAIN SELECT signal, controls gain amplifier device able to programme and carries out gain-adjusted, export reset signal simultaneously, removes the information that single threshold peak detection circuit detects.
Fig. 2 gives the control procedure of the automatic gain control circuit traditional when input signal amplitude is excessive; As the amplitude peak V of output signal
oUT_MAX>V
rEFtime, single threshold peak detection circuit exports as low level signal, comprehensive single threshold peak detection circuit in gain control module this low level signal comprehensive exports new GAIN SELECT signal, after completing gain-adjusted, export a low level reset signal to single threshold peak detection block simultaneously, remove the amplitude information that single threshold peak detection circuit detects; New GAIN SELECT signal controls gain amplifier device able to programme on the basis of existing gain, reduces a step gain; As the amplitude peak V of output signal
oUT_MAX<V
rEFtime, single threshold peak detection circuit exports as high level signal, comprehensive single threshold peak detection circuit in gain control module this high level signal comprehensive exports new GAIN SELECT signal, after completing gain-adjusted, export a low level reset signal to single threshold peak detection block simultaneously, remove the amplitude information that single threshold peak detection circuit detects; New GAIN SELECT signal controls gain amplifier device able to programme increases by a step gain on the basis of existing gain.Because single threshold peak detection circuit only has a threshold voltage, like this in gain adjustment process, when the output amplitude peak of programmable gain amplifier is close to when pressing VREF with threshold level, there will be gain unavoidably and regulate i.e. gain jitter phenomenon back and forth in critical condition, cause distorted signals, have a strong impact on the audio quality that D audio frequency amplifier exports.
Summary of the invention
The object of the invention is to the deficiency for existing automatic gain control circuit, a kind of Dual-threshold automatic gain control circuit be applied in D audio frequency amplifier is proposed, to eliminate the gain jitter phenomenon occurred in gain adjustment process, improve the audio quality that D audio frequency amplifier exports.
For achieving the above object, the present invention includes for carrying out the preliminary programmable gain amplifier 1 amplified to input audio signal, it is characterized in that: also comprise dual threshold and produce circuit 2, dual threshold peak detection block 3 and reaction type gain control module 4;
Described dual threshold produces circuit 2 for generation of threshold voltage V
rEF1and V
rEF2, and be connected to dual threshold peak detection block 3, for it provides threshold voltage;
Described dual threshold peak detection block 3, is provided with 7 inputs u, e, f, g, h, k, s and 1 output m; The audio signal V of the input of its input u and programmable gain amplifier 1
oUTbe connected, for the detection of maximum signal amplitudes; The clock signal C K that its input e produces with D audio frequency amplifier inside is connected; Its input f and input g produces the threshold voltage V that circuit 2 inputs respectively with dual threshold
rEF1and V
rEF2be connected; Reset signal RSET, control signal CTRL1 that its input h, input k and input s input with reaction type gain control module 4 are respectively connected with control signal CTRL2; Its output m output latch signal PD, and be connected to reaction type gain control module 4, for it provides amplitude information;
Described reaction type gain control module 4, is provided with 1 input n, 4 outputs o, p, q, z; The latch signal PD that its input n inputs with dual threshold peak detection block 3 is connected; Its output o, output end p and output q, export reset signal RSET, control signal CTRL1 and control signal CTRL2 respectively, and be connected to dual threshold peak detection block 3; Its output z is connected to programmable gain amplifier 1; Reaction type gain control module 4 adopts logical decision to regulate the mode of gain to export and raises gain, lower gain and maintenance gain three class signal, and by this three classes signal controlling programmable gain amplifier 1, to realize the automatic adjustment of gain and to eliminate the jitter phenomenon of gain.
Above-mentioned Dual-threshold automatic gain control circuit, wherein dual threshold produce circuit 2, comprise error amplifier 201,202, current mirroring circuit 203,204, transistor M1 and resistance R0 ~ R4;
The grid of described transistor M1 is connected with the output of the first error amplifier 201; Its drain electrode is connected with the first end of the first current mirroring circuit 203; Its source electrode is connected with the first end of the second current mirroring circuit 204 by resistance R0;
The in-phase input end of described first error amplifier 201 connects the common mode electrical level V of D audio frequency amplifier inside generation
cM, its inverting input is connected to the common port of transistor M1 and resistance R0;
One end of described resistance R1 is connected with the second end of the first current mirroring circuit 203; Other end Series Sheet group R2, R3 and R4 of resistance R1 are to the second end of the second current mirroring circuit 204; The common port of resistance R1 and R2 produces the first output of circuit 2 as dual threshold, export threshold voltage V
rEF1; The common port of resistance R2 and R3 produces the second output of circuit 2 as dual threshold, export threshold voltage V
rEF2;
The inverting input of described second error amplifier 202 is connected with the output of self, component unit gain amplifying circuit; Its in-phase input end connects the common mode electrical level V that D audio frequency amplifier inside produces
cM; Its output is connected with the common port of resistance R3 with R4, for definite threshold voltage V
rEF1and V
rEF2common mode level.
Above-mentioned Dual-threshold automatic gain control circuit, wherein dual threshold peak detection block 3, comprise comparator 301,302, two input NOR gate 303,304,305 and latchs 306;
The in-phase input end of described first comparator 301 is connected with the in-phase input end of the second comparator 302, as the input u of dual threshold peak detection block 3, connects the audio signal V that programmable gain amplifier 1 inputs
oUT; The inverting input of the first comparator 301, as the input f of dual threshold peak detection block 3, connects the threshold voltage V that dual threshold produces circuit 2 input
rEF1; Its output exports comparison signal OV1, and is connected with two the second inputs inputting NOR gate 303;
The inverting input of described second comparator 302, as the input g of dual threshold peak detection block 3, connects the threshold voltage V that dual threshold produces circuit 2 input
rEF2; Its output exports comparison signal OV2, and is connected with two first input ends inputting NOR gate 304;
The first input end of described two input NOR gate 303, as the input k of dual threshold peak detection block 3, connects the control signal CTRL1 that reaction type gain control module 4 inputs; Its output is connected to the first input end of two input NOR gate 305;
Second input of described two input NOR gate 304, as the input s of dual threshold peak detection block 3, connects the control signal CTRL2 that reaction type gain control module 4 inputs; Its output is connected to the second input of two input NOR gate 305;
The data input pin of described latch 306 is connected with two outputs inputting NOR gate 305; Its input end of clock, as the input e of dual threshold peak detection block 3, connects the clock signal C K that D audio frequency amplifier inside produces, for the collection of data message; Its clear terminal, as the input h of dual threshold peak detection block 3, connects reset signal RST, for the removing of data message; Its output Q is as the output m of dual threshold peak detection block 3, and output latch signal PD, for providing the amplitude information detected.
Above-mentioned Dual-threshold automatic gain control circuit, wherein reaction type gain control module 4, comprise the first combinational logic circuit 41, second combinational logic circuit 42 and the 3rd combinational logic circuit 43;
Described first combinational logic circuit 41, the latch signal PD that its first input end inputs with dual threshold peak detection block 3 is connected; The reset signal RST2 that its second input inputs with the second combinational logic circuit 42 is connected, and resets for its internal counter; The clock signal C K that its 3rd input produces with D audio frequency amplifier inside is connected, for providing clock signal for its internal timer sum counter; This first combinational logic circuit 41 has 5 output signals, is respectively control signal T1, T3, PDB, reset signal RS T1 and GAIN SELECT signal d23 ~ d0; Wherein control signal T1, T3 and reset signal RS T1 are connected to the second combinational logic circuit 42, for generation of reset signal RSET and reset signal RST2; Output signal PDB is connected to the 3rd combinational logic circuit (43); GAIN SELECT signal d0 ~ d23 is as the output signal of the output z of reaction type gain control module 4;
Described second combinational logic circuit 42, control signal T1, T3 that its first input end, the second input and the 3rd input input with the first combinational logic circuit 41 are respectively connected with reset signal RS T1; The control signal CTRL1 that its four-input terminal and the 5th input input with the 3rd combinational logic circuit 43 is respectively connected with CTRL2; This second combinational logic circuit 42 has 4 output signals, is respectively reset signal RSET, RST2 and control signal A, B; Wherein reset signal RSET is as the output signal of reaction type gain control module 4 output o; Reset signal RST2 is connected to the first combinational logic circuit 41; Control signal A and control signal B are all connected with the 3rd combinational logic circuit 43;
Described 3rd combinational logic circuit 43, the latch signal PD that its first input end inputs with dual threshold peak detection block 3 is connected; Its second input and the 3rd input are connected with reset signal RS T1 with the latch signal PD of the input of the first combinational logic circuit 41 respectively; The control signal A that its four-input terminal and the 5th input input with the second combinational logic circuit 42 is respectively connected with control signal B; 3rd combinational logic circuit 43 has 2 output signals, is respectively control signal CTRL1 and control signal CTRL2; The output end p of these two control signals respectively as reaction type gain control module 4 and the output signal of output q.
Above-mentioned Dual-threshold automatic gain control circuit, wherein the first combinational logic circuit 41, comprise not gate 501, three and input NOR gate 502,503, timer 504,505, two input or door 506, forward-backward counter 507 and 5-32 decoder 508;
Described not gate 501, its input connects the latch signal PD that dual threshold peak detection block 3 inputs; Its output exports control signal PDB;
Described three input NOR gate 502, its first input end connection control signal PDB; Its second input connects reset signal RST1; Its 3rd input connects the reset signal RST2 that the second combinational logic circuit 42 inputs; Its output is connected with the second input of timer 504, as the enable signal of timer 504;
Described three input NOR gate 503, its first input end connects reset signal RST1; Its second input connects the reset signal RST2 that the second combinational logic circuit 42 inputs; Its 3rd input connects the latch signal PD that dual threshold peak detection block 3 inputs; Its output is connected with the second input of timer 505, as the enable signal of timer 505;
Described timer 504, its first input end is connected with external timing signal CK; Its first output exports control signal T1; Its second output exports control signal T2, and inputs with two or the first input end of door 506 is connected;
Described timer 505, its first input end is connected with external timing signal CK; Its first output exports control signal T4, and inputs with two or the second input of door 506 is connected; Its second output exports control signal T3;
Described two input or doors 506, its output exports reset signal RST1, and is connected to the 3rd input of forward-backward counter 507, as the clock signal of forward-backward counter 507;
Described forward-backward counter 507, the latch signal PD that its first input end and the second input input with dual threshold peak detection block 3 is respectively connected with control PDB, is in and adds count status for controlling forward-backward counter or subtract count status; Forward-backward counter 507 exports five count signal q
4~ q
0, as the data input signal of 5-32 decoder 508;
Described 5-32 decoder 508, it exports 24 GAIN SELECT signal d23 ~ d0, as the output signal of reaction type gain control module 4 output z, for the selection of gain level.
Above-mentioned Dual-threshold automatic gain control circuit, wherein the second combinational logic circuit 42, comprise two input nand gates 601,602,603 and two and input NOR gate 604;
Described two input nand gates 601, its first input end connects the control signal T3 that the first combinational logic circuit 41 inputs; Its second input connects the control signal CTRL2 that the 3rd combinational logic circuit 43 inputs; Its output output signal A, and be connected with the first input end of two input nand gates 603;
Described two input nand gates 602, its first input end connects the control signal T1 that the first combinational logic circuit 41 inputs, and its second input connects the control signal CTRL1 that the 3rd combinational logic circuit 43 inputs; Its output output signal B, and be connected with the second input of two input nand gates 603;
The output of described two input nand gates 603 exports reset signal RST2, and is connected with two the second inputs inputting NOR gate 604;
Described two input NOR gate 604, the reset signal RS T1 that its first input connection first combinational logic circuit 41 inputs; Its output exports reset signal RSET, as the output signal of reaction type gain control module 4 output o.
Above-mentioned Dual-threshold automatic gain control circuit, wherein the 3rd combinational logic circuit 43, comprise two input nand gates 701,702, two and input and door 703,704 and rest-set flip-flop 705;
Described two input nand gates 701, its first input end connects the latch signal PD that dual threshold peak detection block 3 inputs; The reset signal RS T1 that its second input inputs with the first combinational logic circuit 41 is connected; Its output and two inputs and is connected with the first input end of door 703;
Described two inputs and door 702, the reset signal RST1 that its first input end and the second input input with the first combinational logic circuit 41 is respectively connected with control signal PDB; Its output and two inputs and is connected with the first input end of door 704;
Described two inputs and door 703, its second input connects the control signal A that the second combinational logic circuit 42 inputs; Its output is held with the R of rest-set flip-flop 705 and is connected;
Described two inputs and door 704, its second input connects the control signal B that the second combinational logic circuit 42 inputs; Its output is held with the S of rest-set flip-flop 705 and is connected;
Two outputs of described rest-set flip-flop 705 are respectively as the output end p of reaction type gain control module 4 and output q, and export control signal CTRL1 and CTRL2 to control dual threshold peak detection block 3, carry out cycle detection for controlling dual threshold peak detection block 3 pairs of peak value sizes.
The present invention compared with prior art has the following advantages:
(1) the present invention is owing to the addition of a dual threshold peak detection block, by the audio output signal of amplifier and dual threshold being produced the threshold voltage V that circuit produces
rEF1and V
rEF2compare, define the amplification level of audio output signal accurately.
(2) the present invention forms cycle detection loop by programmable gain amplifier, dual threshold peak detection block and reaction type gain control module, dynamically detect the peak value size of audio signal, not only achieve the accurate adjustment of programmable gain amplifier gain, and avoid the generation of gain jitter, improve the quality that audio frequency exports.
Accompanying drawing explanation
Fig. 1 is traditional automatic gain control circuit;
Fig. 2 is the Drazin inverse oscillogram of traditional automatic gain control circuit;
Fig. 3 is the structured flowchart of control circuit of the present invention;
Fig. 4 is the circuit theory diagrams that in the present invention, dual threshold produces circuit;
Fig. 5 is the circuit theory diagrams of dual threshold peak detection block in the present invention;
Fig. 6 is the structured flowchart of reaction type gain control module in the present invention;
Fig. 7 is the circuit theory diagrams of reaction type gain control module in the present invention;
Fig. 8 is the output waveform figure of timing under gain of the present invention;
Fig. 9 is the output waveform figure of timing in gain of the present invention.
Embodiment
Below in conjunction with accompanying drawing and embodiment, the invention will be further described.
With reference to Fig. 3, Dual-threshold automatic gain control circuit of the present invention, comprises programmable gain amplifier 1, and dual threshold produces circuit 2, dual threshold peak detection block 3 and reaction type gain control module 4;
Described programmable gain amplifier 1, is provided with 3 inputs a, b, c and 1 output d; Its input a connects external audio input signal V
iN; Its input b is connected with reaction type gain control module 4; Its input c connects the common-mode signal V that D audio frequency amplifier inside produces
cM; Its output d exports the audio signal V after amplifying
oUT, and connect analog to digital converter and the dual threshold peak detection block 3 of D audio frequency amplifier inside, for completing the conversion of analog signal to digital signal and the detection of maximal audio amplitude output signal;
Described dual threshold produces circuit 2, and its input connects the common-mode signal V that D audio frequency amplifier inside produces
cM; Its output exports threshold voltage V
rEF1and V
rEF2, and be connected to dual threshold peak detection block 3, for it provides threshold voltage;
Described dual threshold peak detection block 3, is provided with 7 inputs u, e, f, g, h, k, s and 1 output m; The audio signal V of the input of its input u and programmable gain amplifier 1
oUTbe connected, for the detection of maximum signal amplitudes; The clock signal C K that its input e produces with D audio frequency amplifier inside is connected; Its input f and input g produces the threshold voltage V that circuit 2 inputs respectively with dual threshold
rEF1and V
rEF2be connected; Reset signal RSET, control signal CTRL1 that its input h, input k and input s input with reaction type gain control module 4 are respectively connected with control signal CTRL2; Its output m output latch signal PD, and be connected to reaction type gain control module 4, for it provides amplitude information;
Described reaction type gain control module 4; Be provided with 1 input n, 4 outputs o, p, q, z; The latch signal PD that its input n inputs with dual threshold peak detection block 3 is connected; Its output o, output end p and output q, export reset signal RSET, control signal CTRL1 and control signal CTRL2 respectively, and be connected to dual threshold peak detection block 3; Its output z is connected to programmable gain amplifier 1; Reaction type gain control module 4 adopts logical decision to regulate the mode of gain to export and raises gain, lower gain and maintenance gain three class signal, and by this three classes signal controlling programmable gain amplifier 1, to realize the automatic adjustment of gain and to eliminate the jitter phenomenon of gain.
Dual-threshold automatic gain control circuit of the present invention needs to be provided with following three kinds of different operating state: I according to difference) for the excessive operating state needed when lowering gain of input audio signal, II) do not need operating state when regulating gain and III for input audio signal is moderate) for operating state when the too small needs of input audio signal regulating gain; Its specific works principle is described below respectively:
I) for input audio signal excessive need lower gain time operating state operation principle be:
The audio signal inputted when programmable gain amplifier 1 meets V
oUT>V
rEF1>V
rEF2, and the control signal CTRL1=0 that reaction type gain control module 4 exports, during CTRL2=1, the latch signal PD=1 that dual threshold peak detection block 3 exports; The forward-backward counter of reaction type gain control module 4 inside is in and adds count status, and now reaction type gain control module 4 internal counter generation counting clock control forward-backward counter completes and once adds counting, and output gain selects signal d
23~ d
0control programmable gain amplifier 1 gain and lower a step; Simultaneously, reaction type gain control module 4 exports reset signal RSET=0, remove the latch information of dual threshold peak detection block 3, carry out new amplitude detection process, and reaction type gain control module 4 exports control signal CTRL1=1, CTRL2=0, makes dual threshold peak detection block 3 output latch signal PD=1; The forward-backward counter of reaction type gain control module 4 inside is in and adds count status, and now the counter of reaction type gain control module 4 inside does not produce counting clock, therefore its GAIN SELECT signal d exported
23~ d
0keep standing state, the gain of programmable gain amplifier 1 remains unchanged; Meanwhile, reaction type gain control module 4 exports reset signal RSET=0, removes the latch information of dual threshold peak detection block 3, carry out new amplitude detection process, and reaction type gain control module 4 exports control signal CTRL1=0, CTRL2=1.Fig. 8 gives the output waveform figure of timing under gain of the present invention, as can be seen from Figure 8, if the audio signal Vout that programmable gain amplifier 1 inputs continues excessive, i.e. and V
oUT>V
rEF1>V
rEF2time, then said process circulation, every circulation primary, current gain value Gain_now lowers a step, until the audio signal that programmable gain amplifier 1 inputs meets V
rEF1>V
oUT>V
rEF2, circulation stops, and now yield value is optimum gain value Gain_best.
II) for input audio signal moderate do not need regulate gain time operating state operation principle be:
The audio signal inputted when programmable gain amplifier 1 meets V
rEF1>V
oUT>V
rEF2, and the control signal CTR L1=0 that reaction type gain control module 4 exports, during CTRL2=1, the latch signal PD=0 that dual threshold peak detection block 3 exports; The forward-backward counter of reaction type gain control module 4 inside is in and subtracts count status, and now the counter of reaction type gain control module 4 inside does not produce counting clock, therefore its GAIN SELECT signal d exported
23~ d
0keep standing state, the gain of programmable gain amplifier 1 remains unchanged; Simultaneously, reaction type gain control module 4 exports reset signal RSET=0, remove the latch information of dual threshold peak detection block 3, carry out new amplitude detection process, and reaction type gain control module 4 exports control signal CTRL1=1, CTRL2=0, makes dual threshold peak detection block 3 output latch signal PD=1; The forward-backward counter of reaction type gain control module 4 inside is in and adds count status, and now the counter of reaction type gain control module 4 inside does not also produce counting clock, therefore its GAIN SELECT signal d exported
23~ d
0keep standing state, the gain of programmable gain amplifier 1 still remains unchanged; Meanwhile, reaction type gain control module 4 exports reset signal RSET=0, removes the latch information of dual threshold peak detection block 3, carry out new amplitude detection process, and reaction type gain control module 4 exports control signal CTRL1=0, CTRL2=1.If programmable gain amplifier 1 input audio signal continues moderate, i.e. V
rEF1>V
oUT>V
rEF2, then said process circulation, the gain of programmable gain amplifier 1 remains unchanged.
III) for the operation principle of operating state when the too small needs of input audio signal regulating gain:
The audio signal inputted when programmable gain amplifier 1 meets V
oUT<V
rEF1<V
rEF2, and the control signal CTRL1=0 that reaction type gain control module 4 exports, during CTRL2=1, the latch signal PD=0 that dual threshold peak detection block 3 exports; The forward-backward counter of reaction type gain control module 4 inside is in and subtracts count status, and now the counter of reaction type gain control module 4 inside does not produce counting clock, therefore its GAIN SELECT signal d exported
23~ d
0keep standing state, the gain of programmable gain amplifier 1 remains unchanged; Simultaneously, reaction type gain control module 4 exports reset signal RSET=0, remove the latch information of dual threshold peak detection block 3, carry out new amplitude detection process, and reaction type gain control module 4 exports control signal CTRL1=1, CTRL2=0, makes dual threshold peak detection block 3 output latch signal PD=0; The forward-backward counter of reaction type gain control module 4 inside is in and subtracts count status, and now reaction type gain control module 4 internal counter generation counting clock control forward-backward counter completes and once subtracts counting, and output gain selects signal d
23~ d
0control programmable gain amplifier 1 gain and raise a step; Meanwhile, reaction type gain control module 4 exports reset signal RSET=0, removes the latch information of dual threshold peak detection block 3, carry out new amplitude detection process, and reaction type gain control module 4 exports control signal CTRL1=0, CTRL2=1.Fig. 9 gives the output waveform figure of timing in gain of the present invention, as can be seen from Figure 9, if the audio signal Vout that programmable gain amplifier 1 inputs continues too small, i.e. and V
oUT<V
rEF1<V
rEF2time, then said process circulation, every circulation primary, current gain value Gain_now raises a step, until the audio signal that programmable gain amplifier 1 inputs meets V
rEF1>V
oUT>V
rEF2, circulation stops, and now yield value is optimum gain value Gain_best.
With reference to Fig. 4, dual threshold of the present invention produces circuit 2, comprises error amplifier 201,202, current mirroring circuit 203,204, transistor M1 and resistance R0 ~ R4;
Described transistor M1, its grid is connected with the output of the first error amplifier 201; Its drain electrode is connected with the first end of the first current mirroring circuit 203; Its source electrode is connected with the first end of the second current mirroring circuit 204 by resistance R0;
The in-phase input end of described first error amplifier 201 connects the common mode electrical level V of D audio frequency amplifier inside generation
cM, its inverting input is connected to the common port of transistor M1 and resistance R0, forms negative feedback with transistor M1, ensures that the size of current flowing through resistance R0 is constant;
One end of described resistance R1 is connected with the second end of the first current mirroring circuit 203, and the other end Series Sheet group resistance R2, R3 and R4 of resistance R1, to the second end of the second current mirroring circuit 204, for electric resistance partial pressure, produce threshold voltage; The common port of resistance R1 and R2 produces the first output of circuit 2 as dual threshold, export threshold voltage V
rEF1; The common port of resistance R2 and R3 produces the second output of circuit 2 as dual threshold, export threshold voltage V
rEF2;
The inverting input of described second error amplifier 202 is connected with the output of self, component unit gain amplifying circuit; Its in-phase input end connects the common mode electrical level V that D audio frequency amplifier inside produces
cM; Its output is connected with the common port of resistance R3 with R4, ensures that the common port voltage of resistance R3 and R4 equals V all the time
cM, thus definite threshold voltage V
rEF1and V
rEF2common mode level.
With reference to Fig. 5, dual threshold peak detection block 3 of the present invention, comprises comparator 301,302, two input NOR gate 303,304,305 and latchs 306;
The in-phase input end of described first comparator 301 is connected with the in-phase input end of the second comparator 302, as the input u of dual threshold peak detection block 3, connects the audio signal V that programmable gain amplifier 1 inputs
oUT; The inverting input of the first comparator 301, as the input f of dual threshold peak detection block 3, connects the threshold voltage V that dual threshold produces circuit 2 input
rEF1; Its output exports comparison signal OV1, and is connected, for detecting audio signal V with two the second inputs inputting NOR gate 303
oUTwhether exceed threshold voltage V
rEF1, to determine whether to need to control reaction type gain control module 4 Drazin inverse gain signal;
The inverting input of described second comparator 302, as the input g of dual threshold peak detection block 3, connects the threshold voltage V that dual threshold produces circuit 2 input
rEF2; Its output exports comparison signal OV2, and is connected with two first input ends inputting NOR gate 304, for detecting audio signal V
oUTwhether exceed threshold voltage V
rEF2, to determine whether to need to control reaction type gain control module 4 Drazin inverse gain signal;
The first input end of described two input NOR gate 303, as the input k of dual threshold peak detection block 3, connects the control signal CTRL1 that reaction type gain control module 4 inputs; Its output is connected to the first input end of two input NOR gate 305;
Second input of described two input NOR gate 304, as the input s of dual threshold peak detection block 3, connects the control signal CTRL2 that reaction type gain control module 4 inputs; Its output is connected to the second input of two input NOR gate 305;
The data input pin of described latch 306 is connected with two outputs inputting NOR gate 305; Its input end of clock, as the input e of dual threshold peak detection block 3, connects the clock signal C K that D audio frequency amplifier inside produces, for the collection of data message; Its clear terminal, as the input h of dual threshold peak detection block 3, connects reset signal RST, for the removing of data message; Its output Q is as the output m of dual threshold peak detection block 3, and output latch signal PD, for providing the amplitude information detected;
As the audio signal V that programmable gain amplifier 1 inputs
oUT>V
rEF1>V
rEF2, and the control signal CTRL1=0 that reaction type gain control module 4 exports, during CTRL2=1, the latch signal PD=1 that dual threshold peak detection block 3 exports; As the audio signal V that programmable gain amplifier 1 inputs
oUT>V
rEF1>V
rEF2, and the control signal CTRL1=1 that reaction type gain control module 4 exports, during CTRL2=0, the latch signal PD=1 that dual threshold peak detection block 3 exports; As the audio signal V that programmable gain amplifier 1 inputs
rEF1>V
oUT>V
rEF2, and the control signal CTRL1=0 that reaction type gain control module 4 exports, during CTRL2=1, the latch signal PD=0 that dual threshold peak detection block 3 exports; As the audio signal V that programmable gain amplifier 1 inputs
rEF1>V
oUT>V
rEF2, and the control signal CTRL1=1 that reaction type gain control module 4 exports, during CTRL2=0, the latch signal PD=1 that dual threshold peak detection block 3 exports; As the audio signal V that programmable gain amplifier 1 inputs
oUT<V
rEF2<V
rEF1, and the control signal CTRL1=0 that reaction type gain control module 4 exports, during CTRL2=1, the latch signal PD=0 that dual threshold peak detection block 3 exports; As the audio signal V that programmable gain amplifier 1 inputs
oUT<V
rEF2<V
rEF1, and the control signal CTRL1=1 that reaction type gain control module 4 exports, during CTRL2=0, the latch signal PD=0 that dual threshold peak detection block 3 exports;
With reference to Fig. 6 and Fig. 7, the reaction type gain control module 4 in the present invention, comprises the first combinational logic circuit 41, second combinational logic circuit 42 and the 3rd combinational logic circuit 43;
The first above-mentioned combinational logic circuit 41, comprises not gate 501, three input NOR gate 502,503, timer 504,505, two input or doors 506, forward-backward counter 507 and 5-32 decoder 508;
The input of described not gate 501 connects the latch signal PD of dual threshold peak detection block 3 input; Its output exports control signal PDB;
The first input end connection control signal PDB of described three input NOR gate 502; Its second input connects reset signal RST1; Its 3rd input connects the reset signal RST2 that the second combinational logic circuit 42 inputs; Its output is connected with the second input of timer 504, as the enable signal of timer 504;
The first input end of described three input NOR gate 503 connects reset signal RST1; Its second input connects the reset signal RST2 that the second combinational logic circuit 42 inputs; Its 3rd input connects the latch signal PD that dual threshold peak detection block 3 inputs; Its output is connected with the second input of timer 505, as the enable signal of timer 505;
The first input end of described timer 504 is connected with external timing signal CK; Its first output exports control signal T1; Its second output exports control signal T2, and inputs with two or the first input end of door 506 is connected;
The first input end of described timer 505 is connected with external timing signal CK; Its first output exports control signal T4, and inputs with two or the second input of door 506 is connected; Its second output exports control signal T3;
The output of described two inputs or door 506 exports reset signal RST1, and is connected to the 3rd input of forward-backward counter 507, as the clock signal of forward-backward counter 507;
The latch signal PD that first input end and second input of described forward-backward counter 507 input with dual threshold peak detection block 3 is respectively connected with control PDB, is in and adds count status for controlling forward-backward counter or subtract count status; Forward-backward counter 507 exports five count signal q
4~ q
0, as the data input signal of 5-32 decoder (508);
Described 5-32 decoder 508 export 24 GAIN SELECT signal d23 ~ d0(design in only by front 24 output signals of 5-32 decoder), and the output signal of output z as reaction type gain control module 4, for the selection of gain level.
As the latch signal PD=1 that dual threshold peak detection block 3 exports, and the 3rd logic combination circuit 43 exports control signal CTRL1=0, and during CTRL2=1, timer 505 is in cleared condition, exports T3=T4=0; Due to PDB=0, RS T1=0, RST2=0, therefore counter 504 is in time status; Due to PD=1, PDB=0, therefore forward-backward counter 507 is in and adds count status; As the output control signal T2=1 of timer 504, two inputs or door 506 export counting clock, and triggering forward-backward counter 507 completes and once adds counting, and the output gain of 5-32 decoder 508 selects signal d
23~ d
0, control programmable gain amplifier 1 gain and lower a step;
As the latch signal PD=1 that dual threshold peak detection block 3 exports, and the 3rd logic combination circuit 43 exports control signal CTRL1=1, and during CTRL2=0, timer 505 is in cleared condition, exports T3=T4=0; Due to PDB=0, RS T1=0, RST2=0, therefore counter 504 is in time status; Due to PD=1, PDB=0, therefore forward-backward counter 507 is in and adds count status; As the output control signal T1=1 of timer 504, control the second logic combination circuit 42 and the 3rd logic combination circuit 43 exports reset signal RST2, and complete the State Transferring of control signal CTRL1, CTRL2, i.e. CTRL1=0, CTRL2=1; This reset signal RST2 control signal T2=0, two inputs or door 506 do not export counting clock, and the output of forward-backward counter 507 and 5-32 decoder 508 all remains unchanged, thus it is constant to control programmable gain amplifier 1 gain;
As the latch signal PD=0 that dual threshold peak detection block 3 exports, and the 3rd logic combination circuit 43 exports control signal CTRL1=0, during CTRL2=1, and PDB=1, timer 504 is in cleared condition, exports T1=T2=0; Due to RST1=0, RST2=0, therefore counter 505 is in time status; Due to PD=0, PDB=1, therefore forward-backward counter 507 is in and subtracts count status; As the output control signal T3=1 of timer 505, control the second logic combination circuit 42 and the 3rd logic combination circuit 43 exports reset signal RST2, and complete the State Transferring of control signal CTRL1, CTRL2, i.e. CTRL1=1, CTRL2=0; This reset signal RST2 control signal T4=0, two inputs or door 506 do not export counting clock, and the output of forward-backward counter 507 and 5-32 decoder 508 all remains unchanged, thus it is constant to control programmable gain amplifier 1 gain;
As the latch signal PD=0 that dual threshold peak detection block 3 exports, and the 3rd logic combination circuit 43 exports control signal CTRL1=1, during CTRL2=0, and PDB=1, timer 504 is in cleared condition, exports T1=T2=0; Due to RST1=0, RST2=0, therefore counter 505 is in time status; Due to PD=0, PDB=1, therefore forward-backward counter 507 is in and subtracts count status; As the output control signal T4=1 of timer 505, two inputs or door 506 export counting clock, and triggering forward-backward counter 507 completes and once subtracts counting, and the output gain of 5-32 decoder 508 selects signal d
23~ d
0, control programmable gain amplifier 1 gain and raise a step;
Above-mentioned second combinational logic circuit 42, comprises two input nand gates 601,602,603 and two and inputs NOR gate 604;
The first input end of described two input nand gates 601 connects the control signal T3 of the first combinational logic circuit 41 input; Its second input connects the control signal CTRL2 that the 3rd combinational logic circuit 43 inputs; Its output output signal A, and be connected with the first input end of two input nand gates 603;
The first input end of described two input nand gates 602 connects the control signal T1 of the first combinational logic circuit 41 input, and its second input connects the control signal CTRL1 that the 3rd combinational logic circuit 43 inputs; Its output output signal B, and be connected with the second input of two input nand gates 603;
The output of described two input nand gates 603 exports reset signal RST2, and is connected with two the second inputs inputting NOR gate 604;
The reset signal RS T1 of the first input connection first combinational logic circuit 41 input of described two input NOR gate 604; Its output exports reset signal RSET, and as the output signal of reaction type gain control module 4 output o.
This second combinational logic circuit 42 has 4 output signals, is respectively reset signal RSET, RST2 and control signal A, B; Wherein reset signal RSET is as the output signal of reaction type gain control module 4 output o, and is connected to dual threshold peak detection block 3, for removing the latch information of dual threshold peak detection block 3, carries out new amplitude detection process; Reset signal RST2 is connected to the first combinational logic circuit 41, as the reset signal of the first combinational logic circuit 41 Counter; Control signal A and control signal B is all connected to the 3rd combinational logic circuit 43, and control the 3rd combinational logic circuit 43 exports control signal and carries out State Transferring.
The 3rd above-mentioned combinational logic circuit 43, comprises two input nand gates 701,702, two and inputs and door 703,704 and rest-set flip-flop 705;
The first input end of described two input nand gates 701 connects the latch signal PD of dual threshold peak detection block 3 input; The reset signal RST1 that its second input inputs with the first combinational logic circuit 41 is connected; Its output and two inputs and is connected with the first input end of door 703;
Described two inputs are connected with control signal PDB with the reset signal RS T1 that the second input inputs with the first combinational logic circuit 41 respectively with the first input end of door 702; Its output and two inputs and is connected with the first input end of door 704;
Described two inputs are connected the control signal A that the second combinational logic circuit 42 inputs with the second input of door 703; Its output is held with the R of rest-set flip-flop 705 and is connected;
Described two inputs are connected the control signal B that the second combinational logic circuit 42 inputs with the second input of door 704; Its output is held with the S of rest-set flip-flop 705 and is connected;
Two outputs of described rest-set flip-flop 705 are respectively as the output end p of reaction type gain control module 4 and output q, and export control signal CTRL1 and CTRL2 to control dual threshold peak detection block 3, carry out cycle detection for controlling dual threshold peak detection block 3 pairs of peak value sizes.
Below be only a preferred example of the present invention, do not form any limitation of the invention, obviously under design of the present invention, different changes and improvement can be carried out to its circuit, but these are all at the row of protection of the present invention.
Claims (7)
1. one kind is applied to the Dual-threshold automatic gain control circuit in D audio frequency amplifier, comprise for carrying out the preliminary programmable gain amplifier (1) amplified to input audio signal, it is characterized in that: also comprise dual threshold and produce circuit (2), dual threshold peak detection block (3) and reaction type gain control module (4);
Described dual threshold produces circuit (2) for generation of threshold voltage V
rEF1and V
rEF2, and be connected to dual threshold peak detection block (3), for it provides threshold voltage;
Described dual threshold peak detection block (3), is provided with 7 inputs u, e, f, g, h, k, s and 1 output m; The audio signal V of the input of its input u and programmable gain amplifier (1)
oUTbe connected, for the detection of maximum signal amplitudes; Its input f and dual threshold produce the threshold voltage V that circuit (2) inputs
rEF1be connected; Its input g and dual threshold produce the threshold voltage V that circuit (2) inputs
rEF2be connected; The reset signal RSET that its input h inputs with reaction type gain control module (4) is connected; The control signal CTRL1 that its input k inputs with reaction type gain control module (4) is connected; The control signal CTRL2 that its output s inputs with reaction type gain control module (4) is connected; Its output m output latch signal PD, and be connected to reaction type gain control module (4), for it provides amplitude information;
Described reaction type gain control module (4), is provided with 1 input n, 4 outputs o, p, q, z; The latch signal PD that its input n inputs with dual threshold peak detection block (3) is connected; Its output o exports reset signal RSET; Output end p exports control signal CTRL1; Output q exports control signal CTRL2; Its output z is connected to programmable gain amplifier (1); Reaction type gain control module (4) adopts logical decision to regulate the mode of gain to export and raises gain, lower gain and maintenance gain three class signal, and by this three classes signal controlling programmable gain amplifier (1), to realize the automatic adjustment of gain and to eliminate the jitter phenomenon of gain; The audio signal inputted when programmable gain amplifier (1) meets V
oUT>V
rEF1>V
rEF2time, a step is lowered in programmable gain amplifier (1) gain, if audio signal V
oUTcontinue excessive, i.e. V
oUT>V
rEF1>V
rEF2time, then process circulation is lowered in above-mentioned gain, and every circulation primary, current gain value lowers a step, until the audio signal that programmable gain amplifier (1) inputs meets V
rEF1>V
oUT>V
rEF2time, circulation stops; The audio signal inputted when programmable gain amplifier (1) meets V
rEF1>V
oUT>V
rEF2time, the gain of programmable gain amplifier (1) remains unchanged, if programmable gain amplifier (1) input audio signal continues moderate, i.e. and V
rEF1>V
oUT>V
rEF2, then said process circulation, the gain of programmable gain amplifier (1) remains unchanged; The audio signal inputted when programmable gain amplifier (1) meets V
oUT<V
rEF1<V
rEF2time, a step is raised in programmable gain amplifier (1) gain, if the audio signal V that programmable gain amplifier (1) inputs
oUTcontinue too small, i.e. V
oUT<V
rEF1<V
rEF2time, then process circulation is raised in above-mentioned gain, and every circulation primary, current gain value raises a step, until the audio signal that programmable gain amplifier (1) inputs meets V
rEF1>V
oUT>V
rEF2, circulation stops.
2. Dual-threshold automatic gain control circuit according to claim 1, it is characterized in that dual threshold produces circuit (2), comprise the first error amplifier (201), the second error amplifier (202), the first current mirroring circuit (203), the second current mirroring circuit (204), transistor M1 and resistance R0 ~ R4;
The grid of described transistor M1 is connected with the output of the first error amplifier (201); Its drain electrode is connected with the first end of the first current mirroring circuit (203); Its source electrode is connected with the first end of the second current mirroring circuit (204) by resistance R0;
The in-phase input end of described first error amplifier (201) connects the common mode electrical level V of D audio frequency amplifier inside generation
cM, its inverting input is connected to the common port of transistor M1 and resistance R0;
One end of described resistance R1 is connected with the second end of the first current mirroring circuit (203); Other end series resistance R2, R3 and R4 of resistance R1 are to the second end of the second current mirroring circuit (204); The common port of resistance R1 and R2 produces the first output of circuit (2) as dual threshold, export threshold voltage V
rEF1; The common port of resistance R2 and R3 produces the second output of circuit (2) as dual threshold, export threshold voltage V
rEF2;
The inverting input of described second error amplifier (202) is connected with the output of self, component unit gain amplifying circuit; Its in-phase input end connects the common mode electrical level V that D audio frequency amplifier inside produces
cM; Its output is connected with the common port of resistance R3 with R4, for definite threshold voltage V
rEF1and V
rEF2common mode level.
3. Dual-threshold automatic gain control circuit according to claim 1, it is characterized in that dual threshold peak detection block (3), comprise the first comparator (301), the second comparator (302), 3 two input NOR gate (303,304,305) and latch (306);
The in-phase input end of described first comparator (301) is connected with the in-phase input end of the second comparator (302), as the input u of dual threshold peak detection block (3), connect the audio signal V that programmable gain amplifier (1) inputs
oUT; The inverting input of the first comparator (301), as the input f of dual threshold peak detection block (3), connects the threshold voltage V that dual threshold generation circuit (2) inputs
rEF1; Its output exports comparison signal OV1, and is connected with the one or two the second input inputting NOR gate (303);
The inverting input of described second comparator (302), as the input g of dual threshold peak detection block (3), connects the threshold voltage V that dual threshold generation circuit (2) inputs
rEF2; Its output exports comparison signal OV2, and is connected with the two or two first input end inputting NOR gate (304);
The first input end of the one or two input NOR gate (303), as the input k of dual threshold peak detection block (3), connects the control signal CTRL1 that reaction type gain control module (4) inputs; Its output is connected to the first input end of the three or two input NOR gate (305);
Second input of the two or two input NOR gate (304), as the input s of dual threshold peak detection block (3), connects the control signal CTRL2 that reaction type gain control module (4) inputs; Its output is connected to the second input of the three or two input NOR gate (305);
The output that the data input pin and the three or two of described latch (306) inputs NOR gate (305) is connected; Its input end of clock, as the input e of dual threshold peak detection block (3), connects the clock signal C K that D audio frequency amplifier inside produces, for the collection of data message; Its clear terminal, as the input h of dual threshold peak detection block (3), connects reset signal RST, for the removing of data message; Its output Q is as the output m of dual threshold peak detection block (3), and output latch signal PD, for providing the amplitude information detected.
4. Dual-threshold automatic gain control circuit according to claim 1, it is characterized in that reaction type gain control module (4), comprise the first combinational logic circuit (41), the second combinational logic circuit (42) and the 3rd combinational logic circuit (43);
Described first combinational logic circuit (41), the latch signal PD that its first input end inputs with dual threshold peak detection block (3) is connected; The reset signal RST2 that its second input inputs with the second combinational logic circuit (42) is connected, and resets for its internal counter; The clock signal C K that its 3rd input produces with D audio frequency amplifier inside is connected, for providing clock signal for its internal timer sum counter; This first combinational logic circuit (41) has 5 output signals, is respectively control signal T1, T3, PDB, reset signal RST1 and GAIN SELECT signal d23 ~ d0; Wherein control signal T1, T3 and reset signal RST1 are connected to the second combinational logic circuit (42), for generation of reset signal RSET and reset signal RST2; Output signal PDB is connected to the 3rd combinational logic circuit (43); GAIN SELECT signal d23 ~ d0 is as the output signal of the output z of reaction type gain control module (4);
Described second combinational logic circuit (42), the control signal T1 that its first input end inputs with the first combinational logic circuit (41) is connected; The control signal T3 that its second input inputs with the first combinational logic circuit (41) is connected; The reset signal RST1 that its 3rd input and the first combinational logic circuit (41) input is connected; The control signal CTRL1 that its four-input terminal inputs with the 3rd combinational logic circuit (43) is connected; The control signal CTRL2 that its 5th input inputs with the 3rd combinational logic circuit (43) is connected; This second combinational logic circuit (42) has 4 output signals, is respectively reset signal RSET, RST2 and control signal A, B; Wherein reset signal RSET is as the output signal of reaction type gain control module (4) output o; Reset signal RST2 is connected to the first combinational logic circuit (41); Control signal A and control signal B are all connected with the 3rd combinational logic circuit (43);
Described 3rd combinational logic circuit (43), the latch signal PD that its first input end inputs with dual threshold peak detection block (3) is connected; The latch signal PD that its second input inputs with the first combinational logic circuit (41) is connected; The reset signal RST1 that its 3rd input and the first combinational logic circuit (41) input is connected; The control signal A that its four-input terminal inputs with the second combinational logic circuit (42) is connected; The control signal B that its 5th input and the second combinational logic circuit (42) input is connected;
3rd combinational logic circuit (43) has 2 output signals, is respectively control signal CTRL1 and control signal CTRL2; The output end p of these two control signals respectively as reaction type gain control module (4) and the output signal of output q.
5. Dual-threshold automatic gain control circuit according to claim 4, it is characterized in that described the first combinational logic circuit (41), comprise not gate (501), 2 three input NOR gate (502,503), 2 timers (504,505), two input or door (506), forward-backward counter (507) and 5-32 decoders (508);
Described not gate (501), its input connects the latch signal PD that dual threshold peak detection block (3) inputs; Its output exports control signal PDB;
One or three input NOR gate (502), its first input end connection control signal PDB; Its second input connects reset signal RST1; Its 3rd input connects the reset signal RST2 that the second combinational logic circuit (42) inputs; Its output is connected with the second input of the first timer (504), as the enable signal of the first timer (504);
Two or three input NOR gate (503), its first input end connects reset signal RST1; Its second input connects the reset signal RST2 that the second combinational logic circuit (42) inputs; Its 3rd input connects the latch signal PD that dual threshold peak detection block (3) inputs; Its output is connected with the second input of the second timer (505), as the enable signal of the second timer (505);
First timer (504), its first input end is connected with external timing signal CK; Its first output exports control signal T1; Its second output exports control signal T2, and inputs with two or the first input end of door (506) is connected;
Second timer (505), its first input end is connected with external timing signal CK; Its first output exports control signal T4, and inputs with two or the second input of door (506) is connected; Its second output exports control signal T3;
Described two input or doors (506), its output exports reset signal RST1, and is connected to the 3rd input of forward-backward counter (507), as the clock signal of forward-backward counter (507);
Described forward-backward counter (507), the latch signal PD that its first input end inputs with dual threshold peak detection block (3) is connected, the control PDB that its second input inputs with dual threshold peak detection block (3) is connected, and is in and adds count status for controlling forward-backward counter or subtract count status; Forward-backward counter (507) exports five count signal q
4~ q
0, as the data input signal of 5-32 decoder (508);
Described 5-32 decoder (508), it exports 24 GAIN SELECT signal d23 ~ d0, as the output signal of reaction type gain control module (4) output z, for the selection of gain level.
6. Dual-threshold automatic gain control circuit according to claim 4, it is characterized in that described the second combinational logic circuit (42), comprise 3 two input nand gates (601,602,603) and two inputs NOR gate (604);
One or two input nand gate (601), its first input end connects the control signal T3 that the first combinational logic circuit (41) inputs; Its second input connects the control signal CTRL2 that the 3rd combinational logic circuit (43) inputs; Its output output signal A, and be connected with the first input end of the three or two input nand gate (603);
Two or two input nand gate (602), its first input end connects the control signal T1 that the first combinational logic circuit (41) inputs, and its second input connects the control signal CTRL1 that the 3rd combinational logic circuit (43) inputs; Its output output signal B, and be connected with the second input of the three or two input nand gate (603);
The output of the three or two input nand gate (603) exports reset signal RST2, and is connected with two the second inputs inputting NOR gate (604);
Described two inputs NOR gate (604), the reset signal RST1 that its first input connection first combinational logic circuit (41) inputs; Its output exports reset signal RSET, as the output signal of reaction type gain control module (4) output o.
7. Dual-threshold automatic gain control circuit according to claim 4, it is characterized in that the 3rd described combinational logic circuit (43), comprise 2 two input nand gates (701,702), 2 two inputs and door (703,704) and rest-set flip-flop (705);
One or two input nand gate (701), its first input end connects the latch signal PD that dual threshold peak detection block (3) inputs; The reset signal RST1 that its second input inputs with the first combinational logic circuit (41) is connected; Its output and the one or two inputs and is connected with the first input end of door (703);
Two or two input and door (702), the reset signal RST1 that its first input end inputs with the first combinational logic circuit (41) is connected; The control signal PDB that its second input inputs with the first combinational logic circuit (41) is connected; Its output and the two or two inputs and is connected with the first input end of door (704);
One or two input and door (703), its second input connects the control signal A that the second combinational logic circuit (42) inputs; Its output is held with the R of rest-set flip-flop (705) and is connected;
Two or two input and door (704), its second input connects the control signal B that the second combinational logic circuit (42) inputs; Its output is held with the S of rest-set flip-flop (705) and is connected;
Two outputs of described rest-set flip-flop (705) are respectively as the output end p of reaction type gain control module (4) and output q, and export control signal CTRL1 and CTRL2 to control dual threshold peak detection block (3), for controlling dual threshold peak detection block (3), cycle detection is carried out to peak value size.
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| CN104485910B (en) * | 2014-12-31 | 2017-12-19 | 上海艾为电子技术股份有限公司 | Gain control method and device |
| CN105099385B (en) * | 2015-08-24 | 2018-07-10 | 上海艾为电子技术股份有限公司 | Gain control circuit and audio frequency apparatus |
| CN105471402B (en) * | 2015-12-23 | 2017-11-10 | 中国人民解放军海军工程大学 | A kind of speed automatic gain control device and its control method |
| CN108063601B (en) * | 2017-12-29 | 2021-08-27 | 上海艾为电子技术股份有限公司 | Automatic gain control circuit and signal processing system |
| CN110545082B (en) * | 2018-05-28 | 2023-06-16 | 晶豪科技股份有限公司 | Modulation selection circuit of audio amplifier |
| CN109921812B (en) * | 2019-01-07 | 2021-05-04 | 广州昂宝电子有限公司 | Automatic gain control method and system |
| CN111901725B (en) * | 2020-07-22 | 2022-02-01 | 上海艾为电子技术股份有限公司 | Audio power amplifier circuit and power limiting method thereof |
| CN113179089B (en) * | 2021-04-19 | 2023-03-14 | 上海艾为电子技术股份有限公司 | Audio power amplifier circuit, power limiting method thereof and electronic equipment |
| CN113395075A (en) * | 2021-07-08 | 2021-09-14 | 成都智明达电子股份有限公司 | Double-threshold anti-jitter quick response extended AGC dynamic circuit |
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