CN110391252A - Electronic device - Google Patents

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Publication number
CN110391252A
CN110391252A CN201811178409.7A CN201811178409A CN110391252A CN 110391252 A CN110391252 A CN 110391252A CN 201811178409 A CN201811178409 A CN 201811178409A CN 110391252 A CN110391252 A CN 110391252A
Authority
CN
China
Prior art keywords
layer
electronic device
insulating layer
luminescence unit
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201811178409.7A
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Chinese (zh)
Inventor
范俊钦
林明昌
陈韵升
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Innolux Corp
Original Assignee
Innolux Display Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Innolux Display Corp filed Critical Innolux Display Corp
Priority to CN202211447930.2A priority Critical patent/CN115732516A/en
Priority to US16/360,521 priority patent/US20190326329A1/en
Priority to KR1020190040773A priority patent/KR20190122150A/en
Priority to EP19169096.5A priority patent/EP3557618B1/en
Publication of CN110391252A publication Critical patent/CN110391252A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/56—Materials, e.g. epoxy or silicone resin
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/127—Active-matrix OLED [AMOLED] displays comprising two substrates, e.g. display comprising OLED array and TFT driving circuitry on different substrates
    • H10K59/1275—Electrical connections of the two substrates

Abstract

The application provides a kind of electronic device.Electronic device includes substrate, the multiple thin film transistor (TFT)s and multiple luminescence units that are set on substrate.The one of them of these luminescence units has packaging plastic and an at least luminescence chip.This packaging plastic is set on luminescence chip, and this luminescence unit is electrically connected at least one of these thin film transistor (TFT)s.

Description

Electronic device
Technical field
The application relates to electronic device, and particularly with regard to a kind of display device.
Background technique
With the development of digital technology, electronic device has been widely used in the every aspect of daily life, such as It is widely used to the modernization information equipment such as TV, notebook computer, computer, mobile phone (such as: Smartphone). In addition, electronic device constantly develops towards light, thin, short and small and fashion-orientation direction.
In various types of electronic devices, light emitting diode (LED) display device because have as it is high-effect and use the longevity It orders long advantage and is becoming increasingly popular.
However, existing electronic device is not all satisfactory in all respects.
Summary of the invention
The some embodiments of the application provide a kind of electronic device.Electronic device include substrate, be set to it is multiple on substrate Thin film transistor (TFT) and multiple luminescence units.The one of them of these luminescence units has packaging plastic and at least one luminous core Piece.This packaging plastic is set on luminescence chip, and this luminescence unit is electrically connected at least one of these thin film transistor (TFT)s.
Hereinafter reference will be made to the drawings is described in detail embodiment.
Detailed description of the invention
When reading together with attached drawing, the application can be more fully understood by from the following detailed description.It is noticeable It is that, according to the standing procedure of industry, each feature is not painted by equal proportion.In fact, for the sake of clearly, the ruler of various features It is very little to be arbitrarily expanded or reduce.
Fig. 1 is the fragmentary cross-sectional view according to the electronic device 1 of some embodiments of the application.
Fig. 2 is the fragmentary cross-sectional view according to the electronic device 10 of some embodiments of the application.
Fig. 3 is the partial top view according to the conducting wire 134a of the conductive layer 134 of some embodiments of the application.
Fig. 4 is the fragmentary cross-sectional view according to the electronic device 20 of some embodiments of the application.
Fig. 5 is the fragmentary cross-sectional view according to the luminescence unit 150 of some embodiments of the application.
Fig. 6 is the partial top view according to the luminescence unit 150 of some embodiments of the application.
Fig. 7 is the fragmentary cross-sectional view according to the luminescence unit 150 of some embodiments of the application.
Fig. 8 is the fragmentary cross-sectional view according to the luminescence unit 150 of some embodiments of the application.
Fig. 9 is the fragmentary cross-sectional view according to the luminescence unit 150 of some embodiments of the application.
Figure 10 is the partial top view according to the luminescence unit 150 of some embodiments of the application.
Component label instructions in figure:
1,10,20~electronic device
17~insulating layer
18~conducting element
37,42~conductive layer
46a, 46b~conductive pad
100~composite substrate
102~pair layer
102a~opening or recess
4,104~substrate
The non-bent area of 104a~substrate
104b~substrate bendable folding area
106~insulating layer
108~insulating layer
11,110~active layer
11a, 110a~source/drain regions
11b, 110b~channel region
16,112~gate insulating layer
14,114~grid layer
116~insulating layer
118~metal layer
120~dielectric layer
124~conductive layer
12,126~passivation layer
128~bridging element
130~insulating layer
134~conductive layer
134a~conducting wire
36,136~insulating layer
38,138~insulating layer
142~conductive layer
44,144~insulating layer
146a, 146b~conductive pad
150~luminescence unit
150a, 150b~conductive pad
52,152~conducting medium
202~package substrate
204,206~conductor layer
208~packaging plastic
208a~encapsulating material
210~connection gasket
212~package substrate
212a~side wall
214~conducting wire
216~phosphor powder
O1、O2、O3~opening
T1、T2、T3~thickness
C1, C2, C3~luminescence chip
Specific embodiment
Disclosure below provides many different embodiments or example to implement the different characteristic of this case.Public affairs below The particular example of each component of description and its arrangement mode is opened, to simplify explanation.Certainly, these specific examples are not used To limit.If being formed in above a second feature for example, the application describes a fisrt feature, that is, indicate that it may With above-mentioned second feature it is the embodiment directly contacted comprising above-mentioned fisrt feature, has also may included supplementary features and be formed in Between above-mentioned fisrt feature and above-mentioned second feature, and the implementation that contact above-mentioned fisrt feature may directly with second feature Example.
In addition, different examples as disclosed below may reuse identical reference symbol and/or label.These are repeated It is to be not limited to have specific pass between the different embodiments discussed and/or structure for simplification and clearly purpose System.
The some embodiments of the application described below.Before these steps as described in the examples, between and/or later It can provide additional operation.Some steps can be substituted or omit in different embodiments.Although in addition, hereinafter with Several steps of particular order illustrate some embodiments of the application, but also reasonably can sequentially carry out these steps with other.
The some electronic devices of some embodiments offers of the application (such as: display device).The electronics of the embodiment of the present application fills A bendable folding area can be had by setting, which may be provided with the good insulating layer of ductility, therefore be bent these electronics dress The problem of being less also easy to produce as ruptured when setting.In addition, in some embodiments, being set between the luminescence unit and substrate of electronic device It is equipped on the whole upper flat insulating layer, so that the conductive pad for being used to connect luminescence unit on the whole upper can be located at identical level, because This can reduce the yield that luminescence unit engages bad problem with conductive pad and electronic device can be improved.
Fig. 1 shows the fragmentary cross-sectional view of the electronic device (such as: display device) 1 of the embodiment of the present application.Such as Fig. 1 institute Show, electronic device 1 may include substrate 4.For example, substrate 4 can be by low ductile material such as glass or high ductility material As polyimide (polyimide, PI), polyethylene terephthalate (polyethylene terephthalate, PET) or Other suitable materials are formed, but the application is not limited thereto.
Please continue to refer to Fig. 1, in some embodiments, electronic device 1 may include the grid layer being set on substrate 4 14.In some embodiments, grid layer 14 may include scan line.In some embodiments, grid layer 14 can by metal, other fit When conductive material or combinations of the above formed.Grid layer 14 can pass through chemical vapor deposition process, physical vapour deposition (PVD) system Journey, other processing procedures appropriate or combinations of the above are formed, but the application is not limited thereto.
Please continue to refer to Fig. 1, in some embodiments, electronic device 1 may include the grid being set on grid layer 14 Insulating layer 16.In some embodiments, gate insulating layer 16 may include silica, silicon nitride, silicon oxynitride, other materials appropriate Material or combinations of the above.In some embodiments, gate insulating layer 16 may include high-k dielectric materials.Gate insulating layer 16 can pass through chemical vapor deposition process, rotary coating process, atomic layer deposition processing procedure, other processing procedures appropriate or above-mentioned group It closes and is formed.
Please continue to refer to Fig. 1, in some embodiments, electronic device 1 may include being set on gate insulating layer 16 Active layer 11.In some embodiments, active layer 11 may include polysilicon, and above-mentioned polycrystalline can be formed via low temperature polycrystalline silicon processing procedure Silicon, but the application is not limited thereto.In some other embodiments, active layer 11 also may include amorphous silicon, indium gallium Zinc, other materials appropriate or combinations of the above.In some embodiments, active layer 11 may include source/drain regions 11a and Channel region 11b.In some embodiments, electronic device 1 may include insulating layer 17, and insulating layer 17 is set to gate insulating layer 16 On.
In some embodiments, as shown in Figure 1, electronic device 1 may include conducting element 18.In some embodiments, it leads Electric device 18 and source/drain regions 11a are electrically connected.For example, conducting element 18 can by metal, transparent conductive material, its His conductive material appropriate or combinations of the above are formed.Grid layer 14, gate insulating layer 16, active layer 10 and conducting element 18 can be collectively formed a thin film transistor (TFT).Fig. 1 is only painted a thin film transistor (TFT) of electronic device 1.In fact, electronic device 1 It may include multiple thin film transistor (TFT)s.
Please continue to refer to Fig. 1, in some embodiments, electronic device 1 may include the passivation being set on conducting element 18 Layer 12.For example, passivation layer 12 may include silicon nitride, silica, aluminium oxide, other materials appropriate or combinations of the above, And it is formed by chemical vapor deposition process, thermal oxidation process, other processing procedures appropriate or combinations of the above, but the application is not As limit.
Please continue to refer to Fig. 1, in some embodiments, electronic device 1 may include the insulation being set on passivation layer 12 Layer 36.In some embodiments, insulating layer 36 is to be formed by organic photoresist and have preferable ductility.In some realities Apply in example, can be used rotary coating process, slot coated processing procedure by organic photoresist of good fluidity be coated on substrate 4 it On, then carry out patterning process appropriate (such as: lithographic process, etch process, other processing procedures appropriate or above-mentioned group Close) to form insulating layer 36.In some embodiments, insulating layer 36 can be for via chemical vapor deposition process or other are appropriate Processing procedure is formed by silicon oxide layer, silicon nitride layer or other insulating layers appropriate.
Please continue to refer to Fig. 1, in some embodiments, electronic device 1 may include the insulation being set on insulating layer 36 Layer 38.The material and forming method of insulating layer 38 can be the same as or similar to insulating layers 36, for brevity, will no longer to this It is described in detail.
In some embodiments, as shown in Figure 1, electronic device 1 may include being set between insulating layer 36 and insulating layer 38 Conductive layer 37.In some embodiments, conductive layer 37 may include a common electrode.For example, conductive layer 37 can be by metal Oxide, metal or other conductive materials appropriate are formed.
In some embodiments, as shown in Figure 1, electronic device 1 may include the conductive layer 42 being set on insulating layer 38. In some embodiments, conductive layer 42 may include conducting wire, other conducting elements appropriate or combinations of the above.For example, it leads Electric layer 42 can be formed by metal or other conductive materials appropriate.For example, the processing procedure for forming conductive layer 42 may include object Vapor deposition process, lithographic process, etch process, other processing procedures appropriate or combinations of the above.
Please continue to refer to Fig. 1, in some embodiments, electronic device 1 may include the insulation being set on insulating layer 38 Layer 44.In some embodiments, insulating layer 44 can have on the whole upper flat top surface.In some embodiments, insulating layer 44 Top surface can on the whole upper parallel substrate 4 top surface, but the application is not limited thereto.In some embodiments, due to exhausted Edge layer 44 has on the whole upper flat top surface, thus be used to connect luminescence unit conductive pad (such as: following conductive pad 46a and 46b) on the whole upper it can be located at identical level, therefore luminescence unit can be reduced and engage bad problem with conductive pad, in turn Improve the yield of electronic device.
In some embodiments, insulating layer 44 may include silicon nitride, silica, other materials appropriate or above-mentioned group It closes.In some embodiments, insulating layer 44 may include high molecular material.In some embodiments, insulating layer 44 may include organic Photoresist.In some embodiments, can be used chemical vapor deposition process, thermal oxidation process, other processing procedures appropriate or on The combination stated forms insulating layer 44.In some embodiments, the processing procedure for forming insulating layer 44 may include rotary coating process, solidification Processing procedure, other processing procedures appropriate or combinations of the above.
Please continue to refer to Fig. 1, in some embodiments, electronic device 1 may include conductive pad 46a and conductive pad 46b.One In a little embodiments, at least part of insulating layer 44 is located between conductive pad (such as: 46a, 46b).In some embodiments, it leads The top surface of electrical pad 46a and the top surface of conductive pad 46b on the whole upper can be located at identical level.In some embodiments, conductive The top surface of the top surface and conductive pad 46b that pad 46a can be coplanar.
In some embodiments, conductive pad 46a and conductive pad 46b can extend into insulating layer from the top surface of insulating layer 44 In 44.In some embodiments, conductive pad 46a and conductive pad 46b can be by metal, other conductive materials appropriate or above-mentioned groups Conjunction is formed.
In some embodiments, can be used patterning process (such as: lithographic process, etch process, other processing procedures appropriate Or combinations of the above) opening appropriate is formed in insulating layer 44, then use physical vapour deposition (PVD) processing procedure, electroplating process, nothing Electroplating process, other processing procedures appropriate or combinations of the above deposit conduction in above-mentioned opening and on the top surface of insulating layer 44 Material is to form conductive pad 46a and conductive pad 46b.
Please continue to refer to Fig. 1, in some embodiments, electronic device 1 may include being bonded to conductive pad 46a and conductive pad The luminescence unit 150 of 46b.In some embodiments, electronic device 1 has multiple luminescence units, but for brevity, is scheming A luminescence unit is only drawn in 1.In some embodiments, luminescence unit 150 may include light emitting diode, organic light-emitting diodes Pipe, micro- light emitting diode, light emitting diode with quantum dots, secondary millimeter light emitting diode, other luminescence units appropriate or above-mentioned Combination.For example, luminescence unit 150 can be electrically connected to conductive pad 46a and conductive pad 46b via conducting medium 52.It lifts For example, conducting medium 52 may include tin, tin alloy, conducting resinl, other materials appropriate or combinations of the above.In some implementations It may include welding processing procedure, such as surface adhering technical by the processing procedure that luminescence unit 150 is bonded to conductive pad 46a and 46b in example (SMT), but the application is not limited thereto.In some embodiments, conducting medium 52 and conductive pad 46a or 46b are in vertical view side Overlapping upwards, but the application is not limited thereto.
In some embodiments, luminescence unit 150 can be via conducting medium 52, conductive pad 46a or 46b and conductive layer 42 It is electrically connected to conducting element 18.Aforementioned film transistor can control the luminous performance of luminescence unit 150.In some embodiments In, light-emitting component 150 is electrically connected to multiple thin film transistor (TFT)s.
Fig. 2 shows the fragmentary cross-sectional view of the electronic device (such as: display device) 10 of the embodiment of the present application.Such as Fig. 2 institute Show, in some embodiments, electronic device 10 may include composite substrate 100.In some embodiments, composite substrate 100 can wrap Transparent substrate is included, but the application is not limited thereto.In some embodiments, composite substrate 100 may include secondary layer 102, substrate 104 and the thin film transistor (TFT) that is set on substrate 104.For example, above-mentioned thin film transistor (TFT) can be by described hereinafter active Layer 110, gate insulating layer 112 with door grid layer 114 to form.In some embodiments, composite substrate 100 may include substrate 104 and the thin film transistor (TFT) that is set on substrate 104 but do not include secondary layer 102.
As shown in Fig. 2, substrate 104 may include non-bent area 104a and bendable folding area 104b.In some embodiments, may be used Bent area 104b is adjacent with non-bent area 104a.It specifically, can be by the substrate 104 of electronic device 10 in these embodiments Bendable folding area 104b and be formed on the 104b of bendable folding area each film layer and element bending.
In some embodiments, may be provided with thin film transistor (TFT) in the non-bent area 104a of substrate 104, substrate 104 can It may be provided with conducting wire in the 104b of bent area, but the application is not limited thereto.
In some embodiments, substrate 104 can be flexible film layer (flexible layer).In some embodiments, base The ductility of plate 104 can be greater than the ductility of secondary layer 102.In some embodiments, secondary layer 102 intensity (such as: stretch strong Degree) intensity of substrate 104 can be greater than.
In some embodiments, secondary layer 102 can be formed from substrate 104 by different materials.For example, secondary layer 102 It can be formed by glass, and substrate 104 can be by polyimide (polyimide, PI) or polyethylene terephthalate (polyethylene terephthalate, PET) is formed, but the application is not limited thereto.In some other embodiments In, secondary layer 102 can be formed with substrate 104 by any other material appropriate.
In some embodiments, method of spin coating (spin-on coating), rolling process, vacuum abutted method, change can be used Vapour deposition process (chemical vapor deposition, CVD), other methods or combinations of the above appropriate are learned in secondary layer Substrate 104 is formed on 102, but the application is not limited thereto.
In some embodiments, it is opened as shown in Fig. 2, one or more can be formed below the bendable folding area 104b of substrate 104 Mouth (or recess) 102a, therefore can reduce when bending composite substrate 100 due to caused by the lower ductility of secondary layer 102 The problem of rupture.
In some embodiments, as shown in Fig. 2, opening (or recess) 102a can expose the substrate 104 of composite substrate 100, But the application is not limited thereto.In some other embodiments, opening (or recess) 102a can not expose composite substrate 100 Substrate 104.
Please continue to refer to Fig. 2, in some embodiments, electronic device 10 may include the insulation being set on substrate 104 Layer 106.In some embodiments, insulating layer 106 can obstruct aqueous vapor and oxygen, therefore can reduce and be set on insulating layer 106 Film layer there is a situation where aoxidize.For example, insulating layer 106 may include silicon nitride, silica, aluminium oxide, other are appropriate Material or combinations of the above, and pass through chemical vapor deposition process, thermal oxidation process, other processing procedures appropriate or combinations of the above It is formed, but the application is not limited thereto.
In some embodiments, after forming insulating layer 106, patterning process can be carried out to insulating layer 106 in exhausted Opening O is formed in edge layer 1061A part.In some embodiments, be open O1Can be located at substrate 104 bendable folding area 104b it Among the upper and/or bendable folding area 104b of substrate 104.In some embodiments, be open O1The top surface of substrate 104 can be exposed. In some embodiments, in top view, be open O1It can be essentially ellipse, square, rectangle, circle, oblong (oblong), triangle, polygonal, irregular shape, other proper shapes or combinations of the above.
In some embodiments, above-mentioned patterning process may include lithographic process, etch process, other processing procedures appropriate or Combinations of the above.For example, lithographic process may include light blockage coating (photoresist coating) (such as: rotation apply Cloth), soft baking (soft baking), light shield alignment (mask aligning), exposure (exposure), postexposure bake (post-exposure), photoresist development (developing photoresist), rinse (rising), dry (such as hard baking (hard baking)), other processing procedures appropriate or combinations of the above.For example, etch process may include dry etch process (such as: plasma etching processing procedure), wet etch process, other processing procedures appropriate or combinations of the above.
Please continue to refer to Fig. 2, in some embodiments, electronic device 10 may include be set to it is exhausted on insulating layer 106 Edge layer 108.Insulating layer 108 may include silicon nitride, silica, aluminium oxide, other materials appropriate or combinations of the above, and pass through Formed using chemical vapor deposition process, thermal oxidation process, other processing procedures appropriate or combinations of the above, but the application not with This is limited.In some embodiments, insulating layer 106 can be formed with insulating layer 108 by identical material, but the application not with This is limited.In some other embodiments, insulating layer 106 can be formed by different materials from insulating layer 108 (such as: absolutely Edge layer 106 is formed by silica, and insulating layer 108 is formed by silicon nitride).
In some embodiments, after forming insulating layer 108, patterning process can be carried out to insulating layer 108 in exhausted Opening O is formed in edge layer 1081A part.In some embodiments, the opening O in insulating layer 1081Part and insulating layer Opening O in 1061Part be connected.In some embodiments, above-mentioned patterning process may include lithographic process, etching system Journey, other processing procedures appropriate or combinations of the above.
Please continue to refer to Fig. 2, in some embodiments, electronic device 10 may include being set to having on insulating layer 108 Active layer 110.In some embodiments, active layer 110 may include polysilicon, can be via low temperature polycrystalline silicon (Low Temperature Poly-silicon, LTPS) processing procedure forms above-mentioned polysilicon, but the application is not limited thereto.In some other embodiments In, active layer 110 also may include amorphous silicon (Amorphous silicon, a-Si), indium gallium zinc (indium gallium Zinc oxide, IGZO), other materials appropriate or combinations of the above.
In some embodiments, active layer 110 may include the source/drain regions 110a and channel region of thin film transistor (TFT) 110b.In some embodiments, source/drain regions 110a is the source/drain regions of n-type thin film transistor, therefore source/drain Area 110a can be doped with phosphorus, arsenic, antimony, other N-shaped admixtures appropriate or combinations of the above.In some other embodiments, source Pole/drain region 110a be p-type thin film transistor source/drain regions, therefore source/drain regions 110a can doped with boron, indium, its His p-doping or combinations of the above appropriate.It in some embodiments, can be via ion disposing process by admixture implant appropriate The source/drain regions 110a of thin film transistor (TFT) is formed into active layer 110.
Please continue to refer to Fig. 2, in some embodiments, electronic device 10 may include the grid being set on active layer 110 Pole insulating layer 112.In some embodiments, gate insulating layer 112 may include silica, it is silicon nitride, silicon oxynitride, other appropriate Material or combinations of the above.In some embodiments, gate insulating layer 112 may include high dielectric constant (high-k) dielectric material Material, such as: LaO, AlO, ZrO, TiO, Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfO2、HfO3、 HfZrO、HfLaO、HfSiO、HfSiON、LaSiO、AlSiO、HfTaO、HfTiO、HfTaTiO、HfAlON、(Ba,Sr)TiO3 (BST)、Al2O3, other materials appropriate or said combination.Gate insulating layer 112 can pass through chemical vapor deposition process, rotation Coating process, atomic layer deposition processing procedure, other processing procedures appropriate or combinations of the above are formed.For example, chemical vapor deposition Processing procedure may include low-pressure chemical vapor deposition processing procedure (low pressure chemical vapor deposition, LPCVD), Low temperature chemical vapor deposition processing procedure (low temperature chemical vapor deposition, LTCVD) quickly rises Warm chemical vapor deposition process (rapid thermal chemical vapor deposition, RTCVD), plasma asistance Chemical vapor deposition process (plasma enhanced chemical vapor deposition, PECVD), other are appropriate Chemical vapor deposition process or combinations of the above.
In some embodiments, after forming gate insulating layer 112, patterning system can be carried out to gate insulating layer 112 Journey in gate insulating layer 112 to form opening O1A part.In some embodiments, the opening O in gate insulating layer 1121 Part and the opening O in insulating layer 1081Part be connected.In some embodiments, above-mentioned patterning process may include light Scribe journey, etch process, other processing procedures appropriate or combinations of the above.
Please continue to refer to Fig. 2, in some embodiments, electronic device 10 may include being set on gate insulating layer 112 Grid layer 114.In some embodiments, active layer 110, gate insulating layer 112 are thin can be collectively formed with door grid layer 114 Film transistor.In some embodiments, the luminescence unit (example for being transferred to electronic device 10 can be controlled via above-mentioned thin film transistor (TFT) Current signal such as: luminescence unit 150 described hereinafter), and the luminous performance of the luminescence unit of controllable electronic device 10.In In some embodiments, grid layer 114 may include or be electrically connected to the scan line (scan lines) of electronic device 10.
In some embodiments, grid layer 114 may include metal, metal nitride, metal oxide, other appropriate lead Electric material or combinations of the above.For example, above-mentioned metal may include copper (copper), molybdenum (molybdenum), tungsten (tungsten), titanium (titanium), tantalum (tantalum), platinum (platinum), hafnium (hafnium), other metals appropriate Or combinations of the above.For example, above-mentioned metal nitride may include molybdenum nitride (molybdenum nitride), tungsten nitride (tungsten nitride), titanium nitride (titanium nitride), tantalum nitride (tantalum nitride), other are appropriate Metal nitride or combinations of the above.For example, above-mentioned metal oxide may include ruthenium-oxide (ruthenium Oxide), tin indium oxide (indium tin oxide), other metal oxides appropriate or combinations of the above.Grid layer 114 Can by chemical vapor deposition process, physical vapour deposition (PVD) processing procedure (such as: sputter process or vapor deposition processing procedure), other systems appropriate Journey or combinations of the above are formed, but the application is not limited thereto.
Please continue to refer to Fig. 2, in some embodiments, electronic device 10 may include be set to it is exhausted on grid layer 114 Edge layer 116.In some embodiments, insulating layer 116 may act as the insulating layer of metal-insulator-metal (MIM) capacitance structure.
For example, insulating layer 116 may include silicon nitride, silica, aluminium oxide, other materials appropriate or above-mentioned group It closes, and is formed by chemical vapor deposition process, thermal oxidation process, other processing procedures appropriate or combinations of the above, but the application It is not limited thereto.
In some embodiments, after forming insulating layer 116, patterning process can be carried out to insulating layer 116 in exhausted Opening O is formed in edge layer 1161A part.In some embodiments, the opening O in insulating layer 1161Part and gate insulator Opening O in layer 1121Part be connected.In some embodiments, above-mentioned patterning process may include lithographic process, etching Processing procedure, other processing procedures appropriate or combinations of the above.
Please continue to refer to Fig. 2, in some embodiments, electronic device 10 may include the gold being set on insulating layer 116 Belong to layer 118.In some embodiments, metal-insulator-can be collectively formed in grid layer 114, insulating layer 116 and metal layer 118 Metal (MIM) capacitance structure.The material and forming method of metal layer 118 can be the same as or similar to the materials and shape of grid layer 114 At method.For brevity, it will not be described in further detail in this.
Please continue to refer to Fig. 2, in some embodiments, electronic device 10 may include being set to insulating layer 116 and metal Dielectric layer 120 on layer 118.In some embodiments, dielectric layer 120 may include silica, the other materials appropriate of silicon nitride Material or combinations of the above, and pass through chemical vapor deposition process, thermal oxidation process, other processing procedures appropriate or combinations of the above shape At, but the application is not limited thereto.
In some embodiments, after forming dielectric layer 120, patterning process can be carried out to dielectric layer 120 with Jie Yu Opening O is formed in electric layer 1201A part.In some embodiments, the opening O in dielectric layer 1201Part and insulating layer Opening O in 1161Part be connected.In some embodiments, above-mentioned patterning process may include lithographic process, etching system Journey, other processing procedures appropriate or combinations of the above.
Please continue to refer to Fig. 2, in some embodiments, electronic device 10 may include being set to leading on dielectric layer 120 Electric layer 124.In some embodiments, conductive layer 124 may include or be electrically connected to the data line (data of electronic device 10 lines)。
In some embodiments, electronic device 10 may include through dielectric layer 120, insulating layer 116 and/or gate insulating layer 112 one or more guide holes, conductive layer 124 are electrically connected to active layer 110 via guide hole.In some embodiments, conductive layer 124 can directly contact the source/drain regions 110a of active layer 110.In some embodiments, metal layer 118 can be via conductive layer 124 are electrically connected to active layer 110.In some embodiments, conductive layer 124 may include copper, molybdenum, tungsten, titanium, aluminium, tantalum, platinum, hafnium, The alloy of other conductive materials or above-mentioned material appropriate.
In some embodiments, can be used patterning process (such as: lithographic process, etch process, other processing procedures appropriate Or combinations of the above) one or more openings appropriate are formed in dielectric layer 120, insulating layer 116 and/or gate insulating layer 112, Then using physical vapour deposition (PVD) processing procedure (such as: sputter or vapor deposition), electroplating process, other processing procedures appropriate or combinations of the above Filling conductive material is in one or more above-mentioned openings to form conductive layer 124 in one or more above-mentioned openings.
In some embodiments, can be used physical vapour deposition (PVD) processing procedure (such as: sputter or vapor deposition), electroplating process, other Processing procedure appropriate or combinations of the above are in the conductive blanket layer (blanket of formation on dielectric layer 120 and conductive layer 124 Layer), then above-mentioned conductive blanket layer can be carried out patterning process (such as: lithographic process, etch process, other are appropriate Processing procedure or combinations of the above) to form patterned conductive layer 124.
Please continue to refer to Fig. 2, in some embodiments, electronic device 10 may include being set to conductive layer 124 and dielectric layer Passivation layer 126 on 120.For example, passivation layer 126 may include silicon nitride, silica, aluminium oxide, other materials appropriate Material or combinations of the above, and pass through chemical vapor deposition process, thermal oxidation process, other processing procedures appropriate or combinations of the above shape At, but the application is not limited thereto.
In some embodiments, after forming passivation layer 126, patterning process can be carried out to passivation layer 126 in blunt Change and forms opening O in layer 1261A part.In some embodiments, the opening O in passivation layer 1261Part and dielectric layer Opening O in 1201Part be connected.In some embodiments, above-mentioned patterning process may include lithographic process, etching system Journey, other processing procedures appropriate or combinations of the above.
Please continue to refer to Fig. 2, in some embodiments, electronic device 10 may include being set on passivation layer 126 and passing through Wear one or more bridging elements 128 of passivation layer 126.In some embodiments, bridging element 128 and conductive layer 124 can be by not Same material is formed, but the application is not limited thereto.
In some embodiments, bridging element 128 may include indium tin oxide (ITO), tin oxide (SnO), indium zinc oxide (IZO), indium gallium zinc (IGZO), indium tin zinc oxide (ITZO), antimony tin (ATO), antimony oxide zinc (AZO), other are appropriate Transparent conductive material or combinations of the above.In some other embodiments, bridging element 128 may include copper, molybdenum, tungsten, titanium, Aluminium, tantalum, platinum, hafnium, other metal materials appropriate or combinations of the above, but the application is not limited thereto.
In some embodiments, can be used patterning process (such as: lithographic process, etch process, other processing procedures appropriate Or combinations of the above) one or more openings appropriate are formed in passivation layer 126, physical vapour deposition (PVD) processing procedure then can be used (such as vapor deposition or sputter), atomic layer deposition processing procedure, other processing procedures appropriate or combinations of the above are in one or more above-mentioned openings Middle filling conductive material appropriate and in forming a conductive blanket layer on passivation layer 126, then can to above-mentioned conductive blanket layer into Row patterning process (such as: lithographic process, etch process, other processing procedures appropriate or combinations of the above) to form bridging element 128。
Please continue to refer to Fig. 2, in some embodiments, electronic device 10 may include being set to passivation layer 126 and bendable Insulating layer 130 on the 104b of folding area.In some embodiments, the fillable opening O of insulating layer 1301.In some embodiments, Insulating layer 130 is formed by compared to insulating layer 106, insulating layer 108, gate insulating layer 112, insulating layer by organic photoresist 116, dielectric layer 120 and/or passivation layer 126 have preferable ductility.In some embodiments, due to preferable with ductility The filling opening of insulating layer 130 O1(also that is, replacing insulating layer 106, the insulating layer 108, grid of part with the insulating layer 130 of part Insulating layer 112, insulating layer 116, dielectric layer 120 and/or passivation layer 126), therefore the hair when bending electronic device 10 can be reduced The situation of raw rupture.
In some embodiments, it can be used rotary coating process, slot coated processing procedure (slit coating) by mobility Good organic photoresist is coated on the non-bent area 104a and bendable folding area 104b of substrate 104, is then fitted When patterning process (such as: lithographic process, etch process, other processing procedures appropriate or combinations of the above) to form insulating layer 130.In some embodiments, it since the organic photoresist for being used to be formed insulating layer 130 has good mobility, can fill up The surface difference of height of the formed structure of abovementioned layers, planarizes body structure surface.Therefore, insulating layer 130 can have on the whole upper flat Smooth top surface.In some embodiments, on the whole the top surface of insulating layer 130 can go up the top surface of parallel substrate 104, but this Shen It please be not limited thereto.
As shown in Fig. 2, on the non-bent area 104a of substrate 104 insulating layer 130 (such as: the insulating layer on active layer 110 130) there can be thickness T1, the insulating layer 130 on the bendable folding area 104b of substrate 104 can have thickness T2.In some embodiments In, thickness T1It is smaller than thickness T2, but the application is not limited thereto.
Please continue to refer to Fig. 2, in some embodiments, electronic device 10 may include being set to leading on insulating layer 130 Electric layer 134.In some embodiments, conductive layer 134 may include conducting wire, conductive pad, other conducting elements appropriate or above-mentioned Combination.
In some embodiments, electronic device 10 may include one or more guide holes being set in insulating layer 130, conductive layer 134 are electrically connected to bridging element 128 via guide hole.In some embodiments, conductive layer 134 is electrical via bridging element 128 It is connected to conductive layer 124.
In some embodiments, conductive layer 134 may include molybdenum, tungsten, titanium, aluminium, tantalum, platinum, hafnium, copper, other conductions appropriate Material or combinations of the above.In some embodiments, conductive layer 134 may include being formed by laminated construction by multiple metal layers (such as: Ti/Al/Ti laminated construction).
In some embodiments, lithographic process can be used to form one or more openings appropriate in insulating layer 130, then Using physical vapour deposition (PVD) processing procedure (such as: sputter or vapor deposition), electroplating process, other processing procedures appropriate or combinations of the above in upper It states and inserts conductive material in one or more openings to form conductive layer 134 in one or more above-mentioned openings.For example, above-mentioned Lithographic process may include the developing manufacture process using developer solution.In some bridging elements 128 by previously described transparent conductive material (such as: it ITO) is formed by embodiment, since these transparent conductive materials are less susceptible to by above-mentioned development liquid damage, bridge The film layer (such as: conductive layer 124) that connecing element 128 can be reduced below is occurred by the situation of above-mentioned development liquid damage.
In some embodiments, can be used physical vapour deposition (PVD) processing procedure (such as: sputter or vapor deposition), electroplating process, other Then processing procedure appropriate or combinations of the above can be led in forming conductive blanket layer on insulating layer 130 and conductive layer 134 to above-mentioned Electrical blanket coating progress patterning process (such as: lithographic process, etch process, other processing procedures appropriate or combinations of the above) with shape At patterned conductive layer 134.
In some embodiments, as shown in Figures 2 and 3, conductive layer 134 on the 104b of bendable folding area include a conducting wire 134a And one or more openings O2.For example, be open O2(as shown in Figure 3) can be formed in the conducting wire 134a of conductive layer 134.In In some embodiments, conducting wire 134a has a wavy edge.In some embodiments, in top view, at least one opening O2 Can it is completely overlapped or partially overlap opening O1.In some embodiments, the wavy edge of conducting wire 134a or opening O2It can reduce The situation that conductive layer 134 ruptures when electronic device 10 to be bent.
For example, can be used patterning process (such as: lithographic process, etch process, other processing procedures appropriate or above-mentioned Combination) formed in conductive layer 134 one or more opening O2.In some embodiments, in top view, be open O2It can be substantive It is upper for ellipse, square, rectangle, circle, oblong, triangle, polygonal, irregular shape, other proper shapes or on The combination stated.
Please continue to refer to Fig. 2, in some embodiments, electronic device 10 may include setting conductive layer 134 and insulating layer Insulating layer 136 on 130.In some embodiments, the fillable opening O of insulating layer 1362。
In some embodiments, the material of insulating layer 136 and forming method can be the same as or similar to the materials of insulating layer 130 And forming method.For brevity, it will not be described in further detail in this.
In some embodiments, since the organic photoresist for being used to be formed insulating layer 136 has good mobility, because This insulating layer 136 can have on the whole upper flat top surface.In some embodiments, the top surface of insulating layer 136 can on the whole on The top surface of parallel substrate 104, but the application is not limited thereto.
As shown in Fig. 2, insulating layer 136 can have thickness T3.For example, thickness T3It can be 1 to 5 μm, but the application is not As limit.
Please continue to refer to Fig. 2, in some embodiments, electronic device 10 may include insulating layer 138.In some embodiments In, insulating layer 138 can extend into insulating layer 136 from the top surface of insulating layer 136.In some embodiments, insulating layer 138 It may include the insulating materials appropriate such as silicon nitride or combinations of the above.In some embodiments, insulating layer 138 and insulating layer 136 It can be formed from different materials.
For example, the thickness of insulating layer 138 can be 0.1 to 1 μm, but the application is not limited thereto.In some implementations In example, lithographic process can be used to form one or more openings appropriate in insulating layer 136, then uses chemical vapor deposition system Journey, other processing procedures appropriate or combinations of the above on the upper top surface for being set forth in insulating layer 136 and it is above-mentioned one or more opening Middle deposition of insulative material is to form insulating layer 138.
In some embodiments, after forming insulating layer 138, patterning process can be carried out to insulating layer 138 in exhausted Opening O is formed in edge layer 1383A part.In some embodiments, be open O3It can be located on the 104b of bendable folding area.In some realities It applies in example, in top view, be open O3It can be overlapped or partially overlap opening O1.In some embodiments, it in top view, opens Mouth O3It can be overlapped or partially overlap at least one opening O2.In some embodiments, in top view, be open O3Can be essentially Ellipse, square, rectangle, circle, oblong, triangle, polygonal, irregular shape, other proper shapes or above-mentioned Combination.For example, above-mentioned patterning process may include lithographic process, etch process, other processing procedures appropriate or above-mentioned group It closes.
Please continue to refer to Fig. 2, in some embodiments, electronic device 10 may include being set to leading on insulating layer 136 Electric layer 142.In some embodiments, conductive layer 142 may include conducting wire, conductive pad, other conducting elements appropriate or above-mentioned Combination.In some embodiments, conductive layer 142 is electrically connected to conductive layer 134 via opening.
In some embodiments, conductive layer 142 may include molybdenum, tungsten, titanium, aluminium, tantalum, platinum, hafnium, copper, chromium, lead, nickel, zinc, indium, The alloy of golden, above-mentioned metal, other conductive materials appropriate or combinations of the above.In some embodiments, conductive layer 142 can wrap It includes and is formed by laminated construction (such as: Mo/Cu laminated construction) by multiple metal layers.For example, the thickness of conductive layer 142 can It is 0.5 to 5 μm, but the application is not limited thereto.
In some embodiments, lithographic process can be used to form one or more openings appropriate in insulating layer 136, then Using physical vapour deposition (PVD) processing procedure (such as: sputter or vapor deposition), electroplating process, other processing procedures appropriate or combinations of the above in upper It states and inserts conductive material in one or more openings to form conductive layer 142 in one or more above-mentioned openings.
In some embodiments, can be used physical vapour deposition (PVD) processing procedure (such as: sputter or vapor deposition), electroplating process, other Then processing procedure appropriate or combinations of the above can be led in forming conductive blanket layer on insulating layer 136 and conductive layer 142 to above-mentioned Electrical blanket coating progress patterning process (such as: lithographic process, etch process, other processing procedures appropriate or combinations of the above) with shape At patterned conductive layer 142.
In some embodiments, the insulating layer 138 being set between conductive layer 142 and insulating layer 136 may act as adhesion coating, And the situation that conductive layer 142 falls off from insulating layer 136 can be reduced and occurred.
Please continue to refer to Fig. 2, in some embodiments, electronic device 10 may include being set to insulating layer 138 and conduction Insulating layer 144 on layer 142.In some embodiments, insulating layer 144 can have on the whole upper flat top surface.Some In embodiment, on the whole the top surface of insulating layer 144 can go up the top surface of parallel substrate 104, but the application is not limited thereto.In In some embodiments, since insulating layer 144 has on the whole upper flat top surface, it is used to connect the conductive pad of luminescence unit (such as: it following conductive pad 146a and 146b) on the whole upper can be located at identical level, therefore luminescence unit and conduction can be reduced Pad the yield for engaging bad problem and improving electronic device.
In some embodiments, insulating layer 144 may include silicon nitride, silica, other materials appropriate or above-mentioned group It closes.In some embodiments, insulating layer 144 may include high molecular material.In some embodiments, insulating layer 144 may include having Machine photoresist.
In some embodiments, chemical vapor deposition process, thermal oxidation process, other processing procedures appropriate or above-mentioned can be used Combination form insulating layer 144.In some embodiments, the processing procedure for forming insulating layer 144 may include rotary coating process, solidification Processing procedure, other processing procedures appropriate or combinations of the above.
In some embodiments, after forming insulating layer 144, patterning process can be carried out to insulating layer 144 in exhausted Opening O is formed in edge layer 1443A part.In some embodiments, the opening O in insulating layer 1443Part and insulating layer Opening O in 1383Part be connected.For example, above-mentioned patterning process may include lithographic process, etch process, other Processing procedure appropriate or combinations of the above.
Please continue to refer to Fig. 2, in some embodiments, electronic device 10 may include conductive pad 146a and conductive pad 146b. In some embodiments, at least part of insulating layer 144 be located at conductive pad (such as: conductive pad 146a and conductive pad 146b) it Between.In some embodiments, conductive pad 146a and 146b on the whole upper can be located at identical level, therefore can reduce luminescence unit (such as: following luminescence unit 150) bad problem is engaged with conductive pad 146a and conductive pad 146b and improves electronics dress The yield set.In some embodiments, the top surface of conductive pad 146a and the top surface of conductive pad 146b on the whole upper can be located at phase Same level.In some embodiments, the top surface of conductive pad 146a can be coplanar with the top surface of conductive pad 146b.
In some embodiments, conductive pad 146a and conductive pad 146b can be extended into absolutely from the top surface of insulating layer 144 In edge layer 144.In some embodiments, conductive pad 146a and conductive pad 146b may include molybdenum, tungsten, titanium, aluminium, tantalum, platinum, hafnium, copper, Chromium, lead, nickel, zinc, indium, gold, the alloy of above-mentioned metal, other conductive materials appropriate or combinations of the above.In some embodiments In, conductive pad 146a and conductive pad 146b may include be formed by by multiple metal layers laminated construction (such as: Ni/Au lamination knot Structure).In some embodiments, the outermost layer of conductive pad 146a and conductive pad 146b can be preferable by inoxidizability such as platinum, gold, palladiums Metal or combinations of the above be formed by anti oxidation layer, but the application is not limited thereto.
In some embodiments, can be used patterning process (such as: lithographic process, etch process, other processing procedures appropriate Or combinations of the above) opening appropriate is formed in insulating layer 144, then using physical vapour deposition (PVD) processing procedure (such as: sputter or Vapor deposition), electroplating process, electroless plating processing procedure, other processing procedures appropriate or combinations of the above be in above-mentioned opening and insulating layer 144 Top surface on deposit conductive material to form conductive pad 146a and conductive pad 146b.
Please continue to refer to Fig. 2, in some embodiments, electronic device 10 may include being bonded to conductive pad 146a and conductive pad The luminescence unit 150 of 146b.In some embodiments, luminescence unit 150 may include light emitting diode (such as: blue-light-emitting two Pole pipe, red light emitting diodes or green LED), Organic Light Emitting Diode, micro- light emitting diode (Micro LED), Light emitting diode with quantum dots (Quantum Dot LED), secondary millimeter light emitting diode (Mini LED), other luminous lists appropriate Member or combinations of the above.
In some embodiments, luminescence unit 150 can be via conductive pad 146a and 146b, conductive layer 142, conductive layer 134, conductive layer 124 and it is electrically connected to the source/drain regions 110a of active layer 110.
Fig. 4 is that electronic device 20 (such as: display device) is shown according to some embodiments of the application.Electronic device 20 with One of difference of electronic device 10 is the luminescence unit 150 and 110 lateral separation of active layer of electronic device 20.Some In embodiment, active layer 110 is not be overlapped in the normal direction with luminescence unit 150, in this application, normal direction be perpendicular to The direction of 104 top surface of substrate.In some embodiments, laterally due to the luminescence unit 150 of electronic device 20 and active layer 110 Separation, therefore active layer 110 when luminescence unit 150 is bonded to conductive pad 146a and 146b can be reduced and pressed by luminescence unit 150 Bad situation occurs.
In some embodiments, luminescence unit 150 may include major part (such as: luminescence chip C1 described hereinafter) with And connection features.In some embodiments, the major part of luminescence unit 150 includes quantum well structures and can have good hair Light efficiency.For example, the major part of luminescence unit 150 may include gallium nitride, aluminium gallium nitride alloy, aluminium nitride, GaAs, phosphatization Indium gallium, aluminum gallium arsenide, indium phosphide, indium arsenide aluminium, InGaAsP, InGaP aluminium, other semiconductor materials appropriate or above-mentioned Combination, but the application is not limited thereto.
Luminescence unit 150 can be electrically connected via its connection features and conductive pad 146a and 146b.In other words, it shines single Member 150 can be electrically connected via its connection features and thin film transistor (TFT).In some embodiments, the connection of luminescence unit 150 is special Sign may include conductor layer, conductive pad, electrode, convex block, other connection features or combinations of the above appropriate.For example, it shines The connection features of unit 150 may include metal material (such as: copper, tungsten, silver, tin, nickel, chromium, titanium, lead, gold, bismuth, antimony, zinc, zirconium, Magnesium, indium, tellurium, gallium or other metals appropriate), the alloy of above-mentioned metal material, other conductive materials appropriate or above-mentioned group It closes, but the application is not limited thereto.
In some embodiments, luminescence unit 150 can be electrically connected to via conducting medium 152 conductive pad 146a with 146b.In some embodiments, conducting medium 152 is Chong Die with conductive pad 146a or 146b in the normal direction.In some implementations In example, conducting medium 152 directly contacts the connection features of conductive pad 146a and 146b and luminescence unit 150.For example, it leads Dielectric 152 may include tin, tin alloy, conducting resinl (ACF), other materials appropriate or combinations of the above.In some embodiments In, it may include welding processing procedure (soldering by the processing procedure that luminescence unit 150 is bonded to conductive pad 146a and 146b Process), but the application is not limited thereto.
In some embodiments, conducting medium can be not provided between luminescence unit 150 and conductive pad 146a and 146b 152, the connection features of luminescence unit 150 can directly contact conductive pad (such as: 146a and 146b).It, can in these embodiments Make the connection features and conductive pad (example of luminescence unit 150 using eutectic bonding processing procedure (eutectic bonding process) Eutectic reaction occurs between such as: 146a and 146b), by luminescence unit 150 be bonded to conductive pad (such as: 146a and 146b).
Fig. 5 shows the sectional view of luminescence unit 150 according to some embodiments.In some embodiments, as shown in figure 5, Luminescence unit 150 may include package substrate 202, and package substrate 202 can be tabular, and the surface of package substrate 202 and internal It may be provided with conductor layer 204,206.In some embodiments, luminescence unit 150 have luminescence chip (such as: light emitting diode Chip) C1, luminescence chip C1 is to be arranged on package substrate 202 in a manner of conducting end downward (face down), and can pass through The suitable material such as connection gasket 210 or tin ball and the conductor layer 204,206 on 202 surface of package substrate are electrically connected.In some realities It applies in example, luminescence unit 150 can be directly electrically connected via its conductor layer 204,206 and conductive pad 146a and conductive pad 146b. In some embodiments, luminescence unit 150 can further include the conductive pad 150a for being set to 206 lower section of conductor layer 204 and conductor layer With conductive pad 150b, and luminescence unit 150 can be via conductor layer 204 and conductor layer 206 and conductive pad 150a and conductive pad 150b is electrically connected to conductive pad 146a and conductive pad 146b.Conductor layer 204, conductor layer 206, connection gasket 210, conductive pad 150a, conductive pad 150b respectively or integrally can be considered the connection features of luminescence unit 150.In some embodiments, including conducting wire The package substrate 202 of layer 204,206 can be used as the support construction of support luminescence chip C1.
Although it should be noted that the luminescence unit 150 in embodiment depicted in Fig. 5 only has a luminescence chip C1, but the application is not limited thereto.In some other embodiments, a luminescence unit 150 may include multiple luminescence chips, Such as in Fig. 6, luminescence unit 150 includes luminescence chip C1, C2, the C3 that can respectively issue feux rouges, green light, blue light.Some In embodiment, luminescence unit 150 also may include packaging plastic 208, packaging plastic 208 may be disposed at luminescence chip (such as: luminescence chip C1, C2 and C3) with the top of package substrate 202.And in some embodiments, packaging plastic 208 is set to the light out of luminescence chip Upper side.For example, the material of packaging plastic 208 can be epoxy (epoxy based resin) or silica resin (silicon), but the application is not limited thereto.In some embodiments, settable on the composite substrate 100 of electronic device 10 There are multiple luminescence units 150.In some embodiments, multiple luminescence units 150 on composite substrate 100 are respectively independent, therefore The package substrate 202 and packaging plastic 208 of one luminescence unit 150 and the package substrate 202 of neighbouring another luminescence unit 150 and envelope Dress glue 208 does not contact with each other.In some embodiments, each independent packaging plastic can correspond to each luminescence chip C1, C2, C3 and set It sets.
Fig. 7 to Figure 10 shows some change case of the application luminescence unit 150.It should be noted that unless stated otherwise, The same or similar element and film layer of these change case and previous embodiment will be indicated with identical symbol, and its material and shape It also can be the same as or similar to the material and forming method of previous embodiment at method.Although in addition, being only painted in Fig. 7 to Fig. 9 One luminescence chip is used as used in explanation, but the actual package of this luminescence unit 150 for not being used to limit the embodiment of the present application Luminescence chip quantity.Furthermore, visual design requirement makes a luminescence unit 150 have any an appropriate number of luminous core Piece simultaneously encapsulates these luminescence chips with packaging plastic 208.
Fig. 7 shows a change case of the application luminescence unit 150.The luminescence unit 150 of embodiment depicted in Fig. 7 with The difference of the luminescence unit 150 of embodiment depicted in Fig. 5 essentially consists in the luminescence unit 150 of embodiment depicted in Fig. 7 Luminescence chip C1 is the surface that package substrate 202 is arranged in a manner of conducting end upward (face up).Depicted in Fig. 7 In embodiment, the conducting end (not being illustrated in figure) on the surface luminescence chip C1 can be electrically connected encapsulation base by conducting wire 214 The conductor layer 204,206 on 202 surface of plate.In Fig. 7, conductor layer 204, conductor layer 206, conducting wire 214 are respectively or entirety can be considered The connection features of luminescence unit 150.
Fig. 8 shows a change case of the application luminescence unit 150.In embodiment depicted in Fig. 8, package substrate 212 have side wall 212a and form a cup-like structure around luminescence chip C1.In luminescence unit 150, luminescence chip C1 can be set It sets in the cavity of package substrate 212 or recess, and the conducting wire being arranged in package substrate 212 is electrically connected by conducting wire 214 Layer 204,206.In addition, the cavity of package substrate 212 or in being recessed settable packaging plastic 208 on luminescence chip C1 and protecting hair Optical chip C1.Package substrate 212 in the embodiment depicted in Fig. 7 and Fig. 8 can have high reflectance, to improve light utilization Rate.In some embodiments, the package substrate 212 including conductor layer 204,206 can be used as the support knot of support luminescence chip C1 Structure.In fig. 8, conductor layer 204, conductor layer 206, conducting wire 214 respectively or integrally can be considered the connection features of luminescence unit 150.
Fig. 9 shows a change case of the application luminescence unit 150.In embodiment depicted in Fig. 9, luminescence chip C1 It is to be encapsulated in such a way that conducting end is directed downwardly, and packaging plastic 208 is set on luminescence chip C1 to form luminescence unit 150.One In a little embodiments, connection gasket 210 exposes from packaging plastic 208, therefore directly can be electrically connected luminescence chip C1 via connection gasket 210 And conductive pad 146a and conductive pad 146b are without the cup-shaped support or package substrate 202 via previous embodiment.Some In embodiment, connection gasket 210 directly contacts conductive pad 146a and conductive pad 146b.In Fig. 9, connection gasket 210 is respectively or whole It can be considered the connection features of luminescence unit 150.
Figure 10 shows the schematic top plan view of a change case of the application luminescence unit 150.Implementation depicted in Figure 10 In example, luminescence unit 150 includes two luminescence chips C2, C3.In some embodiments, luminescence chip C2 and luminescence chip C3 can Issue the different light of color.For example, the capable of emitting blue light of luminescence chip C2 and the capable of emitting green light of luminescence chip C3.Some In embodiment, the packaging plastic 208 of luminescence unit 150 may include encapsulating material 208a and intersperse among encapsulating material 208a (such as: Epoxy or silica resin) in phosphor powder 216 (such as: red phosphors), the blue light issued when luminescence chip and/ Or green light, when being irradiated to phosphor powder 216, some blue light and/or green light can be converted into feux rouges, therefore luminescence unit 150 can produce The raw white light mixed by green light, blue light and feux rouges.In some other embodiments, the luminescence unit 150 of the application is only It include yellow phosphorescence powder with single blue light emitting chip, and in packaging plastic 208, therefore luminescence unit 150 may finally produce Raw white light.In some other embodiments, the luminescence unit 150 of the application only has single blue light emitting chip, And comprising the quantum dot of different-grain diameter in packaging plastic 208, therefore luminescence unit 150 may finally generate the light of different colours. In some other embodiments, it may be provided with quantum dot on the luminescence chip of the luminescence unit 150 of the application.Some other Embodiment in, may include light diffusion particle in the packaging plastic 208 of the luminescence unit 150 of the application to improve out brightness when light The uniformity.The above-mentioned luminescence unit 150 with various packaging plastics or other suitable luminescence units all can be applicable to the application's In various embodiments and change case, repeated no more in this.
Although in some embodiments, can be formed on electronic device 10 it should be understood that not being illustrated in Fig. 2 Other elements (such as: cover board or optical film).For example, above-mentioned cover board can be by glass, tin indium oxide, polyimide, poly- Ethylene terephthalate, other materials appropriate or combinations of the above are formed, but the application is not limited thereto.Citing and Speech, above-mentioned optical film may include diffuser plate (diffuser film), collector lens, other optical films appropriate or above-mentioned group It closes, but the application is not limited thereto.
It should be understood that only showing a luminescence unit of electronic device 10 in Fig. 2 for the sake of for convenience of explanation 150.However, electronic device 10 may include any an appropriate number of luminescence unit 150.In some embodiments, these shine single Member 150 respectively has a packaging plastic 208, and these packaging plastics 208 are separated from each other.And in further embodiments, these shine Unit 150 respectively has a package substrate 202, and these package substrates are separated from each other, but packaging plastic 208 is connected with each other.
It, can be by electronic device (such as: display device) 10 bendings to form curved surface it should be understood that in some embodiments Electronic device (such as: curved-surface display device).Curved surface electronic device in these embodiments may include and 10 phase of electronic device Same or similar technical characteristic, and these curved surface electronic devices should be also included within scope of the present application.
It, can be common by multiple electronic devices 10 (such as: display device) splicing it should be understood that in some embodiments A large-sized electronic device (such as: display device) is formed, and these large-sized electronic devices should also be included in this Shen Please within the scope of.
It should be understood that in some embodiments, on the composite substrate 100 and composite substrate 100 of electronic device 10 Each film layer and element can be used as backlight module.
In summary, it may be provided with the good insulating layer of ductility on the substrate of the electronic device of the embodiment of the present application, because The problem of this is less also easy to produce as ruptured in bending.In addition, in some embodiments, the luminescence unit and substrate of electronic device Between be provided on the whole upper flat insulating layer so that the conductive pad for being used to connect luminescence unit on the whole upper can be located at identical water It is flat, therefore can reduce that luminescence unit engages bad problem with conductive pad and the yield of electronic device can be improved.
The foregoing general description feature of several embodiments, so that fields have usual skill and are better understood the application It is each towards.Fields, which have usual skill, should be appreciated that and can be designed based on the application easily or be modified other Processing procedure and structure, and identical purpose is reached with this and/or reaches the advantage identical as the embodiment introduced herein.Fields Has usual skill it will also be appreciated that these equal structures are without departing from spirit herein and range.Without departing substantially from the application's Under the premise of spirit and scope, various changes, displacement or modification can be carried out to embodiments herein
Each claim of the application can be an other embodiment, and scope of the present application includes each power of the application Benefit requires and the mutual combination of each embodiment.

Claims (12)

1. a kind of electronic device, comprising:
One substrate；
Multiple thin film transistor (TFT)s are set on the substrate；And
Multiple luminescence units, wherein the one of them of multiple luminescence unit has a packaging plastic and an at least luminescence chip, The packaging plastic is set on the luminescence chip, and the luminescence unit is electrically connected at least one of multiple thin film transistor (TFT).
2. electronic device as described in claim 1, which is characterized in that the luminescence unit has more a connection features, and the hair Optical chip is electrically connected by the connection features and the thin film transistor (TFT).
3. electronic device as claimed in claim 2, which is characterized in that the luminescence unit has more a package substrate, and the hair Optical chip is set on the package substrate.
4. electronic device as claimed in claim 3, which is characterized in that the package substrate has around the side of the luminescence chip Wall.
5. electronic device as described in claim 1, which is characterized in that the packaging plastic includes an encapsulating material and intersperses among this Phosphor powder, quantum dot or light diffusion particle in encapsulating material.
6. electronic device as described in claim 1, further includes:
One insulating layer is set on multiple thin film transistor (TFT)；And
Multiple conductive pads are set on the insulating layer, wherein the one of them of multiple conductive pad passes through through the insulating layer The one of them of one conductive layer and multiple thin film transistor (TFT) is electrically connected.
7. electronic device as claimed in claim 6, further includes a conducting medium luminescence unit is electrically connected and led with this Electrical pad.
8. electronic device as claimed in claim 7, which is characterized in that the method for the conducting medium and the conductive pad in the substrate Line is overlapped on direction.
9. electronic device as claimed in claim 6, which is characterized in that the substrate includes a bendable folding area.
10. electronic device as claimed in claim 9 further includes a conducting wire and is set on the bendable folding area, wherein the conducting wire has There are a wavy edge or at least one opening.
11. electronic device as claimed in claim 9, which is characterized in that the substrate includes adjacent to the one non-of the bendable folding area Bent area, wherein the insulating layer is less than the insulating layer in the thickness on the bendable folding area in the thickness on the non-bent area.
12. electronic device as described in claim 1, which is characterized in that the thin film transistor (TFT) has an active layer, and this is active Layer is not be overlapped in a normal direction of the substrate with the luminescence unit.
CN201811178409.7A 2018-04-19 2018-10-10 Electronic device Pending CN110391252A (en)

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KR1020190040773A KR20190122150A (en) 2018-04-19 2019-04-08 Electronic device
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