CN115732516A

CN115732516A - Electronic device

Info

Publication number: CN115732516A
Application number: CN202211447930.2A
Authority: CN
Inventors: 范俊钦; 林明昌; 陈韵升
Original assignee: Innolux Display Corp
Current assignee: Innolux Corp
Priority date: 2018-04-19
Filing date: 2018-10-10
Publication date: 2023-03-03
Also published as: CN110391252A; KR20190122150A

Abstract

The application provides an electronic device. The electronic device comprises a substrate, a plurality of thin film transistors and a plurality of light-emitting units, wherein the thin film transistors are arranged on the substrate. One of the light emitting units has a packaging adhesive and at least one light emitting chip. The packaging glue is arranged on the light-emitting chip, and the light-emitting unit is electrically connected to at least one of the thin film transistors.

Description

Electronic device

The application is applied for 10 months and 10 days in 2018, has the application number of ' 201811178409.7 ', and is a divisional application of Chinese invention patent application named as ' electronic device

Technical Field

The present disclosure relates to electronic devices, and more particularly, to a display device.

Background

With the development of digital technology, electronic devices have been widely used in various aspects of daily life, such as televisions, notebook computers, mobile phones (e.g., smart phones), and other modern information devices. In addition, electronic devices are being developed to be light, thin, small, and fashionable.

Among various types of electronic devices, light Emitting Diode (LED) display devices are becoming increasingly popular because of their advantages such as high performance and long lifetime.

However, the conventional electronic devices are not satisfactory in all aspects.

Disclosure of Invention

Some embodiments of the present application provide an electronic device. The electronic device comprises a substrate, a plurality of thin film transistors and a plurality of light-emitting units, wherein the thin film transistors are arranged on the substrate. One of the light emitting units has a packaging adhesive and at least one light emitting chip. The packaging glue is arranged on the light-emitting chip, and the light-emitting unit is electrically connected to at least one of the thin film transistors.

The embodiments will be described in detail below with reference to the accompanying drawings.

Drawings

The present application is more fully understood from the following detailed description when read together with the accompanying drawings. It is noted that, in accordance with standard practice in the industry, the features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily expanded or reduced for clarity.

FIG. 1 is a partial cross-sectional view of an electronic device 1 according to some embodiments of the present application.

FIG. 2 is a partial cross-sectional view of an electronic device 10 according to some embodiments of the present application.

Fig. 3 is a partial top view of a conductive line 134a of a conductive layer 134 according to some embodiments of the present application.

FIG. 4 is a partial cross-sectional view of an electronic device 20 according to some embodiments of the present application.

Fig. 5 is a partial cross-sectional view of a light emitting cell 150 according to some embodiments of the present application.

Fig. 6 is a partial top view of a light emitting unit 150 according to some embodiments of the present application.

Fig. 7 is a partial cross-sectional view of a light emitting cell 150 according to some embodiments of the present application.

Fig. 8 is a partial cross-sectional view of a light emitting cell 150 according to some embodiments of the present application.

Fig. 9 is a partial cross-sectional view of a light emitting cell 150 according to some embodiments of the present application.

Fig. 10 is a partial top view of a light emitting unit 150 according to some embodiments of the present application.

Element numbering in the figures:

1. 10, 20-electronic device

17 insulating layer

18-conductive element

37. 42 electrically conductive layer

46a, 46 b-conducting pads

100-composite substrate

102 to sublayer

102 a-opening or recess

4. 104 to the substrate

104 a-non-bending region of the substrate

104 b-bendable region of substrate

106 insulating layer

108 insulating layer

11. 110 active layer

11a, 110 a-source/drain regions

11b, 110 b-channel region

16. 112-gate insulation layer

14. 114 gate layer

116 insulating layer

118-metal layer

120 dielectric layer

124-conductive layer

12. 126-passivation layer

128-bridge element

130 insulating layer

134-conductive layer

134 a-conducting wire

36. 136 insulating layer

38. 138 insulating layer

142 to the conductive layer

44. 144 to insulating layer

146a, 146b to conductive pads

150 to the light-emitting unit

150a, 150 b-conductive pads

52. 152-conductive medium

202-packaging substrate

204. 206-conductor layer

208-packaging adhesive

208a to packaging Material

210-connection pad

212-packaging substrate

212 a-side wall

214-conducting wire

216-phosphor powder

O ₁ 、O ₂ 、O ₃ Opening(s)

T ₁ 、T ₂ 、T ₃ Thickness of

C1, C2, C3-luminous chip

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. The following disclosure describes specific examples of components and arrangements thereof to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the application recites a first feature formed on or above a second feature, it is intended that embodiments may include embodiments in which the first feature is directly in contact with the second feature, embodiments may include embodiments in which additional features are formed between the first feature and the second feature, such that the first feature and the second feature may not be directly in contact.

In addition, the same reference numbers and/or designations may be reused for the different examples disclosed below. These iterations are for simplicity and clarity and are not intended to limit the various embodiments and/or configurations discussed to a particular relationship.

Some examples of the present application will be described below. Additional operations may be provided before, during, and/or after the steps described in such embodiments. Some of the described steps may be replaced or omitted in different embodiments. In addition, although some embodiments of the present application are described below with steps in a particular order, the steps may be performed in other reasonable orders.

Some embodiments of the present application provide electronic devices (e.g., display devices). The electronic device of the embodiment of the application can be provided with the bendable area, and the bendable area can be provided with the insulating layer with good ductility, so that the electronic device is not easy to crack when being bent. In addition, in some embodiments, a substantially flat insulating layer is disposed between the light emitting unit and the substrate of the electronic device, so that the conductive pads for connecting the light emitting units can be substantially at the same level, thereby reducing the problem of poor bonding between the light emitting unit and the conductive pads and improving the yield of the electronic device.

FIG. 1 is a partial cross-sectional view of an electronic device (e.g., a display device) 1 according to an embodiment of the present disclosure. As shown in fig. 1, the electronic device 1 may include a substrate 4. For example, the substrate 4 may be formed of a low-ductility material such as glass, or a high-ductility material such as Polyimide (PI), polyethylene terephthalate (PET), or other suitable materials, but the application is not limited thereto.

With continued reference to fig. 1, in some embodiments, the electronic device 1 may include a gate layer 14 disposed over the substrate 4. In some embodiments, the gate layer 14 may include scan lines. In some embodiments, the gate layer 14 may be formed of a metal, other suitable conductive material, or a combination thereof. The gate layer 14 may be formed by a chemical vapor deposition process, a physical vapor deposition process, other suitable processes, or a combination thereof, but the disclosure is not limited thereto.

With continued reference to fig. 1, in some embodiments, the electronic device 1 may include a gate insulating layer 16 disposed on the gate layer 14. In some embodiments, the gate insulation layer 16 may include silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof. In some embodiments, the gate insulation layer 16 may comprise a high dielectric constant dielectric material. The gate insulation layer 16 may be formed by a chemical vapor deposition process, a spin-on process, an atomic layer deposition process, other suitable processes, or a combination thereof.

With continued reference to fig. 1, in some embodiments, the electronic device 1 may include an active layer 11 disposed on a gate insulation layer 16. In some embodiments, the active layer 11 may include polysilicon, which may be formed by a low temperature polysilicon process, but the present application is not limited thereto. In some other embodiments, the active layer 11 may also include amorphous silicon, indium gallium zinc oxide, other suitable materials, or a combination thereof. In some embodiments, the active layer 11 may include source/drain regions 11a and a channel region 11b. In some embodiments, the electronic device 1 may comprise an insulating layer 17, the insulating layer 17 being disposed on the gate insulating layer 16.

In some embodiments, as shown in fig. 1, the electronic device 1 may include a conductive element 18. In some embodiments, the conductive element 18 is electrically connected to the source/drain region 11 a. For example, the conductive element 18 may be formed of a metal, a transparent conductive material, other suitable conductive materials, or a combination thereof. The gate layer 14, the gate insulating layer 16, the active layer 10 and the conductive element 18 may collectively form a thin film transistor. Fig. 1 shows only one tft of the electronic device 1. In practice, the electronic device 1 may comprise a plurality of thin film transistors.

With continued reference to fig. 1, in some embodiments, the electronic device 1 may include a passivation layer 12 disposed on the conductive element 18. For example, the passivation layer 12 may include silicon nitride, silicon oxide, aluminum oxide, other suitable materials, or combinations thereof, and may be formed by a chemical vapor deposition process, a thermal oxidation process, other suitable processes, or combinations thereof, but the disclosure is not limited thereto.

With continued reference to fig. 1, in some embodiments, the electronic device 1 may include an insulating layer 36 disposed over the passivation layer 12. In some embodiments, the insulating layer 36 is formed of an organic photoresist material to have better ductility. In some embodiments, the insulating layer 36 may be formed by applying a flowable organic photoresist material onto the substrate 4 by a spin-on process, a slit-coating process, and performing a suitable patterning process (e.g., a photolithography process, an etching process, other suitable processes, or a combination thereof). In some embodiments, the insulating layer 36 may be a silicon oxide layer, a silicon nitride layer, or other suitable insulating layer formed by a chemical vapor deposition process or other suitable processes.

With continued reference to fig. 1, in some embodiments, the electronic device 1 may include an insulating layer 38 disposed on the insulating layer 36. The material and formation method of the insulating layer 38 may be the same as or similar to that of the insulating layer 36, and will not be described in detail for the sake of brevity.

In some embodiments, as shown in fig. 1, electronic device 1 may include a conductive layer 37 disposed between insulating layer 36 and insulating layer 38. In some embodiments, conductive layer 37 may comprise a common electrode. For example, the conductive layer 37 may be formed of a metal oxide, a metal, or other suitable conductive material.

In some embodiments, as shown in fig. 1, the electronic device 1 may include a conductive layer 42 disposed over the insulating layer 38. In some embodiments, the conductive layer 42 may include conductive wires, other suitable conductive elements, or a combination thereof. For example, the conductive layer 42 may be formed of a metal or other suitable conductive material. For example, the process of forming the conductive layer 42 may include a physical vapor deposition process, a photolithography process, an etching process, other suitable processes, or a combination thereof.

With continued reference to fig. 1, in some embodiments, the electronic device 1 may include an insulating layer 44 disposed over the insulating layer 38. In some embodiments, the insulating layer 44 may have a top surface that is substantially flat. In some embodiments, the top surface of the insulating layer 44 may be substantially parallel to the top surface of the substrate 4, but the disclosure is not limited thereto. In some embodiments, since the insulating layer 44 has a substantially flat top surface, the conductive pads (e.g., the

conductive pads

46a and 46 b) for connecting the light emitting cells can be substantially at the same level, thereby reducing the problem of poor connection between the light emitting cells and the conductive pads, and further improving the yield of the electronic device.

In some embodiments, the insulating layer 44 may comprise silicon nitride, silicon oxide, other suitable materials, or combinations thereof. In some embodiments, the insulating layer 44 may comprise a polymeric material. In some embodiments, the insulating layer 44 may comprise an organic photoresist material. In some embodiments, the insulating layer 44 may be formed using a chemical vapor deposition process, a thermal oxidation process, other suitable processes, or a combination thereof. In some embodiments, the process of forming the insulating layer 44 may include a spin-on process, a curing process, other suitable processes, or a combination thereof.

With continued reference to fig. 1, in some embodiments, the electronic device 1 may include a conductive pad 46a and a conductive pad 46b. In some embodiments, at least a portion of the insulating layer 44 is located between the conductive pads (e.g., 46a, 46 b). In some embodiments, the top surface of the conductive pad 46a and the top surface of the conductive pad 46b may be substantially at the same level. In some embodiments, the top surface of the conductive pad 46a and the top surface of the conductive pad 46b may be coplanar.

In some embodiments, conductive pad 46a and conductive pad 46b may extend from a top surface of insulating layer 44 into insulating layer 44. In some embodiments, the

conductive pads

46a and 46b may be formed of metal, other suitable conductive materials, or a combination thereof.

In some embodiments, a patterning process (e.g., a photolithography process, an etching process, other suitable processes, or combinations thereof) may be used to form an appropriate opening in the insulating layer 44, and then a physical vapor deposition process, an electroplating process, an electroless plating process, other suitable processes, or combinations thereof may be used to deposit a conductive material in the opening and on the top surface of the insulating layer 44 to form the conductive pad 46a and the conductive pad 46b.

With continued reference to fig. 1, in some embodiments, the electronic device 1 may include a light emitting unit 150 coupled to the

conductive pads

46a and 46b. In some embodiments, the electronic device 1 has a plurality of light emitting units, but only one light emitting unit is depicted in fig. 1 for simplicity. In some embodiments, the light emitting unit 150 may include a light emitting diode, an organic light emitting diode, a micro light emitting diode, a quantum dot light emitting diode, a sub-millimeter light emitting diode, other suitable light emitting units, or a combination thereof. For example, the light emitting unit 150 can be electrically connected to the conductive pad 46a and the conductive pad 46b through the conductive medium 52. For example, the conductive medium 52 may include tin, tin alloy, conductive paste, other suitable materials, or combinations thereof. In some embodiments, the process of bonding the light emitting unit 150 to the

conductive pads

46a and 46b may include a soldering process, such as Surface Mount Technology (SMT), but the disclosure is not limited thereto. In some embodiments, the conductive medium 52 overlaps the

conductive pad

46a or 46b in a top view, but the disclosure is not limited thereto.

In some embodiments, the light emitting unit 150 can be electrically connected to the conductive element 18 through the conductive medium 52, the

conductive pad

46a or 46b and the conductive layer 42. The thin film transistor can control the light emitting performance of the light emitting unit 150. In some embodiments, the light emitting device 150 is electrically connected to a plurality of thin film transistors.

FIG. 2 is a partial cross-sectional view of an electronic device (e.g., a display device) 10 according to an embodiment of the present disclosure. As shown in fig. 2, in some embodiments, the electronic device 10 may include a composite substrate 100. In some embodiments, the composite substrate 100 may include a transparent substrate, but the present application is not limited thereto. In some embodiments, the composite substrate 100 may include a sublayer 102, a substrate 104, and a thin film transistor disposed on the substrate 104. For example, the thin film transistor may be formed of an active layer 110, a gate insulating layer 112, and a gate layer 114, which will be described later. In some embodiments, the composite substrate 100 may include a substrate 104 and a thin film transistor disposed on the substrate 104 but not the sub-layer 102.

As shown in fig. 2, the substrate 104 may include a non-bending region 104a and a bending region 104b. In some embodiments, the bendable region 104b is adjacent to the non-bendable region 104 a. In detail, in the embodiments, the bendable region 104b of the substrate 104 of the electronic device 10 and the films and elements formed on the bendable region 104b can be bent.

In some embodiments, a thin film transistor may be disposed in the non-bending region 104a of the substrate 104, and a conductive line may be disposed in the bending region 104b of the substrate 104, but the disclosure is not limited thereto.

In some embodiments, the substrate 104 may be a flexible layer (flex layer). In some embodiments, the ductility of the substrate 104 may be greater than the ductility of the secondary layer 102. In some embodiments, the strength (e.g., tensile strength) of the sublayer 102 may be greater than the strength of the substrate 104.

In some embodiments, the sub-layer 102 and the substrate 104 may be formed of different materials. For example, the sub-layer 102 may be formed of glass, and the substrate 104 may be formed of Polyimide (PI) or polyethylene terephthalate (PET), but the disclosure is not limited thereto. In some other embodiments, the sub-layer 102 and the substrate 104 may be formed of any other suitable material.

In some embodiments, the substrate 104 may be formed on the sub-layer 102 by spin-on coating (spin-on coating), rolling, vacuum bonding, chemical Vapor Deposition (CVD), other suitable methods, or combinations thereof, but the disclosure is not limited thereto.

In some embodiments, as shown in fig. 2, one or more openings (or recesses) 102a may be formed below the bendable region 104b of the substrate 104, thereby reducing the problem of cracking due to the lower ductility of the sub-layer 102 when bending the composite substrate 100.

In some embodiments, as shown in fig. 2, the opening (or recess) 102a may expose the substrate 104 of the composite substrate 100, but the disclosure is not limited thereto. In some other embodiments, the opening (or recess) 102a may not expose the substrate 104 of the composite substrate 100.

With continued reference to fig. 2, in some embodiments, the electronic device 10 may include an insulating layer 106 disposed over the substrate 104. In some embodiments, the insulating layer 106 blocks moisture and oxygen, thereby reducing oxidation of the layers disposed over the insulating layer 106. For example, the insulating layer 106 may comprise silicon nitride, silicon oxide, aluminum oxide, other suitable materials, or combinations thereof, and may be formed by a chemical vapor deposition process, a thermal oxidation process, other suitable processes, or combinations thereof, but the disclosure is not limited thereto.

In some embodiments, after the insulating layer 106 is formed, a patterning process may be performed on the insulating layer 106 to form an opening O in the insulating layer 106 ₁ A part of (a). In some embodiments, the opening O ₁ Can be located on the bendable region 104b of the substrate 104 and/or in the bendable region 104b of the substrate 104. In some embodiments, the opening O ₁ The top surface of the substrate 104 may be exposed. In some embodiments, in the top view, the opening O ₁ May be substantially elliptical, square, rectangular, circular, oblong (oblong), triangular, polygonal, irregular, other suitable shapes, or combinations thereof.

In some embodiments, the patterning process may include a photolithography process, an etching process, other suitable processes, or a combination thereof. For example, the photolithography process may include photoresist coating (e.g., spin coating), soft baking (soft bathing), mask alignment (mask alignment), exposure (exposure), post-exposure baking (post-exposure), photoresist development (depraving photoresist), rinsing (rising), drying (e.g., hard baking), other suitable processes, or a combination thereof. For example, the etching process may include a dry etching process (e.g., a plasma etching process), a wet etching process, other suitable processes, or a combination thereof.

With continued reference to fig. 2, in some embodiments, the electronic device 10 may include an insulating layer 108 disposed over the insulating layer 106. The insulating layer 108 may comprise silicon nitride, silicon oxide, aluminum oxide, other suitable materials, or combinations thereof, and may be formed by using a chemical vapor deposition process, a thermal oxidation process, other suitable processes, or combinations thereof, but the disclosure is not limited thereto. In some embodiments, the insulating layer 106 and the insulating layer 108 can be formed of the same material, but the disclosure is not limited thereto. In some other embodiments, the insulating layer 106 and the insulating layer 108 may be formed of different materials (e.g., the insulating layer 106 is formed of silicon oxide and the insulating layer 108 is formed of silicon nitride).

In some embodiments, after the insulating layer 108 is formed, a patterning process may be performed on the insulating layer 108 to form an opening O in the insulating layer 108 ₁ A part of (a). In some embodiments, the opening O in the insulating layer 108 ₁ And the opening O in the insulating layer 106 ₁ Are in communication. In some embodiments, the patterning process may include a photolithography process, an etching process, other suitable processes, or a combination thereof.

With continued reference to fig. 2, in some embodiments, the electronic device 10 may include an active layer 110 disposed on the insulating layer 108. In some embodiments, the active layer 110 may include polysilicon, which may be formed by a Low Temperature Polysilicon (LTPS) process, but the disclosure is not limited thereto. In some other embodiments, the active layer 110 may also include Amorphous silicon (a-Si), indium Gallium Zinc Oxide (IGZO), other suitable materials, or combinations thereof.

In some embodiments, the active layer 110 may include source/drain regions 110a and a channel region 110b of a thin film transistor. In some embodiments, the source/drain region 110a is a source/drain region of an n-type TFT, and thus the source/drain region 110a may be doped with P, as, sb, other suitable n-type dopants, or combinations thereof. In some other embodiments, the source/drain region 110a is a source/drain region of a p-type thin film transistor, and thus the source/drain region 110a may be doped with boron, indium, other suitable p-type dopants, or a combination thereof. In some embodiments, the active layer 110 may be implanted with an appropriate dopant to form source/drain regions 110a of the tft.

Referring to fig. 2, in some embodiments, an electronic device10 may include a gate insulating layer 112 disposed over the active layer 110. In some embodiments, the gate insulating layer 112 may include silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof. In some embodiments, the gate insulation layer 112 may comprise a high dielectric constant (high-k) dielectric material, such as: laO, alO, zrO, tiO, ta ₂ O ₅ 、Y ₂ O ₃ 、SrTiO ₃ (STO)、BaTiO ₃ (BTO)、BaZrO、HfO ₂ 、HfO ₃ 、HfZrO、HfLaO、HfSiO、HfSiON、LaSiO、AlSiO、HfTaO、HfTiO、HfTaTiO、HfAlON、(Ba,Sr)TiO ₃ (BST)、Al ₂ O ₃ Other suitable materials, or combinations thereof. The gate insulating layer 112 may be formed by a chemical vapor deposition process, a spin-on process, an atomic layer deposition process, other suitable processes, or a combination thereof. For example, the cvd process may include a low pressure cvd (low pressure chemical vapor deposition), a low temperature cvd (low temperature chemical vapor deposition), a Rapid Thermal Cvd (RTCVD), a Plasma Enhanced Cvd (PECVD), other suitable cvd processes, or a combination thereof.

In some embodiments, after forming the gate insulating layer 112, a patterning process may be performed on the gate insulating layer 112 to form an opening O in the gate insulating layer 112 ₁ A part of (a). In some embodiments, the opening O in the gate insulating layer 112 ₁ And the opening O in the insulating layer 108 ₁ Are in communication. In some embodiments, the patterning process may include a photolithography process, an etching process, other suitable processes, or a combination thereof.

With continued reference to fig. 2, in some embodiments, the electronic device 10 may include a gate layer 114 disposed over the gate insulating layer 112. In some embodiments, the active layer 110, the gate insulating layer 112, and the gate layer 114 may collectively form a thin film transistor. In some embodiments, the current signal transmitted to a light-emitting unit (e.g., the light-emitting unit 150 described later) of the electronic device 10 can be controlled via the thin film transistor, so as to control the light-emitting performance of the light-emitting unit of the electronic device 10. In some embodiments, the gate layer 114 may include or be electrically connected to scan lines (scan lines) of the electronic device 10.

In some embodiments, the gate layer 114 may include a metal, a metal nitride, a metal oxide, other suitable conductive materials, or combinations thereof. For example, the metal may include copper (copper), molybdenum (molybdenum), tungsten (tungsten), titanium (titanium), tantalum (tantalum), platinum (platinum), hafnium (hafnium), other suitable metals, or combinations thereof. For example, the metal nitride may include molybdenum nitride (molybdenum nitride), tungsten nitride (tungsten nitride), titanium nitride (titanium nitride), tantalum nitride (tantalum nitride), other suitable metal nitrides, or combinations thereof. For example, the metal oxide may include ruthenium oxide (ruthenium oxide), indium tin oxide (indium tin oxide), other suitable metal oxides, or combinations thereof. The gate layer 114 may be formed by a chemical vapor deposition process, a physical vapor deposition process (e.g., a sputtering process or an evaporation process), other suitable processes, or a combination thereof, but the disclosure is not limited thereto.

With continued reference to fig. 2, in some embodiments, the electronic device 10 may include an insulating layer 116 disposed over the gate layer 114. In some embodiments, the insulating layer 116 can function as an insulating layer of a metal-insulator-metal (MIM) capacitor structure.

For example, the insulating layer 116 may comprise silicon nitride, silicon oxide, aluminum oxide, other suitable materials, or combinations thereof, and may be formed by a chemical vapor deposition process, a thermal oxidation process, other suitable processes, or combinations thereof, but the disclosure is not limited thereto.

In some embodiments, after the insulating layer 116 is formed, a patterning process may be performed on the insulating layer 116 to form an opening O in the insulating layer 116 ₁ A part of (a). In some embodiments, opening O in insulating layer 116 ₁ And the opening O in the gate insulating layer 112 ₁ Partial phase ofAnd (4) communicating. In some embodiments, the patterning process may include a photolithography process, an etching process, other suitable processes, or a combination thereof.

With continued reference to fig. 2, in some embodiments, the electronic device 10 may include a metal layer 118 disposed on the insulating layer 116. In some embodiments, the gate layer 114, the insulating layer 116, and the metal layer 118 may collectively form a metal-insulator-metal (MIM) capacitor structure. The material and formation method of the metal layer 118 may be the same as or similar to those of the gate layer 114. For the sake of brevity, no detailed description will be provided herein.

With continued reference to fig. 2, in some embodiments, the electronic device 10 may include a dielectric layer 120 disposed over the insulating layer 116 and the metal layer 118. In some embodiments, the dielectric layer 120 may comprise silicon oxide, silicon nitride, other suitable materials, or combinations thereof, and may be formed by a chemical vapor deposition process, a thermal oxidation process, other suitable processes, or combinations thereof, but the disclosure is not limited thereto.

In some embodiments, after forming the dielectric layer 120, the dielectric layer 120 may be patterned to form an opening O in the dielectric layer 120 ₁ A part of (a). In some embodiments, the opening O in the dielectric layer 120 ₁ And the opening O in the insulating layer 116 ₁ Are in communication. In some embodiments, the patterning process may include a photolithography process, an etching process, other suitable processes, or a combination thereof.

With continued reference to fig. 2, in some embodiments, the electronic device 10 may include a conductive layer 124 disposed over the dielectric layer 120. In some embodiments, the conductive layer 124 may include or be electrically connected to data lines (data lines) of the electronic device 10.

In some embodiments, the electronic device 10 may include one or more vias through the dielectric layer 120, the insulating layer 116, and/or the gate insulating layer 112, through which the conductive layer 124 is electrically connected to the active layer 110. In some embodiments, the conductive layer 124 may directly contact the source/drain region 110a of the active layer 110. In some embodiments, the metal layer 118 may be electrically connected to the active layer 110 through the conductive layer 124. In some embodiments, conductive layer 124 may include copper, molybdenum, tungsten, titanium, aluminum, tantalum, platinum, hafnium, other suitable conductive materials, or alloys thereof.

In some embodiments, one or more openings may be formed in the dielectric layer 120, the insulating layer 116, and/or the gate insulating layer 112 by a patterning process (e.g., a photolithography process, an etching process, other suitable processes, or a combination thereof), and then the one or more openings may be filled with a conductive material by a physical vapor deposition process (e.g., sputtering or evaporation), an electroplating process, other suitable processes, or a combination thereof, so as to form the conductive layer 124 in the one or more openings.

In some embodiments, a conductive blanket layer may be formed on the dielectric layer 120 and the conductive layer 124 by a physical vapor deposition process (e.g., sputtering or evaporation), an electroplating process, other suitable processes, or a combination thereof, and then a patterning process (e.g., a photolithography process, an etching process, other suitable processes, or a combination thereof) may be performed on the conductive blanket layer to form the patterned conductive layer 124.

With continued reference to fig. 2, in some embodiments, the electronic device 10 may include a passivation layer 126 disposed over the conductive layer 124 and the dielectric layer 120. For example, the passivation layer 126 may include silicon nitride, silicon oxide, aluminum oxide, other suitable materials, or combinations thereof, and may be formed by a chemical vapor deposition process, a thermal oxidation process, other suitable processes, or combinations thereof, but the disclosure is not limited thereto.

In some embodiments, after forming the passivation layer 126, the passivation layer 126 may be subjected to a patterning process to form an opening O in the passivation layer 126 ₁ A part of (a). In some embodiments, the opening O in the passivation layer 126 ₁ And the opening O in the dielectric layer 120 ₁ Are in communication. In some embodiments, the patterning process may include a photolithography process, an etching process, other suitable processes, or a combination thereof.

With continued reference to fig. 2, in some embodiments, the electronic device 10 may include one or more bridging elements 128 disposed over the passivation layer 126 and penetrating the passivation layer 126. In some embodiments, the bridging element 128 and the conductive layer 124 may be formed of different materials, but the present application is not limited thereto.

In some embodiments, the bridge element 128 may include Indium Tin Oxide (ITO), tin oxide (SnO), indium Zinc Oxide (IZO), indium Gallium Zinc Oxide (IGZO), indium Tin Zinc Oxide (ITZO), antimony Tin Oxide (ATO), antimony Zinc Oxide (AZO), other suitable transparent conductive materials, or combinations thereof. In some other embodiments, the bridging element 128 may include copper, molybdenum, tungsten, titanium, aluminum, tantalum, platinum, hafnium, other suitable metal materials, or combinations thereof, but the disclosure is not limited thereto.

In some embodiments, one or more suitable openings may be formed in the passivation layer 126 using a patterning process (e.g., a photolithography process, an etching process, other suitable processes, or combinations thereof), and then one or more of the openings may be filled with a suitable conductive material and a conductive blanket layer may be formed on the passivation layer 126 using a physical vapor deposition process (e.g., evaporation or sputtering), an atomic layer deposition process, other suitable processes, or combinations thereof, and then the conductive blanket layer may be patterned (e.g., a photolithography process, an etching process, other suitable processes, or combinations thereof) to form the bridge element 128.

With continued reference to fig. 2, in some embodiments, the electronic device 10 may include an insulating layer 130 disposed on the passivation layer 126 and the bendable region 104b. In some embodiments, the insulating layer 130 may fill the opening O ₁ . In some embodiments, the insulating layer 130 formed of the organic photoresist material has better ductility than the insulating layer 106, the insulating layer 108, the gate insulating layer 112, the insulating layer 116, the dielectric layer 120, and/or the passivation layer 126. In some embodiments, the opening O is filled with a ductile insulating layer 130 ₁ (i.e., a portion of the insulating layer 106, the insulating layer 108, the gate insulating layer 112, the insulating layer 116, the dielectric layer 120, and/or the passivation layer 126 is replaced with a portion of the insulating layer 130), so cracking of the electronic device 10 during bending can be reduced.

In some embodiments, a spin coating process, a slit coating process (slit coating) may be used to coat the flowable organic photoresist material on the non-bending region 104a and the bending region 104b of the substrate 104, and then an appropriate patterning process (e.g., a photolithography process, an etching process, other appropriate processes, or a combination thereof) may be performed to form the insulating layer 130. In some embodiments, the organic photoresist material used to form the insulating layer 130 has good fluidity, so that the difference in height of the surface of the structure formed by the above layers can be filled up, and the surface of the structure can be planarized. Accordingly, the insulating layer 130 may have a substantially flat top surface. In some embodiments, the top surface of the insulating layer 130 may be substantially parallel to the top surface of the substrate 104, but the disclosure is not limited thereto.

As shown in FIG. 2, the insulating layer 130 on the non-bending region 104a of the substrate 104 (e.g., the insulating layer 130 on the active layer 110) may have a thickness T ₁ The insulating layer 130 on the bendable region 104b of the substrate 104 may have a thickness T ₂ . In some embodiments, the thickness T ₁ Can be less than thickness T ₂ However, the present application is not limited thereto.

With continued reference to fig. 2, in some embodiments, the electronic device 10 may include a conductive layer 134 disposed over the insulating layer 130. In some embodiments, the conductive layer 134 may include conductive wires, conductive pads, other suitable conductive elements, or a combination thereof.

In some embodiments, the electronic device 10 may include one or more vias disposed in the insulating layer 130, through which the conductive layer 134 is electrically connected to the bridging element 128. In some embodiments, the conductive layer 134 is electrically connected to the conductive layer 124 through the bridging element 128.

In some embodiments, conductive layer 134 may comprise molybdenum, tungsten, titanium, aluminum, tantalum, platinum, hafnium, copper, other suitable conductive materials, or combinations thereof. In some embodiments, conductive layer 134 may comprise a stack of multiple metal layers (e.g., a Ti/Al/Ti stack).

In some embodiments, a photolithography process may be used to form one or more openings in the insulating layer 130, and then a physical vapor deposition process (e.g., sputtering or evaporation), an electroplating process, other suitable processes, or a combination thereof may be used to fill the one or more openings with a conductive material to form the conductive layer 134 in the one or more openings. For example, the photolithography process may include a developing process using a developing solution. In some embodiments in which the bridging elements 128 are formed of the transparent conductive material (e.g., ITO) described above, the bridging elements 128 can reduce the damage to the underlying film (e.g., the conductive layer 124) caused by the developer since the transparent conductive material is less susceptible to damage by the developer.

In some embodiments, a conductive blanket layer may be formed over the insulating layer 130 and the conductive layer 134 using a physical vapor deposition process (e.g., sputtering or evaporation), an electroplating process, other suitable processes, or a combination thereof, and then a patterning process (e.g., a photolithography process, an etching process, other suitable processes, or a combination thereof) may be performed on the conductive blanket layer to form the patterned conductive layer 134.

In some embodiments, as shown in fig. 2 and 3, the conductive layer 134 includes a conductive line 134a and one or more openings O on the bendable region 104b ₂ . For example, the opening O ₂ May be formed in the conductive line 134a of the conductive layer 134 (as shown in fig. 3). In some embodiments, the wire 134a has a wavy edge. In some embodiments, in the top view, at least one opening O ₂ Can be completely overlapped or partially overlapped with the opening O ₁ . In some embodiments, the undulating edge or opening O of the wire 134a ₂ Cracking of conductive layer 134 when electronic device 10 is bent can be reduced.

For example, one or more openings O may be formed in the conductive layer 134 using a patterning process (e.g., a photolithography process, an etching process, other suitable processes, or a combination thereof) ₂ . In some embodiments, in the top view, the opening O ₂ May be substantially oval, square, rectangular, circular, oblong, triangular, polygonal, irregular, other suitable shapes, or combinations thereof.

Please refer to fig. 2, which is a flowchart ofIn some embodiments, the electronic device 10 may include an insulating layer 136 disposed over the conductive layer 134 and the insulating layer 130. In some embodiments, the insulating layer 136 may fill the opening O ₂ 。

In some embodiments, the material and formation method of the insulating layer 136 may be the same as or similar to those of the insulating layer 130. For the sake of brevity, no detailed description will be provided herein.

In some embodiments, the insulating layer 136 may have a substantially flat top surface due to the good flowability of the organic photoresist used to form the insulating layer 136. In some embodiments, the top surface of the insulating layer 136 may be substantially parallel to the top surface of the substrate 104, but the disclosure is not limited thereto.

As shown in FIG. 2, the insulating layer 136 may have a thickness T ₃ . For example, the thickness T ₃ May be 1 to 5 μm, but the present application is not limited thereto.

With continued reference to fig. 2, in some embodiments, the electronic device 10 may include an insulating layer 138. In some embodiments, insulating layer 138 may extend from a top surface of insulating layer 136 into insulating layer 136. In some embodiments, the insulating layer 138 may comprise a suitable insulating material such as silicon nitride, or a combination thereof. In some embodiments, insulating layer 138 and insulating layer 136 may be formed of different materials.

For example, the thickness of the insulating layer 138 may be 0.1 to 1 μm, but the disclosure is not limited thereto. In some embodiments, a photolithography process may be used to form one or more appropriate openings in the insulating layer 136, and then a chemical vapor deposition process, other appropriate process, or a combination thereof may be used to deposit an insulating material on the top surface of the insulating layer 136 and in the one or more openings to form the insulating layer 138.

In some embodiments, after the insulating layer 138 is formed, the insulating layer 138 may be patterned to form an opening O in the insulating layer 138 ₃ A part of (a). In some embodiments, the opening O ₃ May be located on the bendable region 104b. In some embodiments, in the top view, the opening O ₃ Can overlap or partially overlap the opening O ₁ . In some embodiments, in the top view, the opening O ₃ Can overlap or partially overlap at least one opening O ₂ . In some embodiments, in the top view, the opening O ₃ May be substantially oval, square, rectangular, circular, oblong, triangular, polygonal, irregular, other suitable shapes, or combinations thereof. For example, the patterning process may include a photolithography process, an etching process, other suitable processes, or a combination thereof.

With continued reference to fig. 2, in some embodiments, the electronic device 10 may include a conductive layer 142 disposed over the insulating layer 136. In some embodiments, the conductive layer 142 can include conductive wires, conductive pads, other suitable conductive elements, or a combination thereof. In some embodiments, the conductive layer 142 is electrically connected to the conductive layer 134 through the opening.

In some embodiments, the conductive layer 142 may include molybdenum, tungsten, titanium, aluminum, tantalum, platinum, hafnium, copper, chromium, lead, nickel, zinc, indium, gold, alloys thereof, other suitable conductive materials, or combinations thereof. In some embodiments, the conductive layer 142 may include a stack structure formed by a plurality of metal layers (e.g., a Mo/Cu stack structure). For example, the thickness of the conductive layer 142 may be 0.5 to 5 μm, but the application is not limited thereto.

In some embodiments, the one or more openings may be formed in the insulating layer 136 by a photolithography process, and then the one or more openings may be filled with a conductive material by a physical vapor deposition process (e.g., sputtering or evaporation), an electroplating process, other suitable processes, or a combination thereof to form the conductive layer 142 in the one or more openings.

In some embodiments, a conductive blanket layer may be formed on the insulating layer 136 and the conductive layer 142 by a physical vapor deposition process (e.g., sputtering or evaporation), an electroplating process, another suitable process, or a combination thereof, and then a patterning process (e.g., a photolithography process, an etching process, another suitable process, or a combination thereof) may be performed on the conductive blanket layer to form the patterned conductive layer 142.

In some embodiments, the insulating layer 138 disposed between the conductive layer 142 and the insulating layer 136 can serve as an adhesion layer, which can reduce the occurrence of the conductive layer 142 falling off from the insulating layer 136.

With continued reference to fig. 2, in some embodiments, the electronic device 10 may include an insulating layer 144 disposed over the insulating layer 138 and the conductive layer 142. In some embodiments, the insulating layer 144 may have a top surface that is substantially flat. In some embodiments, the top surface of the insulating layer 144 may be substantially parallel to the top surface of the substrate 104, but the disclosure is not limited thereto. In some embodiments, since the insulating layer 144 has a substantially flat top surface, the conductive pads (e.g., the

conductive pads

146a and 146 b) for connecting the light emitting cells can be substantially at the same level, thereby reducing poor connection between the light emitting cells and the conductive pads and improving yield of the electronic device.

In some embodiments, the insulating layer 144 may comprise silicon nitride, silicon oxide, other suitable materials, or combinations thereof. In some embodiments, the insulating layer 144 may comprise a polymeric material. In some embodiments, the insulating layer 144 may comprise an organic photoresist material.

In some embodiments, the insulating layer 144 may be formed by a chemical vapor deposition process, a thermal oxidation process, other suitable processes, or a combination thereof. In some embodiments, the process of forming the insulating layer 144 may include a spin-on process, a curing process, other suitable processes, or a combination thereof.

In some embodiments, after the insulating layer 144 is formed, the insulating layer 144 may be patterned to form an opening O in the insulating layer 144 ₃ A part of (a). In some embodiments, opening O in insulating layer 144 ₃ And the opening O in the insulating layer 138 ₃ Are connected. For example, the patterning process may include a photolithography process, an etching process, other suitable processes, or a combination thereof.

Referring to fig. 2, in some embodiments, the electronic device 10 may include the conductive pad 146a and the conductive pad 146b. In some embodiments, at least a portion of the insulating layer 144 is located between the conductive pads (e.g., conductive pad 146a and conductive pad 146 b). In some embodiments, the

conductive pads

146a and 146b may be substantially at the same level, so that poor connection between the light emitting unit (e.g., the light emitting unit 150) and the

conductive pads

146a and 146b can be reduced, thereby improving yield of the electronic device. In some embodiments, the top surface of the conductive pad 146a and the top surface of the conductive pad 146b may be substantially at the same level. In some embodiments, the top surface of conductive pad 146a and the top surface of conductive pad 146b may be coplanar.

In some embodiments, conductive pad 146a and conductive pad 146b may extend from a top surface of insulating layer 144 into insulating layer 144. In some embodiments, the

conductive pads

146a and 146b may comprise molybdenum, tungsten, titanium, aluminum, tantalum, platinum, hafnium, copper, chromium, lead, nickel, zinc, indium, gold, alloys thereof, other suitable conductive materials, or combinations thereof. In some embodiments, the

conductive pads

146a and 146b may comprise a stack of metal layers (e.g., ni/Au stack). In some embodiments, the outermost layers of the

conductive pads

146a and 146b may be an oxidation resistant layer formed by a metal with better oxidation resistance, such as platinum, gold, palladium, or a combination thereof, but the disclosure is not limited thereto.

In some embodiments, a patterning process (e.g., a photolithography process, an etching process, other suitable processes, or combinations thereof) may be used to form an appropriate opening in the insulating layer 144, and then a physical vapor deposition process (e.g., sputtering or evaporation), an electroplating process, an electroless plating process, other suitable processes, or combinations thereof may be used to deposit a conductive material in the opening and on the top surface of the insulating layer 144 to form the conductive pad 146a and the conductive pad 146b.

With continued reference to fig. 2, in some embodiments, the electronic device 10 may include a light emitting unit 150 coupled to the

conductive pads

146a and 146b. In some embodiments, the light emitting unit 150 may include a light emitting diode (e.g., a blue light emitting diode, a red light emitting diode, or a green light emitting diode), an organic light emitting diode, a Micro light emitting diode (Micro LED), a Quantum Dot light emitting diode (Quantum Dot LED), a sub-millimeter light emitting diode (Mini LED), other suitable light emitting units, or a combination thereof.

In some embodiments, the light emitting unit 150 can be electrically connected to the active layer 110 through the

conductive pads

146a and 146b, the conductive layer 142, the conductive layer 134, the conductive layer 124, and the source/drain region 110a.

FIG. 4 illustrates an electronic device 20 (e.g., a display device) according to some embodiments of the present disclosure. One of the differences between the electronic device 20 and the electronic device 10 is that the light emitting unit 150 of the electronic device 20 is laterally separated from the active layer 110. In some embodiments, the active layer 110 and the light emitting unit 150 do not overlap in a normal direction, which is a direction perpendicular to the top surface of the substrate 104 in the present application. In some embodiments, since the light emitting unit 150 of the electronic device 20 is laterally separated from the active layer 110, the active layer 110 may be crushed by the light emitting unit 150 when the light emitting unit 150 is bonded to the

conductive pads

146a and 146b.

In some embodiments, the light emitting unit 150 may include a main portion (e.g., a light emitting chip C1 described later) and a connection feature. In some embodiments, the main portion of the light emitting unit 150 includes a quantum well structure and may have good light emitting efficiency. For example, the main portion of the light emitting unit 150 may include gallium nitride, aluminum nitride, gallium arsenide, indium gallium phosphide, aluminum gallium arsenide, indium phosphide, indium aluminum arsenide, indium gallium aluminum phosphide, other suitable semiconductor materials, or a combination thereof, but the disclosure is not limited thereto.

The light emitting unit 150 can be electrically connected to the

conductive pads

146a and 146b through the connection features thereof. In other words, the light emitting unit 150 can be electrically connected to the thin film transistor through the connection feature thereof. In some embodiments, the connection features of the light emitting unit 150 may include a wiring layer, a conductive pad, an electrode, a bump, other suitable connection features, or a combination thereof. For example, the connection feature of the light emitting unit 150 may include a metal material (e.g., copper, tungsten, silver, tin, nickel, chromium, titanium, lead, gold, bismuth, antimony, zinc, zirconium, magnesium, indium, tellurium, gallium, or other suitable metals), an alloy thereof, other suitable conductive materials, or a combination thereof, but the disclosure is not limited thereto.

In some embodiments, the light emitting unit 150 may be electrically connected to the

conductive pads

146a and 146b through the conductive medium 152. In some embodiments, the conductive medium 152 overlaps the

conductive pad

146a or 146b in the normal direction. In some embodiments, the conductive medium 152 directly contacts the

conductive pads

146a and 146b and the connection features of the light emitting unit 150. For example, the conductive medium 152 may include tin, tin alloy, conductive paste (ACF), other suitable materials, or combinations thereof. In some embodiments, the process of bonding the light emitting unit 150 to the

conductive pads

146a and 146b may include a soldering process (soldering process), but the disclosure is not limited thereto.

In some embodiments, no conductive medium 152 may be disposed between the light emitting unit 150 and the

conductive pads

146a and 146b, and the connection features of the light emitting unit 150 may directly contact the conductive pads (e.g., 146a and 146 b). In such embodiments, a eutectic bonding process may be used to bond the light emitting cell 150 to the conductive pads (e.g., 146a and 146 b) by causing a eutectic reaction between the connection features of the light emitting cell 150 and the conductive pads (e.g., 146a and 146 b).

FIG. 5 illustrates a cross-sectional view of a light emitting cell 150, according to some embodiments. In some embodiments, as shown in fig. 5, the light emitting unit 150 may include a package substrate 202, the package substrate 202 may be a flat plate, and the surface and the inside of the package substrate 202 may be provided with

wire layers

204 and 206. In some embodiments, the light emitting unit 150 has a light emitting chip (e.g., a light emitting diode chip) C1, and the light emitting chip C1 is disposed on the package substrate 202 with its conductive terminal facing down (face down), and is electrically connected to the wire layers 204 and 206 on the surface of the package substrate 202 through a bonding pad 210 or a solder ball or other suitable material. In some embodiments, the light emitting unit 150 can be electrically connected to the conductive pad 146a and the conductive pad 146b directly through the wiring layers 204 and 206 thereof. In some embodiments, the light emitting unit 150 may further include a conductive pad 150a and a conductive pad 150b disposed below the

conductive layers

204 and 206, and the light emitting unit 150 may be electrically connected to the conductive pad 146a and the conductive pad 146b through the

conductive layers

204 and 206, and the conductive pad 150a and the conductive pad 150 b. The wiring layer 204, the wiring layer 206, the connection pad 210, the conductive pad 150a, and the conductive pad 150b can be regarded as connection features of the light emitting unit 150, respectively or as a whole. In some embodiments, the package substrate 202 including the wire layers 204, 206 may serve as a support structure for supporting the light emitting chip C1.

It should be noted that although the light emitting unit 150 in the embodiment shown in fig. 5 has only one light emitting chip C1, the present application is not limited thereto. In some other embodiments, a light emitting unit 150 may include a plurality of light emitting chips, for example, in fig. 6, the light emitting unit 150 includes light emitting chips C1, C2, and C3 that can emit red light, green light, and blue light, respectively. In some embodiments, the light emitting unit 150 may further include a packaging adhesive 208, and the packaging adhesive 208 may be disposed above the light emitting chips (e.g., the light emitting chips C1, C2, and C3) and the package substrate 202. In some embodiments, the encapsulant 208 is disposed over the light-emitting side of the light-emitting chip. For example, the material of the encapsulation adhesive 208 may be epoxy-based resin (epoxy resin) or silicone resin (silicone), but the application is not limited thereto. In some embodiments, a plurality of light emitting units 150 may be disposed on the composite substrate 100 of the electronic device 10. In some embodiments, the light emitting units 150 on the composite substrate 100 are independent from each other, so the package substrate 202 and the package adhesive 208 of one light emitting unit 150 do not contact with the package substrate 202 and the package adhesive 208 of another adjacent light emitting unit 150. In some embodiments, each of the independent encapsulation glues may be disposed corresponding to each of the light emitting chips C1, C2, and C3.

Fig. 7 to 10 illustrate some variations of the light emitting unit 150 of the present application. It should be noted that, unless otherwise specified, elements and layers of these variations which are the same or similar to those of the previous embodiments are indicated by the same symbols, and the materials and formation methods thereof may also be the same or similar to those of the previous embodiments. In addition, although only one light emitting chip is shown in fig. 7 to 9 for illustration, this is not intended to limit the number of light emitting chips of the actual package of the light emitting unit 150 according to the embodiment of the present application. Further, a light emitting unit 150 may have any suitable number of light emitting chips according to design requirements and the light emitting chips are packaged by the packaging adhesive 208.

Fig. 7 shows a variation of the light-emitting unit 150 of the present application. The difference between the light emitting unit 150 of the embodiment shown in fig. 7 and the light emitting unit 150 of the embodiment shown in fig. 5 is that the light emitting chip C1 of the light emitting unit 150 of the embodiment shown in fig. 7 is disposed on the surface of the package substrate 202 with its conductive end facing upward (face up). In the embodiment shown in fig. 7, the conductive terminals (not shown) on the surface of the light emitting chip C1 can be electrically connected to the conductive wire layers 204 and 206 on the surface of the package substrate 202 through the conductive wires 214, respectively. In fig. 7, the wire layer 204, the wire layer 206, and the wire 214 may be individually or integrally regarded as connection features of the light emitting unit 150.

Fig. 8 shows a variation of the light-emitting unit 150 of the present application. In the embodiment shown in fig. 8, the package substrate 212 has a sidewall 212a to form a cup-shaped structure surrounding the light emitting chip C1. In the light emitting unit 150, the light emitting chip C1 may be disposed in a cavity or a recess of the package substrate 212 and electrically connected to the wire layers 204, 206 disposed in the package substrate 212 through the wires 214. In addition, the cavity or the recess of the package substrate 212 may be disposed with the package adhesive 208 on the light emitting chip C1 and protect the light emitting chip C1. The package substrate 212 in the embodiments shown in fig. 7 and 8 may have high reflectivity to improve light utilization. In some embodiments, the package substrate 212 including the wire layers 204, 206 may serve as a support structure for supporting the light emitting chip C1. In fig. 8, the wire layer 204, the wire layer 206, and the wire 214 may be individually or integrally regarded as a connection feature of the light emitting unit 150.

Fig. 9 shows a variation of the light-emitting unit 150 of the present application. In the embodiment shown in fig. 9, the light emitting chip C1 is packaged with the conductive end facing downward, and the packaging adhesive 208 is disposed on the light emitting chip C1 to form the light emitting unit 150. In some embodiments, the bonding pads 210 are exposed from the encapsulant 208, so that the light emitting chip C1 and the

conductive pads

146a and 146b can be electrically connected directly through the bonding pads 210 without passing through the cup-shaped support or the package substrate 202 of the previous embodiments. In some embodiments, the connection pad 210 directly contacts the conductive pad 146a and the conductive pad 146b. In fig. 9, the connection pads 210 may be individually or entirely regarded as connection features of the light emitting unit 150.

Fig. 10 is a schematic top view illustrating a variation of the light emitting unit 150 of the present application. In the embodiment shown in fig. 10, the light emitting unit 150 includes two light emitting chips C2 and C3. In some embodiments, the light emitting chips C2 and C3 can emit light beams with different colors. For example, the light emitting chip C2 may emit blue light and the light emitting chip C3 may emit green light. In some embodiments, the encapsulant 208 of the light emitting unit 150 may include an encapsulant 208a and a phosphor 216 (e.g., a red phosphor) dispersed in the encapsulant 208a (e.g., an epoxy or silicone), wherein when the blue light and/or the green light emitted by the light emitting chip is irradiated onto the phosphor 216, a portion of the blue light and/or the green light is converted into red light, so that the light emitting unit 150 may generate white light formed by mixing the green light, the blue light and the red light. In some other embodiments, the light emitting unit 150 of the present application has only a single blue light emitting chip, and the package adhesive 208 contains yellow phosphor powder, so that the light emitting unit 150 can finally generate white light. In some other embodiments, the light emitting unit 150 of the present application has only a single blue light emitting chip, and the encapsulant 208 contains quantum dots with different particle sizes, so that the light emitting unit 150 can finally generate light with different colors. In some other embodiments, quantum dots may be disposed on the light emitting chip of the light emitting unit 150 of the present application. In some other embodiments, the light-diffusing particles may be included in the encapsulant 208 of the light-emitting unit 150 of the present application to improve the brightness uniformity of the light emitted. The light emitting unit 150 with various encapsulation glues or other suitable light emitting units can be applied in various embodiments and variations of the present application, and are not described herein again.

It should be understood that although not shown in FIG. 2, in some embodiments, other components (e.g., cover plates or optical films) may be formed on the electronic device 10. For example, the cover plate may be formed of glass, ito, pi, pet, other suitable materials, or combinations thereof, but the disclosure is not limited thereto. For example, the optical film may include a diffuser plate (diffuser film), a condenser lens, other suitable optical films, or a combination thereof, but the disclosure is not limited thereto.

It should be understood that, for convenience of illustration, only one light-emitting unit 150 of the electronic device 10 is illustrated in fig. 2. However, the electronic device 10 may include any suitable number of light emitting units 150. In some embodiments, each of the light emitting units 150 has an encapsulant 208, and the encapsulants 208 are separated from each other. In other embodiments, the light emitting units 150 each have a package substrate 202, and the package substrates are separated from each other, but the package adhesives 208 are connected to each other.

It is understood that in some embodiments, the electronic device (e.g., display device) 10 may be bent to form a curved electronic device (e.g., curved display device). Curved electronic devices in such embodiments may include the same or similar features as electronic device 10, and such curved electronic devices are intended to be included within the scope of the present application.

It should be understood that in some embodiments, a plurality of electronic devices 10 (e.g., display devices) may be combined to form a large-sized electronic device (e.g., display device), and such large-sized electronic devices are also included in the scope of the present application.

It is understood that in some embodiments, the composite substrate 100 of the electronic device 10 and various layers and components on the composite substrate 100 may be used as a backlight module.

In summary, the substrate of the electronic device according to the embodiment of the present invention can be provided with the insulating layer having good ductility, so that the electronic device is less likely to cause a crack when bent. In addition, in some embodiments, a substantially flat insulating layer is disposed between the light emitting unit and the substrate of the electronic device, so that the conductive pads for connecting the light emitting units can be substantially at the same level, thereby reducing the problem of poor bonding between the light emitting unit and the conductive pads and improving the yield of the electronic device.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present application. Those skilled in the art should appreciate and readily appreciate that other processes and structures can be devised and modified based on the present application that achieve the same purposes and/or achieve the same advantages as the embodiments described herein. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the application. Various changes, substitutions, or alterations may be made to the embodiments of the present application without departing from the spirit and scope of the application

Each claim of the present application may be an individual embodiment, and the scope of the present application includes each claim of the present application and each embodiment in combination with each other.

Claims

1. An electronic device, comprising:

a substrate including a bendable region;

a plurality of thin film transistors disposed on the substrate;

a first insulating layer disposed on the plurality of thin film transistors;

a first conductive layer disposed on the first insulating layer, wherein the first conductive layer is in direct contact with the top surface of the first insulating layer, penetrates through the first insulating layer, and is electrically connected to one of the plurality of thin film transistors;

a second insulating layer disposed on the first insulating layer and the first conductive layer and directly contacting at least a portion of the top surface of the first conductive layer; and

a conductive wire disposed on the bendable region and the first insulating layer and having a wavy edge or at least one opening.

2. The electronic device of claim 1, further comprising a plurality of light-emitting units electrically connected to the plurality of thin film transistors, wherein one of the plurality of light-emitting units has an encapsulant material and at least one light-emitting layer, the encapsulant material being disposed on the light-emitting layer.

3. The electronic device of claim 2, wherein the at least one light emitting body frame is at least one light emitting chip.

4. The electronic device of claim 2, wherein a distance between one of the plurality of light-emitting units and the substrate is different from a distance between the conductive line and the substrate.

5. The electronic device of claim 2, wherein the light-emitting unit further has a connection feature, and the light-emitting layer is electrically connected to the thin film transistor through the connection feature.

6. The electronic device of claim 2, wherein the one of the plurality of light-emitting units comprises phosphor powder, quantum dots, or light-diffusing particles dispersed in the encapsulant.

7. The electronic device of claim 2, wherein the thin film transistor has an active layer, and the active layer and the light emitting unit do not overlap in a normal direction of the substrate.

8. The electronic device of claim 2, wherein the thin film transistor has an active layer, and the active layer and the light-emitting unit at least partially overlap in a normal direction of the substrate.

9. The electronic device of claim 1, further comprising a third insulating layer disposed on the second insulating layer.

10. The electronic device of claim 9, wherein the substrate comprises a non-bending region adjacent to the bending region, wherein a thickness of the first insulating layer on the non-bending region is smaller than a thickness of the first insulating layer on the bending region.