CN110379714A - The forming method and semiconductor structure of semiconductor structure - Google Patents
The forming method and semiconductor structure of semiconductor structure Download PDFInfo
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- CN110379714A CN110379714A CN201910637434.5A CN201910637434A CN110379714A CN 110379714 A CN110379714 A CN 110379714A CN 201910637434 A CN201910637434 A CN 201910637434A CN 110379714 A CN110379714 A CN 110379714A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000000463 material Substances 0.000 claims abstract description 78
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 125000006850 spacer group Chemical group 0.000 claims abstract description 49
- 238000007667 floating Methods 0.000 claims abstract description 42
- 229920002120 photoresistant polymer Polymers 0.000 claims description 62
- 238000005530 etching Methods 0.000 claims description 35
- 238000002955 isolation Methods 0.000 claims description 33
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 238000001312 dry etching Methods 0.000 claims description 12
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 11
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims 1
- 150000001335 aliphatic alkanes Chemical class 0.000 claims 1
- 229910052799 carbon Inorganic materials 0.000 claims 1
- 229910052731 fluorine Inorganic materials 0.000 claims 1
- 239000011737 fluorine Substances 0.000 claims 1
- 239000007789 gas Substances 0.000 description 20
- 238000011049 filling Methods 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- 206010034960 Photophobia Diseases 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 208000013469 light sensitivity Diseases 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Element Separation (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention provides a kind of forming method of semiconductor structure and semiconductor structures, including the first mask layer is formed on the substrate；The substrate of first mask layer and segment thickness is etched, to form at least one isolated groove in the substrate, the transverse width dimension of the isolated groove is gradually reduced from notch along slot bottom；Spacer material layer is filled in the isolated groove；The second mask layer is formed on the spacer material layer, the transverse width dimension of second mask layer is less than the maximum lateral width size of the isolated groove；Use second mask layer for mask again, the spacer material layer for removing first mask layer and not covered by second mask layer, to form several openings, floating gate layer is finally filled in said opening, due to not being removed by the spacer material layer that second mask layer covers, so that the opening formed can effectively avoid occurring cavity blemish in floating gate layer, improve the yield of device close to rectangle.
Description
Technical field
The present invention relates to technical field of semiconductor preparation more particularly to the forming methods and semiconductor of a kind of semiconductor structure
Structure.
Background technique
Memory device is the device for storing a large amount of digital informations, in recent years, the progress and the market demand of technology
Expedite the emergence of more and more highdensity various types of memory devices, wherein non-volatile memory device (Non-volatile
Memory, NVM) it remains to keep data information for seasonable in system closing or non-transformer, floating gate type memory part is exactly a kind of non-
Volatile memory, in floating gate type memory part, charge is stored in floating gate, they non-transformer supply in the case where still
Data information can be kept, so being widely used in various business and military electronic devices and equipment.
The structure of floating gate type memory part is similar with Metal Oxide Semiconductor Field Effect Transistor (MOSFET) structure, packet
The source/drain being located in substrate and the grid above substrate are included, it is main with general MOSFET the difference lies in that floating
Grid-type memory device further includes a floating gate (Floating Gate, FG), but prepared by existing floating gate type memory part
Cheng Zhong is easy to cause device to be scrapped there are cavity blemish, influence yield when preparing floating gate, in floating gate；Even, the sky in floating gate
Hole defect is not found in time, causes the storage performance of finished device bad.
Summary of the invention
The purpose of the present invention is to provide a kind of forming method of semiconductor structure and semiconductor structures, existing to solve
Floating gate type memory part the problem of floating gate is easy to produce cavity blemish during the preparation process.
In order to achieve the above object, the present invention provides a kind of forming methods of semiconductor structure, comprising:
One substrate is provided, the first mask layer is formed on the substrate；
The substrate of first mask layer and segment thickness is etched, to form at least one isolation in the substrate
The transverse width dimension of groove, the isolated groove is gradually reduced from notch along slot bottom；
Spacer material layer is filled in the isolated groove；
The second mask layer is formed on the spacer material layer, the transverse width dimension of second mask layer is less than described
The maximum lateral width size of isolated groove；
Using second mask layer as mask, remove first mask layer and not by second mask layer cover every
From material layer, to form several openings；
Floating gate layer is formed in the opening.
Optionally, the transverse width dimension H1 of second mask layer meets following formula:
H2≤H1 < H3；
Wherein, H2 is the minimum lateral width dimensions of the isolated groove, and H3 is that the minimum lateral of the isolated groove is wide
Spend size.
Optionally, using second mask layer as mask, first mask layer is removed and not by second mask layer
The step of spacer material layer of covering includes:
Using second mask layer as mask, first mask layer is removed using dry etching and is not covered by described second
One setting thickness of the spacer material layer of mold layer covering；
Remaining first mask layer is removed using wet etching.
Optionally, the thickness of remaining first mask layer is between 100 angstroms -150 angstroms.
Optionally, quarter of the etching gas that the dry etching uses to first mask layer and the spacer material layer
Erosion selection ratio is between 0.8:1~1:1.2.
Optionally, the material of first mask layer includes silicon nitride, and the material of the spacer material layer includes silica,
The etching gas that the dry etching uses includes several carbon fluorine gas.
Optionally, the etching gas is tetrafluoromethane；Alternatively, the etching gas is tetrafluoromethane and other carbon fluorine gas
The mixture of body, the proportion by adjusting tetrafluoromethane and other carbon fluorine gas are covered with adjusting the etching gas to described first
The etching selection ratio of mold layer and the spacer material layer.
Optionally, the substrate of first mask layer and segment thickness is etched, to be formed in the substrate at least
The step of one isolated groove includes:
The first photoresist layer is formed on first mask layer, exposure is executed to first photoresist layer using the first light shield
Light, to form patterned first photoresist layer；
Using patterned first photoresist layer as mask, the lining of first mask layer and segment thickness is etched
Bottom, to form at least one described isolated groove in the substrate；
Remove patterned first photoresist layer；
And include: the step of forming second mask layer on the spacer material layer
The second photoresist layer is formed on first mask layer and the spacer material layer, using the second light shield to described
Two photoresist layers execute exposure, to form the second mask layer.
Optionally, first light shield and second light shield use identical light shield, and first photoresist layer with
The material of second photoresist layer is respectively positive photoresist and negative sense photoresist, alternatively, first photoresist layer and second light
The material of resistance layer is respectively negative sense photoresist and positive photoresist.
The present invention also provides a kind of semiconductor structures, are formed using the forming method of the semiconductor structure.
Inventors have found that in the preparation of existing floating gate type memory part, it usually needs be initially formed fleet plough groove isolation structure
(shallow trench isolation, STI), namely a layer mask layer is first formed on the substrate, then etch the mask layer
And the substrate of segment thickness, to form at least one isolated groove in the substrate, then fill in the isolation trench every
From material layer, the spacer material layer and the isolated groove constitute the fleet plough groove isolation structure.Formed the shallow trench every
After structure, need to remove the mask layer to form several openings, then filling floating gate layer is floating to be formed in said opening
Grid.But due to etching technics limitation, when forming the isolated groove, the side wall of the isolated groove and non-perpendicular to described
The surface of substrate, but there is an angle with the surface of the substrate, so that the fleet plough groove isolation structure formed is in
Trapezoidal structure, so, after removing the mask layer, the opening of formation is trapezoidal, that is to say, that the opening is
It is up-narrow and down-wide, it is unfavorable for the filling of floating gate layer, i.e., when filling the floating gate layer in the opening, is easy to produce in the floating gate layer
Raw cavity blemish, scraps so as to cause device.
Based on this, in the forming method of semiconductor structure provided by the invention and semiconductor structure, including on substrate
Form the first mask layer；The substrate of first mask layer and segment thickness is etched, to be formed in the substrate at least
The transverse width dimension of one isolated groove, the isolated groove is gradually reduced from notch along slot bottom；Fill spacer material layer in
In the isolated groove；The second mask layer, the transverse width dimension of second mask layer are formed on the spacer material layer
Less than the maximum lateral width size of the isolated groove；Use second mask layer for mask again, removal described first is covered
Mold layer and not by second mask layer cover spacer material layer finally filled in said opening with forming several openings
Floating gate layer, due to not being removed by the spacer material layer that second mask layer covers, so that the described of formation opens
Mouth is conducive to the filling of floating gate layer, can effectively avoid occurring cavity blemish in floating gate layer, improve device close to rectangle
Yield.
Detailed description of the invention
Fig. 1-Fig. 6 is the diagrammatic cross-section of several device architectures formed using a kind of forming method of semiconductor structure；
Fig. 7 is the flow chart of the forming method of semiconductor structure provided in an embodiment of the present invention；
Fig. 8-Figure 16 is several device junctions formed using the forming method of semiconductor structure provided in an embodiment of the present invention
The diagrammatic cross-section of structure；
Wherein, appended drawing reference are as follows:
101- substrate；102- pad oxide；103- pad oxide；104- photoresist layer；104 '-patterned photoresist layers；
105- light shield；106- isolated groove；107- spacer material layer；108- fleet plough groove isolation structure；109- opening；110- floating gate layer；
111- cavity blemish；
201- substrate；202- pad oxide；The first mask layer of 203-；The first photoresist layer of 2041-；2041 '-patterned
One photoresist layer；The second photoresist layer of 2042-；2042 '-the second mask layers；The first light shield of 2051-；The second light shield of 2052-；206- every
From groove；207- spacer material layer；208- fleet plough groove isolation structure；209- opening；210- floating gate layer；
The transverse width dimension of D1- isolated groove notch；
The transverse width dimension of D2- isolated groove slot bottom；
The transverse width dimension of the second mask layer of H1-；
The transverse width dimension of H2- isolated groove slot bottom；
The transverse width dimension of H3- isolated groove notch.
Specific embodiment
A kind of forming method of semiconductor structure is as shown in figs 1 to 6.Referring initially to Fig. 1, substrate 101, the lining are provided
Pad oxide 102 and mask layer 103 are formed on bottom 101, the pad oxide 102 covers the substrate, the mask layer 103
The pad oxide 102 is covered, the material of the pad oxide 102 can be silica etc., to play alleviation stress, increase film
The effect of adhesion strength between layer, the material of the mask layer 103 can be silicon nitride etc., can be used for etch stopper or grind
Then mill blocking etc. is coated with photoresist on the mask layer 103 to form photoresist layer 104.Next, as shown in Fig. 2, using light
105 pairs of photoresist layers 104 of cover execute exposure, to form patterned photoresist layer 104 ', the patterned photoresist layer 104 '
The position etc. of fleet plough groove isolation structure for defining the shape of active area and needing to form.Then, as shown in figure 3, with described
Patterned photoresist layer 104 ' is mask, etches the substrate of the mask layer 103, pad oxide 102 and segment thickness
101, to form several isolated grooves 106, the patterned photoresist layer 104 ' is then removed using cineration technics.Then, such as
Shown in Fig. 4, isolated material is filled in the isolated groove 106 to form spacer material layer 107, so that the spacer material layer
107 constitute fleet plough groove isolation structure 108 with the isolated groove 106.It is understood that due to the isolated groove 106
The limitation of depth-to-width ratio usually larger (being greater than 3) and etching technics, the side wall of the isolated groove 106 are usually inclined
(there is an angle with the surface of the substrate 101), and the transverse width dimension of the isolated groove 106 from notch along slot bottom by
It is decrescence small that (the transverse width dimension D1 of 106 notch of isolated groove is the maximum lateral width ruler of the isolated groove 106
Very little, the transverse width dimension D2 of 106 slot bottom of isolated groove is the minimum lateral width dimensions of the isolated groove 106), tool
Body is as shown in figure 3, so, the fleet plough groove isolation structure 108 of formation is also in the structure of inverted trapezoidal.
Next, as shown in figure 5, remove the mask layer 103 using wet-etching technology, to form several openings 109,
It is understood that the opening 109 is then inevitable trapezoidal since the fleet plough groove isolation structure 108 is in the structure of inverted trapezoidal
(transverse width dimension at 109 top of opening is less than the transverse width dimension of bottom).Finally, as shown in fig. 6, being opened described
Floating gate layers 110 are filled in mouth 109, since the opening 109 is trapezoidal, are unfavorable for the filling of the floating gate layer 110, so in shape
After the floating gate layer 110, the floating gate layer 110 cavity easy to form on the position of the fleet plough groove isolation structure 108
Defect 111.
Based on this, the present invention provides a kind of forming method of semiconductor structure and semiconductor structures, including on substrate
Form the first mask layer；The substrate of first mask layer and segment thickness is etched, to be formed in the substrate at least
The transverse width dimension of one isolated groove, the isolated groove is gradually reduced from notch along slot bottom；Fill spacer material layer in
In the isolated groove；The second mask layer, the transverse width dimension of second mask layer are formed on the spacer material layer
Less than the maximum lateral width size of the isolated groove；Use second mask layer for mask again, removal described first is covered
Mold layer and not by second mask layer cover spacer material layer finally filled in said opening with forming several openings
Floating gate layer, due to not being removed by the spacer material layer that second mask layer covers, so that the described of formation opens
Mouth is conducive to the filling of floating gate layer, can effectively avoid occurring cavity blemish in floating gate layer, improve device close to rectangle
Yield.
A specific embodiment of the invention is described in more detail below in conjunction with schematic diagram.According to following description,
Advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non-accurate
Ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
As shown in fig. 7, present embodiments providing a kind of forming method of semiconductor structure, comprising:
Step S1: a substrate is provided, is formed with the first mask layer on the substrate；
Step S2: the substrate of etching first mask layer and segment thickness, to be formed in the substrate at least
The transverse width dimension of one isolated groove, the isolated groove is gradually reduced from notch along slot bottom；
Step S3: spacer material layer is formed in the isolated groove；
Step S4: the second mask layer, the transverse width dimension of second mask layer are formed on the spacer material layer
Less than the maximum lateral width size of the isolated groove；
Step S5: using second mask layer as mask, first mask layer is removed and not by second mask layer
The spacer material layer of covering, to form several openings；
Step S6: floating gate layer is formed in the opening.
Specifically, Fig. 8-Figure 16 is please referred to, if for the dry units formed using the forming method of the semiconductor structure
The diagrammatic cross-section of structure, next, Fig. 8-Figure 16 will be combined to make the forming method of semiconductor structure provided in this embodiment
It is described in detail.
Firstly, referring to Fig. 8, execution step S1, provides a substrate 201, has defined in the substrate 201 multiple active
Area (not shown), each active area is from the top of the substrate 201 to the internal stretch of the substrate 201 to a depthkeeping
It spends, source region and drain region (not shown), further, the source region can be formed by modes such as ion implantings in the active area
The type for the specific device that can be formed as needed with the doping type in drain region determines.A pad oxygen is formed on the substrate 201
Change layer 202 and the first mask layer 203, the pad oxide 202 covers the substrate 201, and first mask layer 203 covers institute
State pad oxide 202.The material of the pad oxide 202 can be silica etc., to play alleviation stress, increase between film layer
Adhesion strength effect, the material of first mask layer 203 can be silicon nitride etc., can be used for etch stopper or grinding
Stop etc..Please continue to refer to Fig. 8, it is coated with photoresist on first mask layer 203, to form the first photoresist layer 2041, then
As shown in figure 9, exposure is executed to first photoresist layer 2041 using the first light shield 2051, to form patterned first photoresist
Layer 2041 ', the figure of the figure and the active area of patterned first photoresist layer 2041 ' matches, so that the figure
First photoresist layer 2041 ' of shape can define the shape of the active area and the fleet plough groove isolation structure that needs to form
Position etc..
It is mask with patterned first photoresist layer 2041 ' next, executing step S2, etching described first is covered
The substrate 201 of mold layer 203, pad oxide 202 and segment thickness, to be formed in the substrate 201 described at least one
Then isolated groove 206 removes patterned first photoresist layer 2041 ', forms device architecture as shown in Figure 10.It can
With understanding, the isolated groove 206 needs vertically through the active area since the depth-to-width ratio of the isolated groove 206 is logical
The limitation of normal larger (being greater than 3) and etching technics, the side wall of the isolated groove 206 it is usually inclined (with it is described
The surface of substrate 201 has an angle), and the transverse width dimension of the isolated groove 206 is gradually reduced from notch along slot bottom
(the transverse width dimension H3 of 206 notch of isolated groove is the maximum lateral width size of the isolated groove 106, described
The transverse width dimension H2 of 106 slot bottom of isolated groove is the minimum lateral width dimensions of the isolated groove 106) so that described
Isolated groove 206 is in inverted trapezoidal.
Next, as shown in figure 11, executing step S3, spacer material layer 207 is filled in the isolated groove 206, with
The spacer material layer 207 filled in the isolated groove 206 and the isolated groove 206 is set to constitute fleet plough groove isolation structure
208, it is to be understood that the shape and ruler of the shape and size of the fleet plough groove isolation structure 208 and the isolated groove 206
Very little to match, i.e., the described fleet plough groove isolation structure 208 is also in inverted trapezoidal, and for maximum lateral width having a size of H3, minimum lateral is wide
Degree is having a size of H2.
Further, Figure 12 is please referred to, step S4 is executed, in first mask layer 203 and the fleet plough groove isolation structure
Photoresist is coated on 208 to form the second photoresist layer 2042, next, as shown in Figure 10 and Figure 13, it is right using the second light shield 2052
Second photoresist layer 2042 executes exposure, to form the second mask layer 2042 ' (namely patterned second photoresist layer), institute
The transverse width dimension H1 for stating the second mask layer 2042 ' is less than the fleet plough groove isolation structure 208 (or isolated groove 206) most
Big transverse width dimension H3, the transverse width dimension H1 of second mask layer 2042 ' also greater than or be equal to the shallow trench every
Minimum lateral width dimensions H2 from structure 208 (or isolated groove 206), so, second mask layer 2042 ' only covers
Fleet plough groove isolation structure 208 described in cover.Optionally, second mask layer 2042 ' can be located at the shallow trench isolation
The center of structure 208, so that the transverse width dimension that 208 the right and left of the fleet plough groove isolation structure exposes is equal.
In the present embodiment, second light shield 2052 and first light shield 2051 use same light shield, to save
Preparation cost, when the second light shield 2052 and the first light shield 2051 same light shield of use, first photoresist layer 2041
The material for needing to use light sensitivity opposite with second photoresist layer 2042, for example, the material of first photoresist layer 2041 is
The material of positive photoresist, second photoresist layer 2042 then uses negative sense photoresist, alternatively, the material of first photoresist layer 2041
For negative sense photoresist, then the material of second photoresist layer 2042 then uses positive photoresist.It is understood that by adjusting exposure
Parameter can to use same light shield even if second light shield 2052 and first light shield 2051, the of formation
The transverse width dimension H1 of two mask layers 2042 ' can be less than the fleet plough groove isolation structure 208 (or isolated groove 206) most
Big transverse width dimension H3.
Next, please referring to Figure 11 and Figure 14, step S5 is executed, is mask with second mask layer 2042 ', using dry
Method etching removes first mask layer 203 and is not set by the one of the spacer material layer 207 that second mask layer 2042 ' covers
Determine thickness；That is, by the segment thickness of first mask layer 203 and the fleet plough groove isolation structure 208 or so two
The segment thickness removal for the spacer material layer 207 that side is exposed, the thickness of remaining first mask layer 203 can be thinner,
E.g. between 100 angstroms -150 angstroms, prevent the dry etching to the pad oxide 202 and the substrate to realize
201 cause the effect of damage.
Further, in the present embodiment, the thickness of first mask layer 203 and the fleet plough groove isolation structure 208 is phase
With, so in order to preferably remove first mask layer 203 and not by the described shallow of second mask layer 2042 ' covering
The setting thickness of groove isolation construction 208, the etching gas that the dry etching uses to first mask layer 203 and
The etching selection ratio of the spacer material layer is between 0.8:1~1:1.2, it is preferred that first mask layer 203 and described
The etching selection ratio of spacer material layer is 1:1, so that first mask layer 203 and the fleet plough groove isolation structure 208
Etch rate is identical.After etching, the residual thickness of first mask layer 203 and not by second mask layer 2042 '
The residual thickness of the fleet plough groove isolation structure 208 of covering is identical.In the present embodiment, the material of first mask layer 203
Packet is silicon nitride, and the material of the spacer material layer in the fleet plough groove isolation structure 208 is silica, and the dry etching uses
Etching gas include several carbon fluorine gas, for example, the etching gas can be tetrafluoromethane (CF4), to silica
Etching selection ratio with silicon nitride is close to 1:1, alternatively, the etching gas is also possible to for tetrafluoromethane (CF4) and other
Carbon fluorine gas (CHF3、C4F6Or C4F8Deng) mixture pass through when the etching gas is the mixture of several carbon fluorine gas
Adjust tetrafluoromethane (CF4) with the adjustable etching gas of proportion of other carbon fluorine gas to first mask layer 203
And the etching selection ratio of the spacer material layer is between 0.8:1~1:1.2.
Certainly, if first mask layer 203 and the spacer material layer are other materials, can accordingly change described
The etching gas of dry etching so that the dry etching use etching gas to first mask layer 203 and it is described every
Between 0.8:1~1:1.2, the present embodiment is no longer illustrated etching selection ratio from material layer one by one.
Next, as shown in figure 15, removing remaining first mask layer 203 using wet etching, forming several open
Mouth 109.It is understood that due to eliminating what described 208 the right and left of fleet plough groove isolation structure exposed using dry etching
Spacer material layer, so the side wall that the fleet plough groove isolation structure 208 is higher than the part of the substrate 201 can after etching
With the surface perpendicular to (or close to vertically) substrate 201, after removing first mask layer 203, the opening 109
For (or close to) rectangle, be conducive to the filling of floating gate layer.Finally, as shown in figure 16, filling floating gate layer in the opening 109
210, since the opening 109 is (or close to) rectangle, is not in cavity blemish in the floating gate layer 210, improves device
The yield of part.
Based on this, the present embodiment additionally provides a kind of semiconductor structure, using the forming method of the semiconductor structure
It is formed.
To sum up, in the forming method of semiconductor structure provided in an embodiment of the present invention and semiconductor structure, it is included in lining
The first mask layer is formed on bottom；The substrate of first mask layer and segment thickness is etched, to be formed in the substrate
The transverse width dimension of at least one isolated groove, the isolated groove is gradually reduced from notch along slot bottom；Fill isolated material
Layer is in the isolated groove；The second mask layer, the transverse width of second mask layer are formed on the spacer material layer
Size is less than the maximum lateral width size of the isolated groove；It uses second mask layer for mask again, removes described the
One mask layer and the spacer material layer not covered by second mask layer, to form several openings, finally in said opening
Floating gate layer is filled, due to not being removed by the spacer material layer that second mask layer covers, so that the institute formed
Opening is stated close to rectangle, is conducive to the filling of floating gate layer, can effectively avoid occurring cavity blemish in floating gate layer, improve device
The yield of part.
The above is only a preferred embodiment of the present invention, does not play the role of any restrictions to the present invention.Belonging to any
Those skilled in the art, in the range of not departing from technical solution of the present invention, to the invention discloses technical solution and
Technology contents make the variation such as any type of equivalent replacement or modification, belong to the content without departing from technical solution of the present invention, still
Within belonging to the scope of protection of the present invention.
Claims (10)
1. a kind of forming method of semiconductor structure characterized by comprising
One substrate is provided, the first mask layer is formed on the substrate；
The substrate of first mask layer and segment thickness is etched, to form at least one isolating trenches in the substrate
The transverse width dimension of slot, the isolated groove is gradually reduced from notch along slot bottom；
Spacer material layer is formed in the isolated groove；
The second mask layer is formed on the spacer material layer, the transverse width dimension of second mask layer is less than the isolation
The maximum lateral width size of groove；
Using second mask layer as mask, first mask layer is removed and not by the isolation material of second mask layer covering
The bed of material, to form several openings；
Floating gate layer is formed in the opening.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that second mask layer it is laterally wide
Degree size H1 meets following formula:
H2≤H1 < H3；
Wherein, H2 is the minimum lateral width dimensions of the isolated groove, and H3 is the minimum lateral broad-ruler of the isolated groove
It is very little.
3. the forming method of semiconductor structure as claimed in claim 1 or 2, which is characterized in that be with second mask layer
Mask removes first mask layer and does not include: by the step of spacer material layer of second mask layer covering
Using second mask layer as mask, first mask layer is removed using dry etching and not by second mask layer
One setting thickness of the spacer material layer of covering；
Remaining first mask layer is removed using wet etching.
4. the forming method of semiconductor structure as claimed in claim 3, which is characterized in that remaining first mask layer
Thickness is between 100 angstroms -150 angstroms.
5. the forming method of semiconductor structure as claimed in claim 3, which is characterized in that the etching that the dry etching uses
Gas is to the etching selection ratio of first mask layer and the spacer material layer between 0.8:1~1:1.2.
6. the forming method of semiconductor structure as claimed in claim 5, which is characterized in that the material packet of first mask layer
Silicon nitride is included, the material of the spacer material layer includes silica, and the etching gas that the dry etching uses includes several
Carbon fluorine gas.
7. the forming method of semiconductor structure as claimed in claim 6, which is characterized in that the etching gas is tetrafluoro first
Alkane；Alternatively, the etching gas is the mixture of tetrafluoromethane and other carbon fluorine gas, by adjusting tetrafluoromethane and other carbon
The proportion of fluorine gas is to adjust the etching gas to the etching selection ratio of first mask layer and the spacer material layer.
8. the forming method of semiconductor structure as claimed in claim 1 or 2, which is characterized in that etching first mask layer
And the substrate of segment thickness, include: the step of at least one isolated groove to be formed in the substrate
The first photoresist layer is formed on first mask layer, exposure is executed to first photoresist layer using the first light shield, with
Form patterned first photoresist layer；
Using patterned first photoresist layer as mask, the substrate of first mask layer and segment thickness is etched, with
At least one described isolated groove is formed in the substrate；
Remove patterned first photoresist layer；
And include: the step of forming second mask layer on the spacer material layer
The second photoresist layer is formed on first mask layer and the spacer material layer, using the second light shield to second light
Resistance layer executes exposure, to form the second mask layer.
9. the forming method of semiconductor structure as claimed in claim 8, which is characterized in that first light shield and described second
Light shield uses identical light shield, and the material of first photoresist layer and second photoresist layer is respectively positive photoresist and bears
To photoresist, alternatively, the material of first photoresist layer and second photoresist layer is respectively negative sense photoresist and positive photoresist.
10. a kind of semiconductor structure, which is characterized in that using semiconductor structure as claimed in any one of claims 1-9 wherein
Forming method is formed.
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| CN113140500A (en) * | 2021-04-19 | 2021-07-20 | 上海积塔半导体有限公司 | Method for manufacturing semiconductor structure |
| CN113437015A (en) * | 2021-06-21 | 2021-09-24 | 长江存储科技有限责任公司 | Method for manufacturing semiconductor device |
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| CN103794549A (en) * | 2012-10-31 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN104112654A (en) * | 2013-04-18 | 2014-10-22 | 中芯国际集成电路制造(上海)有限公司 | Process method for reducing floating gate holes |
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| US20050282351A1 (en) * | 2004-06-22 | 2005-12-22 | Manuel Quevedo-Lopez | Methods and systems to mitigate etch stop clipping for shallow trench isolation fabrication |
| US20070218619A1 (en) * | 2006-03-20 | 2007-09-20 | Ji-Hoon Cha | Method of manufacturing nonvolatile semiconductor memory device |
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| CN113437015A (en) * | 2021-06-21 | 2021-09-24 | 长江存储科技有限责任公司 | Method for manufacturing semiconductor device |
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Address after: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee after: Wuhan Xinxin Integrated Circuit Co.,Ltd. Country or region after: China Address before: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee before: Wuhan Xinxin Semiconductor Manufacturing Co.,Ltd. Country or region before: China |