CN110365329B - Phase frequency detector circuit - Google Patents

Phase frequency detector circuit Download PDF

Info

Publication number
CN110365329B
CN110365329B CN201810318222.6A CN201810318222A CN110365329B CN 110365329 B CN110365329 B CN 110365329B CN 201810318222 A CN201810318222 A CN 201810318222A CN 110365329 B CN110365329 B CN 110365329B
Authority
CN
China
Prior art keywords
signal
output
trigger
phase
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810318222.6A
Other languages
Chinese (zh)
Other versions
CN110365329A (en
Inventor
薛盘斗
冯光涛
张步新
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201810318222.6A priority Critical patent/CN110365329B/en
Publication of CN110365329A publication Critical patent/CN110365329A/en
Application granted granted Critical
Publication of CN110365329B publication Critical patent/CN110365329B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Manipulation Of Pulses (AREA)

Abstract

A phase frequency detector circuit comprising: the first signal phase discrimination branch is used for outputting a first output signal according to a first signal, and the first output signal is related to the rising edge of the first signal; the second signal phase discrimination branch is used for outputting a second output signal according to a second signal, the second output signal is related to the rising edge of the second signal, the phase of the first signal is higher than that of the second signal, and the phase difference range is [0,2 pi ]; if the phase difference between the first signal and the second signal is greater than pi, the first output signal is kept at a high level after the rising edge of the first signal arrives, and the second output signal is kept at a low level after the rising edge of the second signal arrives. According to the invention, the first input unit and the second input unit are respectively arranged in the first signal phase discrimination branch and the second signal phase discrimination branch so as to control the output of the branch where the first signal and the second signal arrive at the rising edge, thereby thoroughly preventing the generation of dead zones and accelerating the capturing process of the whole circuit.

Description

Phase frequency detector circuit
Technical Field
The invention relates to the field of integrated circuits, in particular to a phase frequency detector circuit.
Background
The phase-locked loop is a closed-loop automatic phase control system capable of tracking an input signal, and the theoretical basis is an automatic control theory. The phase-locked loop has carrier tracking characteristics, and can perform high-precision phase measurement and frequency measurement. In analog and digital communication systems, phase locked loops have become an indispensable fundamental component. The phase-locked loop adopting the charge pump structure is widely applied to the fields of wireless communication, clock generation, frequency synthesis and the like due to the advantages of easiness in integration, low power consumption, low jitter and the like.
The phase frequency detector is an important component in a charge pump phase locked loop for detecting the phase difference between a reference signal and a feedback signal. In the design process of the charge pump phase-locked loop, a high-speed, low-power-consumption and wide-input-range phase frequency detector is always a design difficulty. When the phase difference of two input signals is close to zero, the structure of the traditional phase frequency detector has the dead zone problem, a delay unit is added on a reset path for solving the dead zone problem, and when the phase difference of the two input signals is close to 2 pi due to the addition of the delay unit, the structure of the traditional phase frequency detector can encounter the dead zone problem, namely the rising edge of the input signals cannot be recorded by the output signals, so that the actual detection range of the phase frequency detector is smaller than [ -2 pi, 2 pi ], and the locking time of a locking ring is prolonged.
At present, an improved phase frequency detector structure is provided, an input signal is introduced into a reset path, the generation of dead zones is effectively reduced by judging the height of the input signal, and the capturing process of a circuit is quickened. However, when the phase frequency detector structure has a phase difference of 2pi between two input signals, there is still a problem of dead zone.
Therefore, a phase frequency detector is required to prevent the generation of dead zones.
Disclosure of Invention
The invention solves the problem of providing a phase frequency detector circuit for comprehensively detecting phase difference.
To solve the above problems, an embodiment of the present invention provides a phase frequency detector circuit, including: the first signal phase discrimination branch is used for outputting a first output signal according to a first signal, and the first output signal is related to the rising edge of the first signal; the second signal phase discrimination branch is used for outputting a second output signal according to a second signal, the second output signal is related to the rising edge of the second signal, the phase of the first signal is higher than that of the second signal, and the phase difference range is [0,2 pi ]; if the phase difference between the first signal and the second signal is greater than pi, the first output signal is kept at a high level after the rising edge of the first signal arrives, and the second output signal is kept at a low level after the rising edge of the second signal arrives.
Optionally, if the phase difference between the first signal and the second signal is not greater than pi, when rising edges of the first signal and the second signal arrive, both the first output signal and the second output signal jump to high level.
Optionally, the first signal phase-discriminating branch includes: the first input unit comprises a first NOR gate, the first NOR gate is suitable for receiving a second signal and a second memory signal, the first NOR gate outputs the first NOR signal to the first trigger, and the second memory signal is generated by the second memory circuit; the first trigger is suitable for outputting a first memory signal according to a first signal, a first NOR signal, a first output signal and a second output signal, and the phase of the first memory signal is opposite to that of the first output signal; the first inverter is used for inverting the first memory signal and outputting a first output signal.
Optionally, the second signal phase-discriminating branch includes: the second input unit comprises a second NOR gate, the second NOR gate is suitable for receiving a first signal and a first memory signal, outputting the second NOR signal to a second trigger, and the first memory signal is generated by a first memory circuit; the second trigger is suitable for outputting a second memory signal according to a second signal, a second NOR signal, a first output signal and a second output signal, and the second memory signal is opposite to the second output signal in phase; and the second inverter is used for inverting the second memory signal and outputting a second output signal.
Optionally, the first trigger includes: the first trigger circuit is suitable for outputting a first trigger signal according to a first signal, a first NOR signal, a first output signal and a second output signal, wherein the first trigger signal is low level when the phase difference of the first signal and the second signal is not more than pi and the first output signal and the second output signal are both high level, and is kept high level when the phase difference of the first signal and the second signal is more than pi; the first memory circuit is suitable for outputting a first memory signal according to a first signal and a first trigger signal, if the phase difference of the first signal and the second signal is not more than pi, when the first signal is at a low level, the first memory signal is consistent with the first trigger signal, when the first signal is at a high level, the first memory signal is opposite to the first trigger signal, if the phase difference of the first signal and the second signal is more than pi, and when the rising edge of the first signal arrives, the first memory signal jumps to a low level and is kept.
Optionally, the first trigger circuit includes: the first trigger branch is suitable for outputting a high-level signal according to the first signal, the first nor signal; and one end of the first reset branch is connected with the output end of the first trigger branch, and is suitable for resetting the high-level signal output by the first trigger branch to be low level when the first output signal and the second output signal are both high level.
Optionally, the second trigger includes: the second trigger circuit is suitable for outputting a second trigger signal according to a second signal, a second NOR signal, a first output signal and a second output signal, wherein the second trigger signal is in a low level when the phase difference of the first signal and the second signal is not more than pi and the first output signal and the second output signal are both in a high level, and is opposite to the second signal potential when the phase difference of the first signal and the second signal is more than pi; the second memory circuit is suitable for outputting a second memory signal according to a second signal and a second trigger signal, if the phase difference of the first signal and the second signal is not more than pi, when the second signal is in a low level, the second memory signal is consistent with the second trigger signal in potential, when the second signal is in a high level, the second memory signal is opposite to the second trigger signal in potential, the phase difference of the first signal and the second signal is more than pi, and the second memory signal keeps in high level output.
Optionally, the second trigger circuit includes: the second trigger branch is suitable for outputting a high-level signal according to the second signal and the second or non-signal if the phase difference between the first signal and the second signal is not more than pi, and outputting a signal with opposite potential to the second signal if the phase difference between the first signal and the second signal is more than pi; and one end of the second reset branch is connected with the output end of the second trigger branch, and is suitable for resetting the second trigger signal to a low level when the first output signal and the second output signal are both at a high level.
Optionally, the first trigger branch includes: the first PMOS tube has a first end coupled with the output end of the first input unit, a second end coupled with the grid of the first NMOS tube, and the grid receives a first signal; the first end of the third PMOS tube is coupled with the power supply, the second end of the third PMOS tube is coupled with the first end of the first NMOS tube, the coupling part is a first node, a first trigger signal is output, and the grid electrode receives the first signal; the second end of the first NMOS tube is coupled with the first end of the second NMOS tube; and the second end of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube receives the first signal.
Optionally, the first reset branch includes: a fifth NMOS tube, the first end of which is coupled with the first node, the second end of which is coupled with the first end of the sixth NMOS tube, and the grid electrode of which receives the first output signal; and the second end of the sixth NMOS tube is grounded, and the grid electrode of the sixth NMOS tube receives the second output signal.
Optionally, the second trigger branch includes: the first end of the second PMOS tube is coupled with the output end of the second input unit, the second end of the second PMOS tube is coupled with the grid electrode of the third NMOS tube, and the grid electrode receives a second signal; the first end of the fourth PMOS tube is coupled with the power supply, the second end of the fourth PMOS tube is coupled with the first end of the third NMOS tube, the coupling part is a second node, and the grid electrode receives a second signal; the second end of the third NMOS tube is coupled with the first end of the fourth NMOS tube; and the second end of the fourth NMOS tube is grounded, and the grid electrode of the fourth NMOS tube receives the second signal.
Optionally, the second reset branch includes: a seventh NMOS tube, the first end of which is coupled with the second node, the second end of which is coupled with the first end of the eighth NMOS tube, and the grid electrode of which receives the first output signal; and the second end of the eighth NMOS tube is grounded, and the grid electrode of the eighth NMOS tube receives the second output signal.
Optionally, one of the first end and the second end of the PMOS tube and the NMOS tube is a drain, and the other is a source.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the first input unit and the second input unit are respectively arranged in the first signal phase discrimination branch and the second signal phase discrimination branch so as to control the output of the branch where the first signal and the second signal arrive at when the rising edge of the first signal arrives, specifically, if the phase difference between the first signal and the second signal is larger than pi, when the rising edge of the first signal arrives, the first signal phase discrimination branch outputs high level, and when the rising edge of the second signal arrives, the second signal phase discrimination branch still keeps low level output, thus, the output of the first signal phase discrimination branch is not reset to low level until the phase difference between the two input signals is not larger than pi, thereby thoroughly preventing the generation of dead zones, leading the voltage-controlled oscillator in the charge pump phase-locked loop to continuously adjust the frequency of the feedback signal, and further accelerating the capturing process of the whole circuit.
Drawings
Fig. 1 is a schematic diagram of a prior art phase frequency detector;
fig. 2 is a schematic diagram of a prior art phase frequency detector blind zone;
fig. 3 is a schematic diagram of another prior art phase frequency detector;
fig. 4 is a schematic diagram of another prior art phase frequency detector;
fig. 5 is a schematic diagram of a frame structure of a phase frequency detector circuit according to an embodiment of the present invention;
fig. 6 is a schematic circuit diagram of a phase frequency detector circuit according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a NOR gate circuit of one embodiment of the present invention; and
fig. 8 is a schematic diagram of a simulation of the phase frequency detector circuit of fig. 6.
Detailed Description
For convenience of description and understanding, fig. 1 shows a schematic structure of a conventional phase frequency detector in the prior art, where the conventional phase frequency detector includes: a first D flip-flop 11, a second D flip-flop 12, an and gate 13 and a delay unit 14. If the phase of the first input signal S1 is higher than that of the second input signal S2, the first output terminal UP outputs a high level when the rising edge of the first input signal S1 arrives; when the rising edge of the second input signal S2 comes, the second output terminal DN outputs a high level, and when the first output terminal UP and the second output terminal DN both output a high level, the first D flip-flop 11 and the second D flip-flop 12 are reset by the reset signal Rst generated by the and gate 13 and the delay unit 14, and the pulse width difference of the first output signal UP and the second output signal DN is proportional to the phase difference between the input signals. If the phase of the first input signal S1 lags behind the second input signal S2, the operation principle is the same as that described above. The first input signal S1 may be a reference signal and the second input signal S2 may be a feedback signal.
Referring to fig. 2, fig. 2 is a schematic diagram of a blind zone of a phase frequency detector according to the prior art. As can be seen from the figure, when the phase difference of the two input signals S1, S2 approaches 2pi, the second rising edge of the first input signal S1 comes when the reset signal Rst is active, so that the second rising edge of the first input signal S1 is not detected by the phase frequency detector, which is the blind spot problem described above.
Fig. 3 shows a schematic diagram of another prior art phase frequency detector for the dead zone problem. The improved phase frequency detector comprises a plurality of PMOS tubes: PM1-PM4, a plurality of NMOS tubes: NM1-NM10 and a plurality of inverters: I1-I6. Compared with the traditional phase frequency detector shown in fig. 2, the improved phase frequency detector introduces the first input signal S1 and the second input signal S2 into two reset paths respectively, and effectively reduces the dead zone by judging the height of the input signals in the reset paths.
Fig. 4 is a schematic diagram of another phase frequency detector in the prior art, and it can be seen from fig. 4 that if the phase of the first input signal is preferential, the first output signal UP is high when the phase of the first input signal S1 and the phase of the second input signal S2 differ by pi or more. However, at time t41, the phase difference between the first input signal S1 and the second input signal S2 is 2pi, and rising edges of the two input signals arrive at the same time, referring to fig. 3, the first output signal UP, the second output signal DN, and the first input signal S1 are all at high level, so that the NMOS transistor NM1, the NMOS transistor NM2, and the NMOS transistor NM3 are turned on, the voltage of the node U1 is pulled down to low level, the NMOS transistor NM4 and the NMOS transistor NM5 are turned on, the node U2 outputs high level, and the first output terminal UP outputs low level.
As described above, when the phase difference between two input signals is 2pi, the output end corresponding to the input signal with the phase priority cannot maintain the high-level output, and the problem of dead zone is still not thoroughly solved.
In order to solve the problems, the invention is provided with the first input unit and the second input unit so as to control the output of the branch where the first signal and the second signal are located when the rising edge of the first signal and the second signal arrives, thereby thoroughly preventing the generation of dead zones and accelerating the capturing process of the whole circuit.
In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, a detailed description of specific embodiments of the present invention is provided below with reference to the accompanying drawings.
Fig. 5 is a schematic diagram of a frame structure of a phase frequency detector circuit according to an embodiment of the present invention. The phase frequency detector circuit comprises a first signal phase detection branch circuit 51 and a second signal phase detection branch circuit 52, wherein the first signal phase detection branch circuit 51 is used for outputting a first output signal according to a first signal, and the first output signal is related to the first signal; the second signal phase-discriminating branch 52 is configured to output a second output signal according to a second signal, where the second output signal is related to a rising edge of the second signal, and the phase of the first signal is higher than that of the second signal, and the phase difference range is [0,2 pi ]. The structures of the first signal phase-discriminating leg 51 and the second signal phase-discriminating leg 52 are symmetrical.
In some embodiments, the first signal may be a reference signal and the second signal may be a feedback signal. Of course, the first signal may be a feedback signal, and the second signal may be a reference signal. Those skilled in the art will appreciate that in implementations, both the reference signal and the feedback signal may be phase-first signals.
In some embodiments, the first signal phase-discriminating branch 51 includes a first input unit 511, a first flip-flop 512 and a first inverter 513, and the first input unit 511 is adapted to output a first nor signal to the first flip-flop 512 according to the second signal and the second memory signal.
The first flip-flop 512 is adapted to output a first memory signal according to a first signal, a first nor signal, a first output signal and a second output signal, the first inverted signal being opposite in phase to the first output signal, the first memory signal being associated with a rising edge of the first signal.
In some embodiments, the first flip-flop 512 includes a first flip-flop 5121 and a first memory 5122, wherein the first flip-flop 5121 is adapted to output a first flip-flop signal according to a first signal, a first nor signal, a first output signal, and a second output signal, the first flip-flop signal being low when the first signal and the second signal are not more than pi in phase difference, and the first output signal and the second output signal are both high, and being kept high when the first signal and the second signal are more than pi in phase difference.
The first trigger circuit 5121 includes a first trigger branch 51211 and a first reset branch 51212. The first triggering branch 51211 is adapted to output a high signal in accordance with a first signal, a first nor signal; and one end of the first reset branch 51212 is connected to the output end of the first trigger branch 51211, and is adapted to reset the high level signal output by the first trigger branch 51211 to a low level when the first output signal and the second output signal are both at a high level.
The first memory circuit 5122 is adapted to output a first memory signal according to a first signal and a first trigger signal, if the phase difference between the first signal and the second signal is not greater than pi, when the first signal is at a low level, the first memory signal is consistent with the first trigger signal, when the first signal is at a high level, the first memory signal is opposite to the first trigger signal, if the phase difference between the first signal and the second signal is greater than pi, and when the rising edge of the first signal comes, the first memory signal jumps to a low level and is maintained.
The first inverter 513 is adapted to invert the first memory signal and output a first output signal.
In some embodiments, the second signal phase-discriminating branch 52 includes a second input unit 521, a second flip-flop 522, and a second inverter 523, and the second input unit 521 is adapted to output a second nor signal to the second flip-flop 522 according to the first signal and the first memory signal.
The second flip-flop 522 is adapted to output a second memory signal according to a second signal, a second nor signal, a first output signal and a second output signal, wherein the second memory signal is opposite to the second output signal in phase, and the second memory signal is related to a rising edge of the second signal.
In some embodiments, the second flip-flop 522 includes a second flip-flop circuit 5221 and a second memory circuit 5222, wherein the second flip-flop circuit 5221 is adapted to output a second flip-flop signal according to a second signal, a second nor signal, a first output signal and a second output signal, the second flip-flop signal being low when the first signal and the second signal are not more than pi in phase difference and the first output signal and the second output signal are both high in level and being opposite to the second signal in potential when the first signal and the second signal are more than pi in phase difference.
The second trigger circuit 5221 includes a second trigger branch 52211 and a second reset branch 52212. The second trigger branch 52211 is adapted to output a high-level signal according to the second signal, the second or the non-signal if the phase difference between the first signal and the second signal is not greater than pi, and the output signal is opposite to the potential of the second signal if the phase difference between the first signal and the second signal is greater than pi; and one end of the second reset branch 52212 is connected with the output end of the second trigger branch, and is suitable for resetting the second trigger signal to a low level when the first output signal and the second output signal are both at a high level.
The second memory circuit 5222 is adapted to output a second memory signal according to the second signal and the second trigger signal, and if the phase difference between the first signal and the second signal is not greater than pi, the second memory signal is consistent with the second trigger signal when the second signal is at a low level, and is opposite to the second trigger signal when the second signal is at a high level, the phase difference between the first signal and the second signal is greater than pi, and the second memory signal is kept at a high level.
The second inverter 523 is adapted to invert the second memory signal and output a second output signal.
In a preferred application scenario, if the phase difference between the first signal and the second signal is not greater than pi, the first signal phase-discriminating branch 51 outputs a high level when the phase-prioritized first signal rising edge arrives. Specifically, when the first signal is at a low level, the first nor signal is at a low level, the first trigger signal outputted by the first trigger circuit 5121 is at a high level, and when the rising edge of the first signal arrives, the first memory circuit 5122 outputs a low level, the first inverter 513 inverts the first memory signal at a low level, and the outputted first output signal is at a high level; when the rising edge of the second signal arrives, the second signal phase-discriminating branch 52 outputs a high level, and the specific operation principle is the same as that of the first signal phase-discriminating branch 51.
When the first output signal and the second output signal are both high level, the first trigger signal and the second trigger signal are both low level, the first memory signal and the second memory signal are both high level, and the first output signal and the second output signal are both reset to low level.
If the phase difference between the first signal and the second signal is greater than pi, the first output signal is high when the rising edge of the first signal arrives, and the specific principle is as described above. When the rising edge of the second signal arrives, the second trigger circuit 5221 outputs a low level and the second memory circuit 5222 outputs a high level, so that the second signal phase-discriminating branch 52 outputs a low level until the phase difference of the two input signals is not greater than pi. Since the first output signal and the second output signal cannot be at high level at the same time, the first signal phase-discriminating branch 51 continuously outputs high level.
In summary, with the scheme of the first embodiment, if the phase difference between the first signal and the second signal is greater than pi, when the rising edge of the first signal arrives, the first signal phase-discriminating branch 51 outputs a high level, and when the rising edge of the second signal arrives, the second signal phase-discriminating branch 52 still keeps a low level output, and the output of the first signal phase-discriminating branch 51 is not reset to a low level until the phase difference between the two input signals is not greater than pi, so that the generation of dead zones can be thoroughly prevented. Meanwhile, the first signal phase discrimination branch 51 continuously outputs high level, so that the voltage-controlled oscillator in the charge pump phase-locked loop can continuously adjust the frequency of the feedback signal, and the capturing process of the whole circuit is further accelerated.
Fig. 6 is a schematic circuit diagram of a phase frequency detector circuit according to another embodiment of the present invention. Specifically, in the present embodiment, the first input unit 511 includes a first NOR gate NOR1, which receives the second signal S2 and the second memory signal DNN and outputs the first NOR signal SNOR1 to the first trigger circuit 5121.
In some embodiments, the first triggering branch 51211 includes: the first PMOS MP1, a first end of the first PMOS MP1 is coupled to the output end of the first input unit 511, receives the first nor signal SNOR1, and a second end is coupled to the gate of the first NMOS MN1, where the gate receives the first signal S1; the first end of the third PMOS tube MP3 is coupled with a power supply, the second end of the third PMOS tube MP3 is coupled with the first end of the first NMOS tube MN1, the coupling position is a first node U1, a first trigger signal is output, and the grid electrode receives a first signal S1; the second end of the first NMOS tube MN1 is coupled with the first end of the second NMOS tube MN 2; the second NMOS transistor MN2, where the second end of the second NMOS transistor MN2 is grounded, and the gate receives the first signal S1.
In some embodiments, the first reset branch 51212 includes: a fifth NMOS transistor MN5, where a first end of the fifth NMOS transistor MN5 is coupled to the first node U1, a second end of the fifth NMOS transistor MN5 is coupled to a first end of the sixth NMOS transistor MN6, and the gate receives the first output signal UP; and the second end of the sixth NMOS tube MN6 is grounded, and the grid electrode receives a second output signal DN. In an implementation, the first trigger signal SF1 is a level value at the first node U1.
In some embodiments, the first memory circuit 5122 includes: a fifth PMOS MP5, wherein a first end of the fifth PMOS MP5 is coupled to the power supply, a second end is coupled to a first end of the ninth NMOS MN9, the coupling is a third node U3, and the gate is coupled to the first node U1; a ninth NMOS transistor MN9, wherein a second end of the ninth NMOS transistor MN9 is coupled to the tenth NMOS transistor MN10, and a gate receives the first signal S1; and a tenth NMOS transistor MN10, wherein a second end of the tenth NMOS transistor MN10 is grounded, and a gate is coupled with the first node U1. In an embodiment, the first memory signal UPN is a level value at the third node U3.
In some embodiments, the first inverter 513 includes: a seventh PMOS MP7, where a first end of the seventh PMOS MP7 is coupled to the power supply, a second end of the seventh PMOS MP7 is coupled to a first end of the thirteenth NMOS MN13, and outputs a first output signal UP, and a gate is coupled to the third node U3; a thirteenth NMOS transistor MN13, the second end of the thirteenth NMOS transistor MN13 is grounded, and the gate is coupled to the third node U3.
In this embodiment, the second input unit 521 includes a second NOR gate NOR2, which receives the first signal S1 and the first memory signal UPN and outputs the second NOR signal SNOR2 to the second trigger circuit 5221.
In some embodiments, the second triggering branch 52211 includes: the second PMOS MP2, a first end of the second PMOS MP2 is coupled to the output end of the second input unit 521, receives the second nor signal SNOR2, a second end is coupled to the gate of the third NMOS MN3, and the gate receives the second signal S2; the first end of the fourth PMOS tube MP4 is coupled with a power supply, the second end of the fourth PMOS tube MP4 is coupled with the first end of the third NMOS tube MN3, the coupling position is a second node U2, and the grid electrode receives a second signal S2; the second end of the third NMOS tube MN3 is coupled with the first end of the fourth NMOS tube MN 4; and the second end of the fourth NMOS tube MN4 is grounded, and the grid electrode receives the second signal S2.
In some embodiments, the second reset branch 52212 includes: a seventh NMOS MN7, where a first end of the seventh NMOS MN7 is coupled to the second node U2, a second end of the seventh NMOS MN8 is coupled to a first end of the eighth NMOS MN8, and the gate receives the first output signal UP; and the second end of the eighth NMOS tube MN8 is grounded, and the grid electrode receives a second output signal DN. In an embodiment, the second trigger signal SF2 is a level value at the second node U2.
In some embodiments, the second memory circuit 5222 includes: the first end of the sixth PMOS tube MP6 is coupled with a power supply, the second end of the sixth PMOS tube MP6 is coupled with the first end of the eleventh NMOS tube MN11, the coupling position is a fourth node U4, and the grid electrode is coupled with a second node U2; an eleventh NMOS transistor MN11, wherein the second end of the eleventh NMOS transistor MN11 is coupled to the twelfth NMOS transistor MN12, and the gate receives the second signal S2; a twelfth NMOS transistor MN12, a second end of the twelfth NMOS transistor MN12 is grounded, and a gate is coupled to the second node U2. In an embodiment, the second memory signal DNN is a level value at the third node U3.
In some embodiments, the second inverter 523 includes: an eighth PMOS MP8, where a first end of the eighth PMOS MP8 is coupled to the power supply, a second end of the eighth PMOS MP8 is coupled to a first end of the fourteenth NMOS MN14, and outputs a second output signal DN, and a gate is coupled to the fourth node U4; the fourteenth NMOS transistor MN14, the second end of the fourteenth NMOS transistor MN14 is grounded, and the gate is coupled to the fourth node U4.
Fig. 7 is a schematic diagram of a NOR gate circuit including the first NOR gate NOR1 and the second NOR gate NOR2 shown in fig. 6 according to an embodiment of the present invention. It will be appreciated by those skilled in the art that the first NOR gate NOR1 and the second NOR gate NOR2 structures shown in fig. 6 are not limited to the NOR gate structures shown in the present embodiment.
In some embodiments, the nor gate includes a first input terminal a, a second input terminal B, an output terminal Z, and a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, a fifteenth NMOS transistor MN15, and a sixteenth NMOS transistor MN16. Specifically, the first input terminal a is coupled to the gate of the ninth PMOS MP9 and the gate of the fifteenth NMOS MN15, respectively; the second input end B is respectively coupled with the grid electrode of the tenth PMOS tube MP10 and the grid electrode of the sixteenth NMOS tube MN 16; the output end Z is respectively coupled with the second end of the tenth PMOS tube MP10, the first end of the fifteenth NMOS tube MN15 and the first end of the sixteenth NMOS tube MN 16; in addition, the first end of the ninth PMOS MP9 is coupled to the power supply, and the second end is coupled to the first end of the tenth PMOS MP 10; the second end of the fifteenth NMOS transistor MN15 is grounded, and the second end of the sixteenth NMOS transistor MN16 is grounded.
In a specific implementation, if the input signals received by the first input terminal a and the second input terminal B are both low level, the signal output by the output terminal Z is high level, otherwise, the output terminal Z outputs low level.
Those skilled in the art will appreciate that the first end of each MNOS tube and PMOS tube described above may be a drain, and the second end may be a source. That is, the first end may be a source electrode and the second end may be a drain electrode. The arrangement of the source electrode and the drain electrode of the MOS tube in the method does not influence the technical effect of the scheme.
Fig. 8 is a schematic diagram of a simulation of the phase frequency detector circuit of fig. 6. The operation principle of the phase frequency detector circuit provided in this embodiment will be described in detail with reference to fig. 6 and 8. Those skilled in the art will appreciate that in implementations, both the reference signal and the feedback signal may be phase-first signals.
If the phase difference between the first input signal S1 and the second input signal S2 with the phase priority is not greater than pi, before time t81, since the first input signal S1 is at low level, the third PMOS transistor MP3 is turned on, the second NMOS transistor MN2 is turned off, the first node U1 is charged to high level, the fifth PMOS transistor MP5 and the ninth NMOS transistor MN9 are turned off, the tenth NMOS transistor MN10 is turned on, and the first memory signal UPN is at high level.
At time t81, the rising edge of the first input signal S1 arrives, the first NOR gate NOR1 outputs a low level, the first trigger signal SF1 on the node U1 is still at a high level, but the ninth NMOS transistor MN9 is turned on, the first memory signal UPN is pulled down to a low level, so the seventh PMOS transistor MP7 is turned on, the thirteenth NMOS transistor MN13 is turned off, and the first output signal UP changes to a high level.
Before time t82, since the second input signal is at low level, the fourth PMOS transistor MP4 is turned on, the fourth NMOS transistor MN4 is turned off, the second node U2 is charged to high level, the sixth PMOS transistor MP6 and the eleventh NMOS transistor MN11 are turned off, the second NMOS transistor MN12 is turned on, and the second memory signal DNN is at high level.
At time t82, the rising edge of the second input signal S2 arrives, the second NOR gate NOR2 outputs a low level, the second trigger signal SF2 on the node U2 is still at a high level, but the eleventh NMOS transistor MN11 is turned on, the second memory signal DNN is pulled down to a low level, so the eighth PMOS transistor MP8 is turned on, the fourteenth NMOS transistor MN14 is turned off, and the second output signal DN becomes a high level.
When the first output signal UP and the second output signal DN are both at a high level, the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are turned on, the first trigger signal SF1 at the first node U1 becomes a low level, so that the fifth PMOS transistor MP5 turns on the tenth NMOS transistor MN10 and turns off, the first memory signal UPN at the third node becomes a high level, and thus the seventh PMOS transistor MP7 turns off, the thirteenth NMOS transistor MN13 turns on, and the first output signal UP output by the first signal phase-discriminating branch 51 becomes a low level. Similarly, when the first output signal UP and the second output signal DN are both high, the second output signal DN is also reset to low.
If the phase difference between the first signal S1 and the second signal S2 with the phase priority is greater than pi, for example, before time t83, the first signal S1 is at a low level, the first node U1 is charged to a high level, the fifth PMOS transistor MP5 is turned off, and the tenth NMOS transistor MN10 is turned on.
At time t83, the rising edge of the first signal S1 arrives, the first NOR gate NOR1 outputs a low level, the first trigger signal SF1 on the node U1 remains at a high level, the ninth NMOS transistor MN9 is turned on, the first memory signal UPN becomes a low level, the seventh PMOS transistor MP7 is turned on, the thirteenth NMOS transistor MN13 is turned off, and the first output signal is at a high level.
For the second signal phase-discriminating branch 52, for example, before time t84, since the first signal S1 and the first memory signal UPN are both at low level, the second NOR gate NOR2 outputs high level, the second PMOS transistor MP2 is turned on at low level, and the third NMOS transistor MN3 is turned on.
At time t84, the rising edge of the second signal S2 comes, the fourth PMOS transistor MP4 is turned off, the fourth NMOS transistor is turned on, the second trigger signal SF2 at the second node U2 is pulled to a low level, the sixth PMOS transistor MP6 is turned on, and the twelfth NMOS transistor MN12 is turned off. Therefore, even if the eleventh NMOS transistor MN11 is turned on due to the second signal S2 becoming high, the second memory signal DNN still outputs high, and the second signal phase-discriminating branch 52 outputs low after being inverted by the second inverter 523. Therefore, the first output signal UP is not reset to the low level.
In summary, if the phase difference between the first signal S1 and the second signal S2 is greater than pi, the first output signal UP is at a high level when the rising edge of the first signal S1 arrives, and the second output signal DN is kept at a low level when the rising edge of the second signal S2 arrives.
Compared with the improved phase frequency detector shown in fig. 3, the phase frequency detector circuit shown in this embodiment still can keep the high level output of the first output signal UP and keep the low level output of the second output signal DN when the phase difference between the first signal S1 and the second signal S2 is 2 pi. The specific working principle of the phase frequency detector circuit when the phase difference of the input signals is 2 pi is as follows.
Referring to fig. 8, before time t85, the first signal S1 and the first memory signal UPN both output a low level, the second NOR gate NOR2 outputs a high level, and the second PMOS transistor MP2 is turned on due to the low level of the second signal S2, so that the third NMOS transistor MN3 is turned on.
Although the first signal S1 goes high to cause the second nor signal SNOR2 to go low at time t85, the second PMOS transistor MP2 is turned off because the rising edge of the second signal S2 arrives at the same time, so the third NMOS transistor MN3 remains on, and the fourth NMOS transistor MN4 is turned on, so the second off signal SF2 at the second node U2 remains low, and the second output signal DN remains low. The details of the intermediate process are as described above and are not described in detail herein. And since the second output signal DN remains low, the first output signal UP will not be reset low and will continue to remain high.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (10)

1. A phase frequency detector circuit, comprising:
the first signal phase discrimination branch is used for outputting a first output signal according to a first signal, and the first output signal is related to the rising edge of the first signal;
the second signal phase discrimination branch is used for outputting a second output signal according to a second signal, the second output signal is related to the rising edge of the second signal, the phase of the first signal is higher than that of the second signal, and the phase difference range is [0,2 pi ];
if the phase difference between the first signal and the second signal is larger than pi, the first output signal is kept at a high level after the rising edge of the first signal comes, and the second output signal is kept at a low level after the rising edge of the second signal comes;
if the phase difference between the first signal and the second signal is not greater than pi, when rising edges of the first signal and the second signal come, both the first output signal and the second output signal jump to high level;
the first signal phase discrimination branch circuit comprises:
the first input unit comprises a first NOR gate, the first NOR gate is suitable for receiving a second signal and a second memory signal, the first NOR gate outputs the first NOR signal to the first trigger, and the second memory signal is generated by the second trigger;
the first trigger is suitable for outputting a first memory signal according to a first signal, a first NOR signal, a first output signal and a second output signal, and the phase of the first memory signal is opposite to that of the first output signal;
the first inverter is used for inverting the first memory signal and outputting a first output signal;
the second signal phase discrimination branch circuit comprises:
the second input unit comprises a second NOR gate, the second NOR gate is suitable for receiving a first signal and a first memory signal, outputting the second NOR signal to a second trigger, and the first memory signal is generated by the first trigger;
the second trigger is suitable for outputting a second memory signal according to a second signal, a second NOR signal, a first output signal and a second output signal, and the second memory signal is opposite to the second output signal in phase;
and the second inverter is used for inverting the second memory signal and outputting a second output signal.
2. The phase frequency detector circuit of claim 1, wherein the first flip-flop comprises:
the first trigger circuit is suitable for outputting a first trigger signal according to a first signal, a first NOR signal, a first output signal and a second output signal, wherein the first trigger signal is low level when the phase difference of the first signal and the second signal is not more than pi and the first output signal and the second output signal are both high level, and is kept high level when the phase difference of the first signal and the second signal is more than pi;
the first memory circuit is suitable for outputting a first memory signal according to a first signal and a first trigger signal, if the phase difference of the first signal and the second signal is not more than pi, when the first signal is at a low level, the first memory signal is consistent with the first trigger signal, when the first signal is at a high level, the first memory signal is opposite to the first trigger signal, if the phase difference of the first signal and the second signal is more than pi, and when the rising edge of the first signal arrives, the first memory signal jumps to a low level and is kept.
3. The phase frequency detector circuit of claim 2, wherein the first trigger circuit comprises:
the first trigger branch is suitable for outputting a high-level signal according to the first signal, the first nor signal;
and one end of the first reset branch is connected with the output end of the first trigger branch, and is suitable for resetting the high-level signal output by the first trigger branch to be low level when the first output signal and the second output signal are both high level.
4. The phase frequency detector circuit of claim 1, wherein the second flip-flop comprises:
the second trigger circuit is suitable for outputting a second trigger signal according to a second signal, a second NOR signal, a first output signal and a second output signal, wherein the second trigger signal is in a low level when the phase difference of the first signal and the second signal is not more than pi and the first output signal and the second output signal are both in a high level, and is opposite to the second signal potential when the phase difference of the first signal and the second signal is more than pi;
the second memory circuit is suitable for outputting a second memory signal according to a second signal and a second trigger signal, if the phase difference of the first signal and the second signal is not more than pi, when the second signal is in a low level, the second memory signal is consistent with the second trigger signal in potential, when the second signal is in a high level, the second memory signal is opposite to the second trigger signal in potential, the phase difference of the first signal and the second signal is more than pi, and the second memory signal keeps in high level output.
5. The phase frequency detector circuit of claim 4, wherein the second trigger circuit comprises:
the second trigger branch is suitable for outputting a high-level signal according to the second signal and the second or non-signal if the phase difference between the first signal and the second signal is not more than pi, and outputting a signal with opposite potential to the second signal if the phase difference between the first signal and the second signal is more than pi;
and one end of the second reset branch is connected with the output end of the second trigger branch, and is suitable for resetting the second trigger signal to a low level when the first output signal and the second output signal are both at a high level.
6. A phase frequency detector circuit according to claim 3, wherein the first trigger branch comprises:
the first PMOS tube has a first end coupled with the output end of the first input unit, a second end coupled with the grid of the first NMOS tube, and the grid receives a first signal;
the first end of the third PMOS tube is coupled with the power supply, the second end of the third PMOS tube is coupled with the first end of the first NMOS tube, the coupling part is a first node, a first trigger signal is output, and the grid electrode receives the first signal;
the second end of the first NMOS tube is coupled with the first end of the second NMOS tube;
and the second end of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube receives the first signal.
7. The phase frequency detector circuit of claim 6, wherein the first reset leg comprises:
a fifth NMOS tube, the first end of which is coupled with the first node, the second end of which is coupled with the first end of the sixth NMOS tube, and the grid electrode of which receives the first output signal;
and the second end of the sixth NMOS tube is grounded, and the grid electrode of the sixth NMOS tube receives the second output signal.
8. The phase frequency detector circuit of claim 5, wherein the second trigger branch comprises:
the first end of the second PMOS tube is coupled with the output end of the second input unit, the second end of the second PMOS tube is coupled with the grid electrode of the third NMOS tube, and the grid electrode receives a second signal;
the first end of the fourth PMOS tube is coupled with the power supply, the second end of the fourth PMOS tube is coupled with the first end of the third NMOS tube, the coupling part is a second node, and the grid electrode receives a second signal;
the second end of the third NMOS tube is coupled with the first end of the fourth NMOS tube;
and the second end of the fourth NMOS tube is grounded, and the grid electrode of the fourth NMOS tube receives the second signal.
9. The phase frequency detector circuit of claim 8, wherein the second reset branch comprises:
a seventh NMOS tube, the first end of which is coupled with the second node, the second end of which is coupled with the first end of the eighth NMOS tube, and the grid electrode of which receives the first output signal;
and the second end of the eighth NMOS tube is grounded, and the grid electrode of the eighth NMOS tube receives the second output signal.
10. A phase frequency detector circuit according to any one of claims 6 to 9, wherein one of the first and second ends of the PMOS and NMOS transistors is a drain and the other is a source.
CN201810318222.6A 2018-04-10 2018-04-10 Phase frequency detector circuit Active CN110365329B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810318222.6A CN110365329B (en) 2018-04-10 2018-04-10 Phase frequency detector circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810318222.6A CN110365329B (en) 2018-04-10 2018-04-10 Phase frequency detector circuit

Publications (2)

Publication Number Publication Date
CN110365329A CN110365329A (en) 2019-10-22
CN110365329B true CN110365329B (en) 2023-04-21

Family

ID=68213995

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810318222.6A Active CN110365329B (en) 2018-04-10 2018-04-10 Phase frequency detector circuit

Country Status (1)

Country Link
CN (1) CN110365329B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101098140A (en) * 2007-06-28 2008-01-02 北京大学深圳研究生院 Fast locked frequency discrimination phase discriminator
CN101388666A (en) * 2008-10-10 2009-03-18 哈尔滨工业大学 Non-linear frequency and phase discriminator without phase discriminating blind zone
CN101826868A (en) * 2009-12-29 2010-09-08 国民技术股份有限公司 Charge pump type phaselocked loop circuit comprising frequency discriminator without dead zone
CN107302356A (en) * 2017-06-08 2017-10-27 中国电子科技集团公司第三十六研究所 A kind of reset delay phase frequency detector and a kind of phase-locked loop frequency synthesizer

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2344787A1 (en) * 2001-04-19 2002-10-19 Pmc-Sierra Ltd. A phase detector customized for clock synthesis unit
KR100668360B1 (en) * 2004-11-09 2007-01-16 한국전자통신연구원 Phase frequency detector
US7388408B2 (en) * 2006-05-16 2008-06-17 Via Technologies Inc. Phase-frequency detector capable of reducing dead zone
US20120112805A1 (en) * 2010-11-10 2012-05-10 Hynix Semiconductor Inc. Phase-frequency detector
US9444471B2 (en) * 2013-06-06 2016-09-13 Freescale Semiconductor, Inc. Phase detector and phase-locked loop

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101098140A (en) * 2007-06-28 2008-01-02 北京大学深圳研究生院 Fast locked frequency discrimination phase discriminator
CN101388666A (en) * 2008-10-10 2009-03-18 哈尔滨工业大学 Non-linear frequency and phase discriminator without phase discriminating blind zone
CN101826868A (en) * 2009-12-29 2010-09-08 国民技术股份有限公司 Charge pump type phaselocked loop circuit comprising frequency discriminator without dead zone
CN107302356A (en) * 2017-06-08 2017-10-27 中国电子科技集团公司第三十六研究所 A kind of reset delay phase frequency detector and a kind of phase-locked loop frequency synthesizer

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
Detection of the Phase Shift from a Single Abrikosov Vortex;T. Golod等;《Physical Review Letters》;20101231;第104卷(第22期);全文 *
基于相位差限制技术的快速锁定锁相环;曹原等;《中国高新技术企业》;20121001(第28期);全文 *
高速低功耗饱和输出鉴频鉴相器的设计;金牡丹等;《科技创新与应用》;20170228(第06期);全文 *

Also Published As

Publication number Publication date
CN110365329A (en) 2019-10-22

Similar Documents

Publication Publication Date Title
US8324949B2 (en) Adaptive quadrature correction for quadrature clock path deskew
US7302026B2 (en) Clock recovery circuit and electronic device using a clock recovery circuit
US20040008063A1 (en) Delay locked loop clock generator
US11218152B2 (en) Charge pump circuit and phase-locked loop
EP3549263B1 (en) Wide capture range reference-less frequency detector
KR20000017468A (en) PLL circuit and method of controlling the same
JP5332328B2 (en) Clock and data recovery circuit
US7656206B2 (en) Phase-locked loop circuit
CN109639268B (en) D trigger and phase frequency detector circuit
JP2011223375A (en) Oscillation circuit
EP2752993B1 (en) Phase frequency detector circuit
US20210281266A1 (en) Voltage-controlled oscillator and pll circuit in which same is used
US6160434A (en) Ninety-degree phase shifter
CN110365329B (en) Phase frequency detector circuit
KR20100094859A (en) Asymmetric charge pump and phase locked loops having its
US5434545A (en) Fully differential voltage controlled oscillator
JP2012160927A (en) Delay control circuit, charge pump circuit, and method of controlling charge/discharge current in charge pump circuit
US9130555B2 (en) Data holding circuit and semiconductor integrated circuit device
KR20110130941A (en) Duty correcting circuit, delay-locked loop circuit including the duty correcting circuit, and method of duty correction
US20040160282A1 (en) Multi-loop oscillator
KR100261964B1 (en) Charge pump circuit
US6806741B2 (en) Phase comparator capable of performing stable phase comparison for high frequency band
KR101538537B1 (en) Charge pump and phase locked loop circuit
KR100990620B1 (en) Phase Detector
KR100990610B1 (en) Phase Detector

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant