CN110347638A - ASIC array, data processing board, and block mining method and apparatus - Google Patents
ASIC array, data processing board, and block mining method and apparatus Download PDFInfo
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- 238000009412 basement excavation Methods 0.000 claims description 10
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
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- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
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- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7825—Globally asynchronous, locally synchronous, e.g. network on chip
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Abstract
The invention relates to an ASIC array used for carrying out block mining, wherein an ASIC chip of the ASIC array is packaged with a plurality of bare chips provided with a network on chip, the network on chip comprises M multiplied by N computing nodes, the NoC addresses of the computing nodes are (M, N), the computing nodes adjacent to the NoC addresses are connected with each other, and the network on chip adopts a two-dimensional folding ring topology structure, so that the computing nodes adjacent to the NoC addresses have the same physical distance. The ASIC array of the invention adopts a two-dimensional folding ring topology structure, the forward and backward paths of the calculation nodes in the network on chip are staggered, and the links between the adjacent nodes in different directions have the same buffer and delay characteristics, thereby greatly simplifying the physical realization of the bare chip and the forwarding strategy of the network on chip.
Description
Technical field
The present invention relates to block chain technical fields, more particularly to a kind of method and apparatus excavated for block, and
Using the ASIC array and data processing board of the method that block excavates.
Background technique
Ether mill (Ethereum) is the block platform chain of a completely new evolution, it allows anyone to establish in platform
With use the decentralization application by block chain technical operation.The core in ether mill is point-to-point (P2P) network, ether
Mill block chain database is safeguarded and is updated by numerous nodes for being connected to network.
Fig. 1 is that the ether mill block of the prior art excavates schematic diagram.As shown in Figure 1, tranaction costs are collected by node, user
(Miner) 12 be exactly the node for collecting in ether mill network 10, propagating, confirming and execute transaction.Transaction is packaged as by users
Block, and compete with one another for, so that their block can be added on next block chain, this process is referred to as to dig mine.Mine
Block is excavated the business subcontract use inner to mine pond (Miningpool) on new block by pool server 11 (Pool server)
Family, it includes that block prefix hashed value, user it is expected the random number range and difficulty or ease that search that each, which digs parameter that miner makees,
Degree.
As block chain network, users successfully " are dug " by solving the problems, such as the task of complex mathematical to area
Block, this is referred to as " proof of work ".One operational problem needs more if algorithmically solved than verifying solution
The resource of the order of magnitude, then it is exactly the splendid selection of proof of work.It is special to prevent from having occurred and that in block chain network
Centralization phenomenon caused by hardware (such as application-specific IC), ether mill have selected to lay particular emphasis on the fortune for consuming more memories
Calculation problem.If problem needs memory and CPU, ideal hardware is exactly common computer.This just makes the workload in ether mill
Prove that there is the characteristic of anti-application-specific IC and this block chain phase excavated by specialised hardware control block of block chain
Than ether mill can bring being securely distributed for more decentralization.
The process of complex mathematical and the cpu performance zero correlation of block excavating equipment are solved the problems, such as, with block excavating equipment
Memory size and memory bandwidth are positively correlated, it means that the block excavation of those large scale deployments by way of shared drive is set
It is standby, linear or superlinearity (super-linear) growth can not be generated on block digging efficiency.
Patent application " a kind of modified ring topologies and its application method ", international publication number
WO2015176243A9 provides the modified ring topologies and its application method in a kind of photoelectric communication field.It is described to change
It is constituted into type ring topologies by m*n with the routing node that mesh topology is connected, including two close rings: the
The 1st routing node of K row is connect with n-th of routing node of K+1 row, the 1st road of the 2nd n-th of routing node of row and m-1 row
It is connected by node, so that all routing nodes of the 2nd row into m-1 row form the 1st close ring, 1 < K < m-1；J column
M-th of routing node arranges the 1st routing node with J+1 and connect, and the 2nd arranges the 1st routing node and m-th of the (n-1)th column routing
Node connection, so that all routing nodes of the 2nd column into the (n-1)th column form the 2nd close ring, 1 < J < n-1.More than
Technological means, it is possible to reduce the average communication transmission path of interaction between node reduces the transmission delay between node.
If but foregoing invention does not consider the unequal problem of the physical length of link between the node of network-on-chip, chain
The physical length on road is unequal may to need additional buffering for the information that will lead in network-on-chip transmitting in particular directions
And causing inconsistent delay, the forwarding strategy complexity of the physical Design and network-on-chip that lead to bare die rises.
Summary of the invention
Keep information transmitting delay in network-on-chip inconsistent for solution link physical length is unequal, and then leads to bare die
The problem of physical Design and the forwarding strategy complexity of network-on-chip rise, the invention discloses a kind of ASIC arrays, use this
The data processing plate of ASIC array, and use the data processing plate block excavating equipment and corresponding block method for digging.
Specifically, the invention discloses a kind of ASIC arrays, for carrying out block excavation, the ASIC core of the ASIC array
Piece is packaged with multiple bare dies for being provided with network-on-chip, which includes M × N number of calculate node, the NoC of the calculate node
Address is (m, n), and the adjacent calculate node in the address NoC is connected with each other by piece upper channel, which is folded using two dimension
Ring topology, wherein the two dimension folded coil topological structure be the line n of the network-on-chip calculate node physically
Location be followed successively by (0, n), (1, n) ..., (M-1, n) when, then the corresponding address NoC of the line n calculate node be followed successively by (0, n),
(M-1, n), (2, n), (M-2, n) ..., (N), the m of the network-on-chip arrange the physical address of the calculate node according to
It is secondary for (m, 0), (m, 1) ..., (m, N-1) when, then m arrange the corresponding address NoC of the calculate node be followed successively by (m, 0), (m,
N-1), (m, 1), (m, N-2) ..., (m,), wherein 0≤m≤M-1,0≤n≤N-1, M >=2, N >=2, and M, N, m, n
For integer.
Further, which includes 6 × 12 calculate nodes, which includes 2 bare dies, PCB electricity
4 × 4 asic chips are arranged in the one side of road plate, and 4 × 4 asic chips are arranged in the another side of the PCB circuit board.
The invention also discloses a kind of block method for digging, carry out block excavation, feature using above-mentioned ASIC array
It is, comprising: step 1, obtain the random data set for being excavated to current block；Step 2, which is drawn
It is divided into multiple subsets and is distributed the calculate node for being stored in the ASIC array；Step 3, a certain calculate node institute is arbitrarily chosen
A certain random number in the subset of preservation carries out first round address arithmetic to obtain destination address, with the destination address, according to this
Two-dimentional folded coil topological structure finds the correspondence calculate node of the destination address, and the son saved from the correspondence calculate node
Input of the correspondence random number of concentration as next round address arithmetic；It is random to be obtained after the address arithmetic of default wheel number
Number is target random number；Step 4, to the target random number carry out hash calculate to obtain target value, if the target value be less than or
Equal to difficulty threshold value, then using the target random number as the block random number of current block, using the target value as the area of current block
Block hashed value；It is on the contrary then abandon the target random number, and it re-execute the steps 3；Step 5, by the block random number and the block
The current block is written in hashed value, and the current block is broadcasted to block chain network；Step 6, when verifier receives broadcast
The current block when, verify the legitimacy of the current block, and enter block chain for legal current block chain is verified.
Further, which includes: current block head and current block body, wherein deserving before proparea build includes
Block hashed value, current block random number, current block hashed value and difficulty threshold value of one block.
The invention also discloses a kind of data processing plates excavated for block, including above-mentioned ASIC array, further includes:
The controller unit being connect with the ASIC array, for monitoring the ASIC array processing, to the ASIC array input data and defeated
The result that the ASIC array obtains out；Temperature management unit, including radiator and temperature sensor, wherein the temperature sensor is used
In the temperature for detecting the data processing plate and it is sent to the controller unit and/or the radiator, or controls the work of the power supply
State；The radiator is used to cool down for the data processing plate；Guidance unit is connect with the controller unit, for the control
The starting of device unit guides；Debugging unit is connect with the controller unit, for the controller unit to be debugged and provided
Tuning parameter.
Further, which is field programmable gate array.
The invention also discloses a kind of equipment excavated for block, including at least one above-mentioned data processing plate, also
It include: network communication module, for connecting block chain network to carry out data receiver and transmission；Task allocating module, being used for will
The data distribution obtained from the network gives the data processing plate, and the result that the data processing plate is obtained passes through the network communication
Module is sent to the network.
The two-dimentional folded coil topological structure that ASIC array of the invention uses, in network-on-chip calculate node it is preceding to it is rear
Interlock to path, it, can be great in different directions close to the buffering having the same of the link between node and delay feature
Simplify physics realization and the network-on-chip forwarding strategy of bare die.
Detailed description of the invention
Fig. 1 is that the ether mill block of the prior art excavates schematic diagram.
Fig. 2 is the ether mill block structure schematic diagram of the prior art.
Fig. 3 is block method for digging flow chart of the invention.
Fig. 4 is the ASIC array structure schematic diagram of first embodiment of the invention.
Fig. 5 is the network-on-chip two-dimensional annular topological structure schematic diagram of first embodiment of the invention.
Fig. 6 is the on piece channel direction schematic diagram between the calculate node of first embodiment of the invention.
Fig. 7 is access diagram between piece between the bare die of first embodiment of the invention.
Fig. 8 is access diagram between piece between the asic chip of first embodiment of the invention.
Fig. 9 A, 9B are one-dimensional foldable circle face topological structure schematic diagrames.
Figure 10 is the two-dimentional foldable circle face topological structure schematic diagram of first embodiment of the invention.
Figure 11 is the structural schematic diagram of the data processing plate based on ASIC array of second embodiment of the invention.
Figure 12 is the block excavating equipment structural schematic diagram of third embodiment of the invention.
Wherein, appended drawing reference are as follows:
10: ether mill 11: mine pool server
12: user's 100:ASIC array
110:ASIC chip 120: bare die
130: network-on-chip 140: node
140-1: calculate node 140-2: functional node
141: memory 142: mixed to calculate device
143: node communication module 144: piece upper channel
150: reflector node 160: channel between piece
161: link pair 162: link
170:PCB circuit board 180: serial parallel channel
200: data processing plate 210: controller unit
220: power supply 230: temperature sensor
240: fan 300: task allocating module
400: network communication module 500: block excavating equipment
RX: receiver TX: transmitter
E, S, W, N: port position
Specific embodiment
Below in conjunction with attached drawing, the present invention will be described in detail.In the accompanying drawings, identical label typicallys represent identical or function
It can similar component.In addition, the leftmost number of appended drawing reference shows the volume of that width attached drawing when the appended drawing reference first appears
Number.
Subject description discloses one or more embodiments comprising feature of the present invention.Disclosed embodiment is used only for lifting
Example explanation.Protection scope of the present invention is not limited to the disclosed embodiments.The present invention is defined by the following claims.Explanation
It is directed to the reference of " one embodiment ", " embodiment ", " example embodiment " etc. in book, refers to that the embodiment of description may include
Specific feature, structure or characteristic, each embodiment of but not must include these a particular feature, structure, or characteristics.In addition,
Such statement not refers to the same embodiment.Further, specific feature, structure or characteristic are being described in conjunction with the embodiments
When, regardless of either with or without specific description, it has been shown that such feature, structure or characteristic are integrated in other embodiments be
In the knowledge of those skilled in the art.
Some vocabulary is used in specification and following claims to censure specific components or component, this field
The member of ordinary skill, it is to be appreciated that technology user or manufacturer can be different noun or term come call the same component or
Component.This specification and following claims not in such a way that the difference of title is as component or component is distinguished, and
It is the criterion with component or component difference functionally as differentiation.In specification in the whole text and subsequent claim
Mentioned " comprising " and "comprising" is an open term, therefore should be construed to " including but not limited to ".In addition, " connection "
One word includes any direct and indirect means of electrical connection herein.Indirect means of electrical connection include by other devices into
Row connection.It should be noted that in the description of the present invention, term " transverse direction ", " longitudinal direction ", "upper", "lower", "front", "rear",
The orientation or positional relationship of the instructions such as "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outside" is based on attached drawing institute
The orientation or positional relationship shown, is merely for convenience of description of the present invention and simplification of the description, and is not the dress of indication or suggestion meaning
It sets or element must have a particular orientation, be constructed and operated in a specific orientation, therefore should not be understood as to limit of the invention
System.
Block chain is a kind of calculating and storage architecture, specifically a kind of distributed accounting system of decentralization, should
Node in system safeguards a account book without trusting each other, by unified common recognition mechanism jointly.And ether mill is a kind of energy
Enough it is reprogrammed the single block chain to realize arbitrarily complicated computing function.Fig. 2 is the ether mill block structure of the prior art
Schematic diagram.As shown in Fig. 2, the block structure in ether mill includes block head and block body, wherein block head includes that previous block dissipates
Train value, the block hashed value of this block, the block random number of this block, the difficulty threshold value for excavating this block etc., block body includes
The signature packet for the message that all external accounts issue in this block establishment process.The common recognition mechanism in ether mill is PoW
(Proof of Work proof of work mechanism), using Ethash algorithm, this algorithm is to Dagger-Hashimoto algorithm
Modified version, using a large amount of pseudo-random data, the set of these pseudo-random datas be referred to as " data set (dataset) " or
Referred to as DAG.The characteristics of Ethash algorithm is that the efficiency that block excavates and memory size and memory bandwidth are positively correlated, process packet
Include: for each block, calculating a seed (seed) first, seed only and current block it is information-related；Then basis
Seed generates the random data set (cache) of a 32M；(had according to the random data set DAG that cache generates a 1GB size
To acyclic graph), DAG is a complete search space, and the process that block excavates is exactly the random selection element (class from DAG
It is similar to search suitable Nonce in the block excavation of block chain) hash operations are carried out again, it is specified that DAG can be quickly calculated from Cache
The element of position, and then Hash verifying requires to periodically update Cache and DAG, every 1000 blocks update once, and
Provide the size linear increase as time goes by of DAG.
Since the proof of work in ether mill has the characteristic of anti-application-specific IC, the digital goods in ether mill
Coin --- in the excavation of ether coin, for ASIC relative to the common computer for using memory and CPU, there is no excellent in speed and efficiency
Gesture.Fig. 3 is block method for digging flow chart of the invention.As shown in figure 3, making the invention discloses a kind of block method for digging
The block excavation in ether mill can be used ASIC array and obtain higher speed and efficiency, specifically, block of the invention
Method for digging includes:
Step S1, the user in ether mill obtain the block body of current block, and for being excavated to current block
Random data set DAG；Wherein DAG is to be obtained by technological means known in Ethash algorithm, such as pass through such as keccak256
The hash of algorithm, which calculates, obtains seed, is calculated by the hash of such as keccak512 algorithm and generates cache according to seed, by such as
The hash of keccak512 algorithm, which is calculated, generates DAG etc. according to cache, and the present invention is not limited thereto；
Random data set DAG is divided into multiple random data set subsets by step S2, and by subset in the form of one-to-one
Distribution is stored in the memory of calculate node, so that the memory of each calculate node is stored with a pseudo random number subset；
Step S3 chooses input of a certain random number as first run address arithmetic in a certain subset, passes through address arithmetic
It is obtained the result is that a destination address, output of the corresponding random number of this destination address as epicycle address arithmetic, i.e.,
The random number of this output is for epicycle address arithmetic as a result, wherein the random number of this output is likely to be at the random number institute of input
Subset, it is also possible to be in another subset；With the destination address, which is found according to the two dimension folded coil topological structure
The correspondence calculate node of address is marked, and as next round from the correspondence random number in the subset that the correspondence calculate node is saved
The input of location operation carries out next round address arithmetic；After carrying out R wheel address arithmetic, using the address arithmetic result of acquisition as target
Random number；Wherein R is preset wheel number；Hash is carried out to the target random number of acquisition to calculate to obtain target value；
The target value of acquisition is compared by step S4 with the difficulty threshold value that current block excavates, if target value be less than or
Equal to difficulty threshold value, then using the target random number of acquisition as the block random number of current block, the target value with acquisition is current
The block hashed value of block；If target value is greater than difficulty threshold value, give up the corresponding target random number of this target value, and again
Execute step S3；
Step S5, by the block head of the step S4 block random number obtained and block hashed value write-in current block, to obtain
To complete current block, complete current block is broadcasted to ether mill.
Step S6, the other users (verifier) in ether mill are in the current block for receiving broadcast, according to current block
Block head included in the block hashed value of previous block, the block random number of current block, current block block dissipate
Train value and difficulty threshold value etc. verify the legitimacy of current block, and enter block chain for legal current block chain is verified.
According to above-mentioned block method for digging, a kind of ASIC array of the disclosed (ASIC Array) of the present invention, institute of the present invention
Disclosed ASIC array is connected between asic chip by high-speed link, and further includes multiple bare dies on each asic chip
(die), each bare die includes a network-on-chip (NoC, Network on Chip), and network-on-chip NoC has multiple calculating to save
Point, network-on-chip NoC have multiple calculate nodes, and each calculate node includes mixed calculation device, node communication module, memory etc..
Fig. 4 is the ASIC array structure schematic diagram of first embodiment of the invention.As shown in figure 4, real in of the invention first
Example is applied, ASIC array 100 includes PCB circuit board 170 and asic chip 110, and wherein asic chip 110 is set to PCB circuit board
170 upper bottom surface and bottom surface, in the upper bottom surface of PCB circuit board 170, asic chip 110 is 16, uniform in 4 × 4 array
Distribution, in the bottom surface of PCB circuit board 170, mirror image is dispersed with same amount of asic chip 110；Each asic chip 110 wraps
Include 2 bare dies 120 arranged side by side；Each bare die 120 includes a network-on-chip 130；Network-on-chip 130 includes 72 calculate nodes
(Node) 140 and 6 reflector nodes (Reflector) 150；Calculate node 140 includes memory (SRAM) 141, mixed calculation device
(Mixer) 142 and node communication module 143, each calculate node 140 has the memory of rMB.In this way, ASIC gusts entire
Column 100 then have a calculating section of a bare die 120,4608 (64 × 72) of a asic chip 110,64 (2 × 32) in 32 (2 × 4 × 4)
Point.
Fig. 5 is the two-dimensional annular topological structure schematic diagram of the network-on-chip of first embodiment of the invention.As shown in figure 5,72
A calculate node 140 is uniformly distributed in 6 × 12 arrays, and definition X is line direction, and Y is column direction, and network-on-chip 130 6 arranges totally, 12
Row also has 1 reflector node 150 in the bottommost of each column respectively, between calculate node 140-1, reflector node 150 and meter
Differential lines between operator node 140-1 by network-on-chip are formed by the interconnection of piece upper channel 144, have network-on-chip
Two-dimensional annular topological structure, wherein each calculate node 140-1 has 4 directly connected calculate node 140-1 to make
For close to node.And reflector node 150 is connected in the column of network-on-chip 130, only there are two close to node, without with it is other
Column connection.Fig. 6 is the on piece channel direction schematic diagram between the calculate node of first embodiment of the invention.As shown in fig. 6, with side
The piece that its immediate node of calculate node 140-1 in the two-dimensional annular topological structure of network-on-chip connects is indicated to E, W, S, N
The port position of upper channel 144, then reflector node 150 only has the direction N, S.
Fig. 7 is access diagram between piece between the bare die of first embodiment of the invention.As shown in fig. 7, between bare die 120
Piece between channel 160 include both links to (pair) 161, both links respectively correspond two directions toward each other to 161,
A transmitter TX and a receiver RX, direction corresponding to link pair 161 is respectively set in the endpoint of each link pair 161
It is determined by the position where transmitter TX and receiver RX.Each link pair 161 has both links 162, in this way, each
Between channel 160 include 4 links 162.Fig. 8 is access diagram between piece between the asic chip of first embodiment of the invention.
As shown in figure 8, being connected with each other between bare die 120 also by channel 160 between piece.Since each asic chip 110 includes 2 naked
Piece 120, therefore channel 160 is attached requiring 4 silvers between any between of chip 110.
It is emphasized that and be connected with each other between 2 bare dies 120 in asic chip 110 by channel 160 between 2 silvers,
Wherein channel 160 can be used as the spare interface channel between 2 bare dies 120 between 1 silver.
In the first embodiment of the present invention, bare die 120 is connected with full-mesh topology (full mesh topology) structure,
Channel 160 is directly connected to every other bare die 120 between i.e. each bare die 120 passes through piece.Bare die 120 further includes for operation
Task generates and the functional module of operational data insertion, and the serial parallel for calculating data insertion and calculated result output is logical
Road (SerDes) 180.Referring once again to Fig. 5, as shown in figure 5, in the first embodiment of the present invention, 72 calculating of network-on-chip
There are 64 calculate node 140-1 connection serial parallel channels 144, remaining 8 calculate node 140-1 linkage functions in node 140-1
Module.In Fig. 5, the functional node 140-2 that dark node on behalf is connected with functional module, light node on behalf and series-parallel
The calculate node 140-1 that channel is connected.
The invention proposes a kind of two-dimentional foldable circle face topological structures.One-dimensional foldable circle face topological structure is first introduced below,
So as to more be readily understood by the details of two-dimentional foldable circle face topological structure.Fig. 9 A, B are one-dimensional foldable circle face topological structures
Schematic diagram.As shown in Figure 9 A, there are the network-on-chips of an one-dimensional ring topology, and wherein most calculate node is with identical
The link channel of length be connected to they close to node, but the connection between fringe node then can only be by passing through all middle nodes
The link channel connection of point, so that the link channel length between its immediate node of not all calculate node is all equal, it will
Will lead to information transmitting may need additional buffering in particular directions and cause inconsistent delay, lead to the physics of bare die
Design and the forwarding strategy complexity of network-on-chip rise.The present invention uses a kind of topological structure of foldable circle face, such as Fig. 9 B institute
Show, so that calculate node forward and backward path interlocks in network-on-chip, although in this way, linkage length increases between node
Add, but then there are identical buffering and delay feature in different directions close to the link between node.
Figure 10 is the two-dimentional foldable circle face topological structure schematic diagram of first embodiment of the invention.As shown in Figure 10, Yu Benfa
Bright first embodiment hands over calculate node 140-1 forward and backward path in network-on-chip 130 using two-dimentional foldable circle face
It is wrong.After folding mode, calculate node logic and calculate node number change, and lead to the object of calculate node 140-1
Reason position changes.The link channel in topological structure in all directions of calculate node 140-1 is indicated with direction E, W, S, N
Port position, logically and physically layout between these it is inconsistent can by optionally link exchange selection signal, and
Any difference physically is not needed in node structure.Rotation right side half node is being partially disposed in link channel close to piece
In the node of upper network edge.Using exchanging mechanism identical with folding, this can be hidden from logical view and be physically rotated.It folds
The topological structure of anchor ring will lead to introduced between the physical structure of anchor ring and its logical construction it is inconsistent, for example, certain end of node
The logical direction of mouth is " E ", and the variation of position, but the logical direction of this corresponding port may occur after physical structure variation,
Still this port is referred to as " E ".The topological structure of two-dimentional foldable circle face through the invention, so that calculate node in network-on-chip
Front, rear, top, and bottom path interlocks, under the premise of ensuring that linkage length is not excessively increased between node, make different directions close to
Link buffering having the same and delay feature between node can simplify the physics realization and network-on-chip forwarding plan of bare die
Slightly.
Specifically, in the first embodiment of the present invention, the topological structure of network-on-chip 130 includes 6 × 12 calculating
Node 140-1, if node NoC address number is identified with columns m and line number n respectively, such as in line n the address node NoC according to
It is secondary be (0, n), (1, n), (2, n), (3, n), (4, n), (5, n), on m column the address node NoC be followed successively by (m, 0), (m,
1), (m, 2), (m, 3), (m, 4), (m, 5), (m, 6), (m, 7), (m, 8), (m, 9), (m, 10), (m, 11) carries out folding operation
Afterwards, the address node NoC becomes (0, n), (5, n), (1, n), (4, n), (2, n), (3, n), the node on m column in line n
The address NoC becomes (m, 0), (m, 11), (m, 1), (m, 10), (m, 2), (m, 9), (m, 3), (m, 8), (m, 4), (m, 7), (m
5)、(m,6)。
In addition, in network-on-chip 130 include linkage function module 8 functional node 140-2, each not with functional module
The calculate node 140-1 of connection has a functional node 140-2 to be used as close to node.Referring to Figure 10, such as Figure 10 institute
Show, using two-dimentional foldable circle face topological structure of the invention, the physical distribution of functional node 140-2 can be remained unchanged, and
Each calculate node 140-1 still has logical neighbors of the functional node 140-2 as connection.
Fig. 9 is a kind of structural schematic diagram of data processing plate based on ASIC array of second embodiment of the invention.Such as Fig. 9
It is shown, in the second embodiment of the present invention, a kind of data processing plate based on ASIC array is provided, which includes
ASIC array 100, controller unit (Controller) 210, power supply (Power) 220 and temperature management unit (thermal
Management), wherein temperature management unit includes temperature sensor (Sensors) 230, radiator 240.ASIC array 100
For receiving data that controller unit 210 transmits and carrying out hash calculating to it, after the result met the requirements, by it
Send controller unit 210 to；Controller unit 210 is connect with ASIC array 100 and temperature management unit respectively, for monitoring
The hash of ASIC array calculates, and is transferred to ASIC array after receiving external data, and exports the result of ASIC array acquisition；
Power supply 220 is used to DC input voitage being converted to operating voltage, and operating voltage is supplied to the ASIC battle array of data processing plate
Column 100, controller unit 210 and other modules；Temperature management unit can will pass through at the data that temperature sensor 230 obtains
The temperature information of reason plate is sent to controller unit 210, can also receive the instruction of controller unit 210, temperature management unit
Be sent to radiator 240 according to the instruction of controller unit 210, the fan governor of radiator 240 to start or close fan,
Or adjustment rotation speed of the fan, power work state can also be controlled in the case where not being related to system software, such as work as temperature sensing
Device 230 detects that data processing plate 200 controls when the temperature is excessively high and cuts off the power.In the second embodiment of the present invention, controller
Unit 210 can be using the Zynq ZU3CG field programmable gate array with 4GB RAM of operation (SuSE) Linux OS
FPGA。
It further include guidance unit, debugging unit and status lamp, wherein guidance unit is used in the second embodiment of the present invention
In controller unit starting guide, e.g. μ SD storage card or other have the storage medium of guiding function, the present invention is not
As limit；Debugging unit may have access to the serial console and JTAG of controller unit, for debugging to controller unit
And tuning parameter is provided, e.g. USB full-speed device etc., the present invention is not limited thereto；Status lamp be used for through color and/or
Brightness change shows the working condition of data processing plate, the elements such as e.g. LED.
ASIC array disclosed by the invention and the data processing plate for using ASIC array, for being hashed using e.g. SHA3
The hash of function calculates, and meets the big memory requirements of the workload verification algorithm Pow in ether mill.Figure 10 is that third of the present invention is implemented
The block excavating equipment structural schematic diagram of example.As shown in Figure 10, it in the third embodiment of the present invention, discloses a kind of for ether
The block excavating equipment 500 that mill block excavates, including at network communication module 400, task allocating module 300 and data above-mentioned
Plate 200 is managed, wherein network communication module 400 is for the data communication with ether mill, the e.g. equipment such as High_speed NIC；Task point
The ether mill block mining data for being used to will acquire with module 400 is distributed to data processing plate, and data processing plate is obtained
As a result ether mill is sent to by network communication module；Ether mill block excavating equipment 500 includes one or more data processings
Plate 200, the data that data processing plate 200 distributes task allocating module 400 are handled, to carry out block excavation.The present invention
The block excavating equipment 500 of 3rd embodiment further include power supply module, radiating module, cabinet etc., belong to block excavation applications
In common technique, therefore which is not described herein again.
Although the present invention is disclosed as above with embodiment, and is not intended to limit the invention, the skill of any the art
Art personnel can carry out equivalent modifications or change to it, be intended to be limited solely by the present invention in without departing from spirit and scope of the invention
Claims protection scope in.
Claims (11)
1. a kind of ASIC array, for carrying out block excavation, which is characterized in that the asic chip of the ASIC array is packaged with multiple
It is provided with the bare die of network-on-chip, which includes M × N number of calculate node, and the address NoC of the calculate node is (m, n),
The adjacent calculate node in the address NoC is connected with each other by piece upper channel, which uses two-dimentional folded coil topological structure,
Wherein the two dimension folded coil topological structure be the line n of the network-on-chip calculate node physical address be followed successively by (0, n),
(1, n) ..., (M-1, n) when, then the corresponding address NoC of the line n calculate node be followed successively by (0, n), (M-1, n), (2, n),
(M-2, n) ...,The physical address that the m of the network-on-chip arranges the calculate node be followed successively by (m, 0),
(m, 1) ..., (m, N-1) when, then m arrange the corresponding address NoC of the calculate node be followed successively by (m, 0), (m, N-1), (m, 1),
(m, N-2) ...,Wherein 0≤m≤M-1,0≤n≤N-1, M >=2, N >=2, and M, N, m, n are integer.
2. ASIC array as described in claim 1, which is characterized in that the network-on-chip includes 6 × 12 calculate nodes.
3. ASIC array as described in claim 1, which is characterized in that the asic chip includes 2 bare dies.
4. ASIC array as described in claim 1, which is characterized in that 4 × 4 ASIC are arranged in the one side of the PCB circuit board
4 × 4 asic chips are arranged in the another side of chip, the PCB circuit board.
5. a kind of block method for digging carries out block excavation using the described in any item ASIC arrays of such as Claims 1 to 4,
It is characterized in that, comprising:
Step 1, the random data set for being excavated to current block is obtained；
Step 2, which is divided into multiple subsets and carries out the calculate node that distribution is stored in the ASIC array；
Step 3, a certain random number arbitrarily chosen in the subset that a certain calculate node is saved carries out first round address arithmetic
To obtain destination address, with the destination address, according to the two dimension folded coil topological structure find the destination address to accrued
Operator node, and the input from the correspondence random number in the subset that the correspondence calculate node is saved as next round address arithmetic；
Using the random number obtained after the address arithmetic of default wheel number as target random number；
Step 4, it carries out hash to the target random number to calculate to obtain target value, if the target value is less than or equal to difficulty threshold
Value, then using the target random number as the block random number of current block, using the target value as the block hashed value of current block；Instead
Then abandon the target random number, and re-execute the steps 3；
Step 5, the current block is written into the block random number and the block hashed value, and the current block is broadcasted to block
Chain network.
6. block method for digging as claimed in claim 5, which is characterized in that further include:
Step 6, when verifier receives the current block of broadcast, the legitimacy of the current block is verified, and verifying is closed
The current block chain of method enters block chain.
7. block method for digging as claimed in claim 5, which is characterized in that the current block includes: current block head and works as
Proparea block, wherein deserving block hashed value, current block random number, the current block hash that proparea build includes previous block
Value and the difficulty threshold value.
8. a kind of data processing plate including the described in any item ASIC arrays of Claims 1 to 4 is excavated for block, special
Sign is, further includes: the controller unit being connect with the ASIC array, for monitoring the ASIC array processing, to the ASIC gusts
Column input data and the result for exporting ASIC array acquisition.
9. data processing plate as claimed in claim 8, which is characterized in that further include:
Temperature management unit, including radiator and temperature sensor, wherein the temperature sensor is for detecting the data processing plate
Temperature and be sent to the controller unit and/or the radiator, or control the working condition of the power supply；The radiator is for being
Data processing plate cooling；
Guidance unit is connect with the controller unit, for the starting guidance to the controller unit；
Debugging unit is connect with the controller unit, for being debugged to the controller unit and providing tuning parameter.
10. data processing plate as claimed in claim 8, which is characterized in that the controller unit is field programmable gate array.
11. a kind of block excavating equipment, including at least one is such as the described in any item data processing plates of claim 8~10, uses
It is excavated in block, which is characterized in that further include:
Network communication module, for connecting network to carry out data receiver and transmission；
Task allocating module, data distribution for will acquire from the network give the data processing plate, and by the data processing plate
Obtained result is sent to the network by the network communication module.
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| US9864582B2 (en) * | 2014-11-14 | 2018-01-09 | Cavium, Inc. | Code processor to build orthogonal execution blocks for programmable network devices |
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