CN103500240B - The method that silicon through hole is carried out Dynamic Programming wiring - Google Patents

Abstract

The present invention provides a kind of and silicon through hole is carried out Dynamic Programming layout method, carries out initialization including (1) and obtains initialization value, total including the silicon through hole needing layout, need the silicon through hole maximum number of layout, optimal objective in every layer；(2) determine whether the corresponding optimal solution of above-mentioned initialization value, if wherein there being corresponding optimal solution, entering step (3), if there is no corresponding optimal solution, entering step (4)；(3) directly quote described optimal solution, and be laid out wiring according to this optimal solution；(4) according to described optimal objective, demand characteristic is extracted；(5) demand characteristic and described initialization value are substituted into iterative equation, and the end of from solve optimal solution；(6) it is laid out wires design according to described optimal solution；(7) above-mentioned initialization value is stored with optimal solution.The present invention is by the optimal objective with the feature of different chip layout Wiring optimizations as Dynamic Programming, then by Dynamic Programming iteration, the end of from obtain optimal solution.

Description

The method that silicon through hole is carried out Dynamic Programming wiring

Technical field

The present invention relates to the location problem of silicon through hole, particularly relate to one and silicon through hole is carried out Dynamic Programming wiring Method.

Background technology

Along with the development of integrated circuit, integrated level is more and more higher, and technological level reduces increasingly, metal interconnecting wires Time delay and power consumption be continuously increased, had a strong impact on the development of integrated technology.In order to promote semiconductor industry Development, there has been proposed three-dimensionally integrated concept, this technology is to realize module list by silicon through hole technology Unit's interconnection communication in vertical direction.Highly shortened line based on silicon through hole three-dimensional integration technology, change The problems such as kind performance and reduction power consumption.The design of silicon through hole is mainly based on two dimensional topology connects up at present, adds Enter the necessary minimum feature of silicon via process, line-spacing data, use EDA(electronic design Automation) instrument automatically generates silicon via design scheme.

But how to carry out the design of silicon through hole, with farthest reduce ghost effect, power consumption, clock skew, Thermodynamics is uneven, a current or academic and difficult problem for industrial quarters.

Summary of the invention

The present invention is directed to this problem, it is provided that a kind of method that silicon through hole is carried out Dynamic Programming wiring.Including Following steps: (1) carries out initialization and obtains initialization value, total including the silicon through hole needing layout, every layer Middle need the silicon through hole maximum number of layout, optimal objective；(2) correspondence of above-mentioned initialization value is determined whether Optimal solution, if wherein there being corresponding optimal solution, entering step (3), if there is no corresponding optimal solution, entering step Suddenly (4)；(3) directly quote described optimal solution, and be laid out wiring according to this optimal solution；(4) basis Described optimal objective, extracts demand characteristic；(5) demand characteristic is substituted into iterative equation with described initialization value, And solve optimal solution on the end of from；(6) it is laid out wires design according to described optimal solution；(7) by upper State initialization value to store with optimal solution.

Preferably, described optimal objective, including shortest path, minimum density, minimum clock skew, Little thermodynamics is uneven, optimal reliability, or appoints the weighted sum of several.

Preferably, being laid out according to optimal solution described in step (3), (6), also include combining often The gate quantity arranged in Ceng and position.

The present invention also provides for one and silicon through hole is carried out Dynamic Programming layout method, comprises the steps: that (1) is entered Row initialization obtains initialization value, total including the silicon through hole needing layout, need in every layer the silicon of layout to lead to Hole maximum number, optimal objective, gate in every layer are arranged；(2) above-mentioned initialization value is determined whether Corresponding placement-and-routing, if wherein there being the placement-and-routing of correspondence, is then directly carried out according to corresponding placement-and-routing Arranging, if there is no the placement-and-routing of correspondence, then entering next step；(3) according to described optimal objective, extract Demand characteristic；(4) demand characteristic and described initialization value are substituted into iterative equation, and the end of from solve Optimal solution；(5) it is laid out wires design according to described optimal solution；(6) by above-mentioned initialization value and layout Wires design stores.

The method that silicon through hole is carried out Dynamic Programming wiring of the present invention, by excellent with different chip layout wirings The optimal objective that feature is Dynamic Programming changed, then by Dynamic Programming iteration, the end of from obtain Excellent solution.

Accompanying drawing explanation

Fig. 1 is the method flow diagram that silicon through hole carries out in the present invention Dynamic Programming wiring.

Fig. 2 is the exemplary plot of the placement-and-routing of 3 layers of stacked chips

Fig. 3 is the exemplary plot of shortest path routing mode in the present invention.

Fig. 4 is the exemplary plot of minimum density wire laying mode in the present invention.

Detailed description of the invention

As it is shown in figure 1, be the present invention silicon through hole (TSV, through silicon via) is dynamically advised Drawing the method flow diagram of wiring, its step is as follows:

In step S101, the optimal objective of silicon through hole is initialized.

Initialize and include defining that to need total number of plies of layout silicon through hole be num_layer, every layer needs layout The maximum number of silicon through hole is num_TSVi, and optimal objective is defined as two-dimensional array opt [] [], and array size is Num_layer*num_TSV, wherein total number of plies is known with every layer of silicon through hole maximum number, two dimension opt number Group and size thereof need to be replaced according to follow-up demand characteristic.

In step s 102, it is judged that whether above-mentioned initialization value has the optimal solution of correspondence.

In other embodiments, placement-and-routing's design of correspondence can directly be determined whether.Wherein, if Directly judge placement-and-routing, then in step S101, initialization value, also should include the logic on chip Door is arranged, including quantity and the position thereof of every layer of gate.

If there is no optimal solution or placement-and-routing's design of correspondence, then enter step S103, according to optimal objective, Extract its demand characteristic.

In the present invention, according to optimal objective, extract demand characteristic.Such as, shortest path, minimum density, Minimum clock skew, minimum thermal mechanical heterogeneity are, optimal reliability etc., or appoint the weighted sum of several.

Wherein, the target of optimal solution and the corresponding relation of demand characteristic are as shown in the table:

Optimal objective	Demand characteristic
		Shortest path	Minimum interconnection length
Minimum density	In unit are, silicon through hole number is minimum
		Minimum clock offsets	On Clock Tree, each layer path difference is minimum
Minimum thermal mechanical heterogeneity	Each path thermodynamic parameter difference is minimum
		Optimal reliability	Density Distribution is the most uniform, Temperature Distribution the most uniformly (difference is minimum the most everywhere)
Weighted sum	Appoint the weighted sum of several

In step S104, feature according to demand, in conjunction with needing the total number of plies of silicon through hole of layout, in every layer Need the silicon through hole maximum number of layout, substitute into recursion equation, and the end of from calculate optimal solution.

Wherein, recursion equation is as follows:

In step S105, according to described optimal solution, determine that optimal silicon via arrangements connects up.

Refer to Fig. 2, be the exemplary plot of the placement-and-routing of 3 layers of stacked chips, be provided with altogether 4 gate ports, 6 optional positions of TSV.

That is, initialize available: when needing silicon through hole number of plies num_layer-1=2 of layout, every layer needs The silicon through hole maximum number of layout is num_TSVi=3.

Refer to Fig. 3, as a example by shortest path routing, i.e. require minimum interconnection length.

I-th layer, jth interconnection length computing formula:

$\mathrm{dis}\left[i\right]\left[j\right]=\underset{j=1}{\overset{\mathrm{num}\_\mathrm{TSVi}}{\mathrm{\Σ}}}{x}_j-x_{j+1}$

The abscissa value of jth silicon through hole during wherein xj represents i-th layer.

Above-mentioned recursion equation is:

In like manner, as shown in Figure 4, for the exemplary plot of minimum density wire laying mode, silicon in unit are is i.e. required Through hole number is minimum, equilibrium with mechanics to realize heat radiation.

In step s 106, above-mentioned initialization value is stored with optimal solution.In another embodiment, Above-mentioned initial value is stored with placement-and-routing.The two is all directly to quote during planning next time for convenience.

If there is the optimal solution of correspondence when the judgement of step S102, then enters step S107, directly quote this Corresponding optimal solution；

In step S108, it is laid out wires design according to this optimal solution.

In another embodiment, if in step s 102, it is judged that result is that the placement-and-routing having correspondence sets Meter, the most directly quotes the design of this placement-and-routing.

Silicon via arrangements based on the dynamic programming wiring that the present invention proposes, has the following advantages: dynamic in application During state planning, for the subproblem (shortest path, minimum clock skew etc.) repeated, only need to be first Secondary solved when running into, and answer is saved, in order to directly quoted when running into the most again, it is not necessary to weight Newly solve, thus greatly improve computational efficiency.By contrast, other alternative manner such as divide and rule or Greedy algorithm, for certain subproblem, in spite of having solved, as long as meeting, will be again to it Solve, thus have impact on computational efficiency.

The present invention shows to adopt can significantly improve placement-and-routing's efficiency in this way through emulation, result.

The above is only the preferred embodiment of the present invention, it is noted that common for the art Technical staff, under the premise without departing from the principles of the invention, it is also possible to make some improvements and modifications, these Improvements and modifications also should be regarded as protection scope of the present invention.

Claims (4)

1. one kind carries out Dynamic Programming layout method to silicon through hole, it is characterised in that include as follows Step:

(1) carry out initialization and obtain initialization value, total including the silicon through hole needing layout, Every layer needs the silicon through hole maximum number of layout, optimal objective；

(2) the corresponding optimal solution of above-mentioned initialization value is determined whether, if wherein there being correspondence Optimal solution then enters step (3), if not having corresponding optimal solution, enters step (4)；

(3) directly quote described optimal solution, and be laid out wiring according to this optimal solution；

(4) according to described optimal objective, demand characteristic is extracted；

(5) feature according to demand, in conjunction with needing the total number of plies of silicon through hole of layout, needing in every layer Want the silicon through hole maximum number of layout, substitute into recursion equation, in the number of plies, first carry out loop iteration, Then loop iteration in each layer, thus the end of from calculate optimal solution；Wherein, recurrence Equation is as follows:

Opt [] []=0

For (int i=num_layer-1；I >=0；I--) { // * * loop iteration in the number of plies

For (int j=0；J≤num_TSVi-1；J++) { // * * loop iteration in each layer

Opt [i] [j]=Math.min (opt [i+1] [j], opt [i+1] [j+1])+opt [i] [j]；

// * * finds out the optimal solution in this layer

}

}

Wherein, initialize and include defining that to need total number of plies of layout silicon through hole be num_layer, often The maximum number needing layout silicon through hole in Ceng is num_TSVi, and optimal objective is defined as two-dimemsional number Group opt [] []；

(6) it is laid out wires design according to described optimal solution；

(7) above-mentioned initialization value is stored with optimal solution.

2. as claimed in claim 1 silicon through hole is carried out Dynamic Programming layout method, its feature Be, described optimal objective, including shortest path, minimum density, minimum clock skew, Minimum thermal mechanical heterogeneity, optimal reliability, or appoint the weighted sum of several.

3. as claimed in claim 1 silicon through hole is carried out Dynamic Programming layout method, its feature It is, being laid out according to optimal solution described in step (3), (6), also includes combining The gate quantity arranged in every layer and position.

4. one kind carries out Dynamic Programming layout method to silicon through hole, it is characterised in that include as follows Step:

(1) carry out initialization and obtain initialization value, total including the silicon through hole needing layout, Every layer need the silicon through hole maximum number of layout, optimal objective, gate in every layer arrange；

(2) determine whether the corresponding placement-and-routing of above-mentioned initialization value, if wherein have right The placement-and-routing answered, then be directly configured according to corresponding placement-and-routing, if not having correspondence Placement-and-routing, then enter next step；

(3) according to described optimal objective, demand characteristic is extracted；

(4) feature according to demand, in conjunction with needing the total number of plies of silicon through hole of layout, needing in every layer Want the silicon through hole maximum number of layout, substitute into recursion equation, in the number of plies, first carry out loop iteration, Then loop iteration in each layer, thus the end of from calculate optimal solution；Wherein, recurrence Equation is as follows:

Opt [] []=0

For (int i=num_layer-1；I >=0；I--) { // * * loop iteration in the number of plies

For (int j=0；J≤num_TSVi-1；J++) { // * * loop iteration in each layer

Opt [i] [j]=Math.min (opt [i+1] [j], opt [i+1] [j+1])+opt [i] [j]；

// * * finds out the optimal solution in this layer

}

}

Wherein, initialize and include defining that to need total number of plies of layout silicon through hole be num_layer, often The maximum number needing layout silicon through hole in Ceng is num_TSVi, and optimal objective is defined as two-dimemsional number Group opt [] []；

(5) it is laid out wires design according to described optimal solution；

(6) design of above-mentioned initialization value and placement-and-routing is stored.