CN110336963B - Dynamic image processing system and image processing method - Google Patents
Dynamic image processing system and image processing method Download PDFInfo
- Publication number
- CN110336963B CN110336963B CN201910491736.6A CN201910491736A CN110336963B CN 110336963 B CN110336963 B CN 110336963B CN 201910491736 A CN201910491736 A CN 201910491736A CN 110336963 B CN110336963 B CN 110336963B
- Authority
- CN
- China
- Prior art keywords
- module
- clock
- register
- configuration
- mode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
- H04N25/42—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by switching between different modes of operation using different resolutions or aspect ratios, e.g. switching between interlaced and non-interlaced mode
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/50—Control of the SSIS exposure
- H04N25/57—Control of the dynamic range
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
- H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
Abstract
The invention discloses a dynamic image processing system and an image processing method, which comprise an image sensor and an FPGA (field programmable gate array) which are mutually connected, wherein the image sensor comprises a register module and an image generation module, the image generation module is used for generating images, and M register modes are stored in the register module; the FPGA comprises a clock module, a configuration module and a receiving processing module, wherein the receiving processing module is used for receiving and processing the image sent by the image generating module, M clock modes are stored in the clock module, and M configuration modes are stored in the configuration module; the M register modes, the M clock modes and the M configuration modes are in one-to-one correspondence. According to the dynamic image processing system and the image processing method provided by the invention, the FPGA and the image sensor are dynamically configured, and the transmission frame rate of the image sensor and the processing rate of the FPGA are successively changed in a very short time under the action of the configuration module in the FPGA, so that the processing capacity of the FPGA on the image sensor is improved.
Description
Technical Field
The present invention relates to the field of image processing, and in particular, to a dynamic image processing system and an image processing method.
Background
With the development of image processing technology, image sensors are used more and more, and particularly in the industrial field, most of pure manual work is replaced by the step of machine vision; in the prior art, the image processing module generally adopts an FPGA to acquire and process an image, and the image processed by the FPGA is output through an interface (e.g., a USB interface, a CameraLink, a gigabit ethernet interface, etc.).
In the existing image processing system, an image sensor keeps a fixed output frame rate of an FPGA (field programmable gate array), namely the image sensor keeps a fixed frame rate and transmits images to the FPGA, and the FPGA keeps a fixed rate and processes received images; if the transmission frame rate needs to be changed during the transmission process, the following two methods are generally adopted for processing:
(1) the method comprises the steps that a DDR buffer is configured in the FPGA, when image processing is carried out, a client sends a frame request signal to control an image sensor to change the transmission frame rate of an image, then image data under the new transmission frame rate are buffered in the DDR buffer, and then the FPGA processes the image data in the DDR buffer. In the processing process, the transmission frame rate of the image sensor is changed, but the rate of receiving and processing the image by the FPGA is not changed, and even if the frame rate of transmitting the image by the image sensor is lowered, the processing rate of the FPGA is still high, so that the problems of high FPGA power consumption, poor system stability and the like are caused.
(2) And a crystal array for adjusting the clock is added outside the image sensor and is used for adjusting the working clock of the image sensor, then the crystal array and the FPGA are connected to a control center, and the working clock of the image sensor and the processing rate of the FPGA are respectively adjusted by the control center, so that the transmission rate and the processing rate of the image sensor and the FPGA are kept consistent. The system adopting the processing mode needs to additionally increase a crystal array and a control center, reduces the integration level of the whole processing system, has complicated control mode and reduces the image processing efficiency.
Disclosure of Invention
The invention aims to provide a dynamic image processing system and an image processing method, which can sequentially change the transmission frame rate of an image sensor and the processing rate of the FPGA in a very short time by dynamically configuring the FPGA and the image sensor and acting a configuration module in the FPGA, thereby improving the processing capacity of the FPGA on the image sensor.
In order to achieve the purpose, the invention adopts the following technical scheme: a dynamic image processing system comprises an image sensor and an FPGA which are connected with each other, wherein the image sensor comprises a register module and an image generation module, the image generation module is used for generating images, and M register modes are stored in the register module;
the FPGA comprises a clock module, a configuration module and a receiving processing module, wherein the receiving processing module is used for receiving and processing the image sent by the image generation module, the register module and the clock module are both connected with the configuration module, M clock modes are stored in the clock module, and M configuration modes are stored in the configuration module; the M register modes, the M clock modes and the M configuration modes are in one-to-one correspondence; wherein M is an integer greater than or equal to 2;
the configuration module in the FPGA selects one of M configuration modes, and transmits the configuration mode to the register module and the clock module in sequence, so that the register module and the clock module select the corresponding register mode and clock mode in sequence; and the register module and the clock module transmit the corresponding register mode and clock mode to the image generation module, so that the image generation module performs image transmission according to the corresponding clock mode.
Further, the system further includes a processing end, and the processing end is connected to the configuration module and is configured to trigger the configuration module to select one of the M configuration modes.
Further, the configuration module is connected with the register module through an SPI interface.
Further, the image generation module and the receiving processing module are connected through a transmission interface, and the transmission interface comprises a data transmission interface, a row selection interface and a column selection interface.
The invention provides an image processing method, which comprises the following steps:
s01: the configuration module in the FPGA selects one of the M configuration modes, and transmits the configuration mode to the register module and the clock module in sequence, so that the register module and the clock module select the corresponding register mode and clock mode in sequence; the FPGA comprises a clock module, a configuration module and a receiving and processing module, and the image sensor comprises a register module and an image generation module;
s02: the register module and the clock module transmit the corresponding register mode and the clock mode to the image generation module, so that the image generation module transmits images according to the selected clock mode.
Further, the configuration module is connected to a processing end, and in step S01, the processing end triggers the configuration module to select one of the M configuration modes.
Further, the processing terminal is a PC terminal.
Further, in step S01, the configuration module sends an SPI signal to the register module, and controls the register module to select a corresponding register mode.
Further, in step S02, the image generating module sends an image to the receiving processing module through a transmission interface, where the transmission interface includes a data transmission interface, a row selection interface, and a column selection interface.
The invention has the beneficial effects that: according to the invention, the configuration module and the clock module are arranged in the FPGA, the register module is arranged in the image sensor, the configuration modes stored in the configuration module, the clock modes stored in the clock module and the register modes stored in the register module are in one-to-one correspondence, and the register module and the clock module are controlled by the configuration module to successively select the corresponding modes, so that the transmission frame rate of the image sensor and the processing rate of the FPGA are successively changed in a very short time, and the processing capacity of the FPGA on the image sensor is improved; the image processing system can change the transmission frame rate of the image sensor and the processing rate of the FPGA in real time and keep the rates of the image sensor and the FPGA consistent, and the FPGA only comprises the clock module, the configuration module and the receiving processing module, so that the problem that a DDR buffer or a crystal array needs to be added in the prior art is solved, the structure of the whole processing system is simplified, and the real-time effectiveness of data processing can be ensured.
Drawings
Fig. 1 is a schematic structural diagram of a dynamic image processing system according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings.
As shown in fig. 1, the dynamic image processing system provided by the present invention includes an image sensor and an FPGA connected to each other, the image sensor includes a register module and an image generation module, the image generation module is used for generating an image, and the register module stores M register modes. The image sensor may specifically adopt an ISA8201 chip.
The FPGA comprises a clock module, a configuration module and a receiving processing module, wherein the receiving processing module is used for receiving and processing the image sent by the image generating module, the register module and the clock module are both connected with the configuration module, M clock modes are stored in the clock module, and M configuration modes are stored in the configuration module; the M register modes, the M clock modes and the M configuration modes are in one-to-one correspondence; wherein M is an integer of 2 or more. For example, if the clock module is configured with four clock modes, i.e., 10M, 20M, 30M and 40M, the configuration module and the register module each include four configuration modes and four register modes corresponding to the four clock modes, where the 10M clock mode represents a transmission rate of 10 mega per second.
As shown in fig. 1, the specific connection relationship is as follows: the configuration module in the FPGA is connected with a register module in the image sensor and a clock module in the FPGA, the register module and the clock module are both connected with an image generation module in the image sensor, and the image generation module is connected with a receiving and processing module in the FPGA; preferably, the configuration module is connected with the register module through an SPI interface; preferably, the image generating module and the receiving processing module are connected through a transmission interface, and the transmission interface includes a data transmission interface, a row selection interface and a column selection interface. The system further comprises a processing end, wherein the processing end is connected with the configuration module in the FPGA and used for triggering the configuration mode of the configuration module, so that the change of the transmission frame rate of the image sensor and the processing rate of the FPGA is caused, and the specific processing end can be a PC and the like.
When the system starts to process images, the configuration module in the FPGA selects one of M configuration modes, and transmits the selected configuration mode to the register module and the clock module in sequence, so that the register module and the clock module select the corresponding register mode and clock mode in sequence; the register module transmits the selected register mode to the image generation module, and then the clock module transmits the selected clock mode to the image generation module, so that the image generation module performs image transmission according to the selected clock mode.
When the transmission rate of the image sensor to the FPGA needs to be changed, the configuration module in the FPGA is switched to another configuration mode in the M configuration mode, and the switched configuration modes are sequentially transmitted to the register module and the clock module, so that the register module and the clock module are sequentially switched to the corresponding register mode and the clock mode; the register module and the clock module are connected to the image generation module and transmit the switched register mode and clock mode to the image generation module, so that the image generation module performs image transmission according to the switched clock mode.
It is worth to be noted that, after the configuration module in the FPGA switches the configuration mode, because the configuration module is connected with the clock module and the register module, but the time of the configuration module acting on the clock module and the register module has a sequence, the invention ensures that the selected or switched configuration module acts on the register module first, namely that the configuration module configures the image sensor first and then configures the FPGA; this is because: firstly adjusting the transmission rate of the image sensor and then adjusting the processing rate of the FPGA can ensure that the adjustment process is carried out stably, and if the processing rate of the FPGA is firstly adjusted and then the transmission rate of the image sensor is adjusted, system disorder can be caused. Specifically, the sequential action of the configuration module on the register module and the clock module can be completed in the following manner: the configuration module selects one configuration mode from M configuration modes, firstly transmits the configuration mode to the register module, so that the register module selects the corresponding register mode, and then transmits the configuration mode to the clock module, so that the clock module selects the corresponding clock mode.
The invention provides an image processing method, which comprises the following steps:
s01: when the system starts to process images, a processing end triggers a configuration module in an FPGA to select one configuration mode (a first configuration mode) from M configuration modes, and the selected configuration mode is sequentially transmitted to a register module and a clock module, so that the register module and the clock module sequentially select the corresponding register mode (the first register mode) and the clock mode (the first clock mode); specifically, the configuration module sends an SPI signal to the register module to control the register module to select the corresponding register mode. Wherein, the processing end can be a PC end.
S02: the register module and the clock module are both connected to the image generation module, and transmit the register mode (first register mode) and the clock mode (first clock mode) after selection to the image generation module, so that the image generation module performs image transmission according to the selected clock mode (first clock mode). Specifically, the image generation module sends the image to the receiving processing module through a transmission interface, wherein the transmission interface includes a data transmission interface, a row selection interface and a column selection interface.
S03: when the transmission rate of the image sensor to the FPGA needs to be changed, the processing end triggers the configuration module in the FPGA to switch another configuration mode (a second configuration mode) in the M configuration modes, and the switched configuration modes are sequentially transmitted to the register module and the clock module, so that the register module and the clock module sequentially switch the corresponding register mode (the second register mode) and the clock mode (the second clock mode); specifically, the configuration module sends an SPI signal to the register module to control the register module to switch the corresponding register mode.
S04: the register module and the clock module are both connected to the image generation module, and transmit the register mode (second register mode) and the clock mode (second clock mode) after switching to the image generation module, so that the image generation module performs image transmission according to the clock mode (second clock mode) after switching. Specifically, the image generation module sends the image to the receiving processing module through a transmission interface, wherein the transmission interface includes a data transmission interface, a row selection interface and a column selection interface.
The first clock mode, the first register mode and the first configuration mode are corresponding modes, and the second clock mode, the second register mode and the second configuration mode are corresponding modes and only named, and those skilled in the art can name the corresponding modes at any time.
According to the invention, the configuration module and the clock module are arranged in the FPGA, the register module is arranged in the image sensor, the configuration modes stored in the configuration module, the clock modes stored in the clock module and the register modes stored in the register module are in one-to-one correspondence, and the register module and the clock module are controlled by the configuration module to successively select the corresponding modes, so that the transmission frame rate of the image sensor and the processing rate of the FPGA are successively changed in a very short time, and the processing capacity of the FPGA on the image sensor is improved; the image processing system can change the transmission frame rate of the image sensor and the processing rate of the FPGA in real time and keep the rates of the image sensor and the FPGA consistent, and the FPGA only comprises the clock module, the configuration module and the receiving processing module, so that the problem that a DDR buffer or a crystal array needs to be added in the prior art is solved, the structure of the whole processing system is simplified, and the real-time effectiveness of data processing can be ensured.
The above description is only a preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the appended claims.
Claims (9)
1. A dynamic image processing system is characterized by comprising an image sensor and an FPGA which are connected with each other, wherein the image sensor comprises a register module and an image generation module, the image generation module is used for generating images, and M register modes are stored in the register module;
the FPGA comprises a clock module, a configuration module and a receiving processing module, wherein the receiving processing module is connected with the image generation module and is used for receiving and processing the image sent by the image generation module, the register module and the clock module are both connected with the configuration module, M clock modes are stored in the clock module, and M configuration modes are stored in the configuration module; the M register modes, the M clock modes and the M configuration modes are in one-to-one correspondence; wherein M is an integer greater than or equal to 2;
the configuration module in the FPGA selects one of M configuration modes, and transmits the configuration mode to the register module and the clock module in sequence, so that the register module and the clock module select the corresponding register mode and clock mode in sequence; the register module and the clock module transmit the corresponding register mode and the clock mode to the image generation module, so that the image generation module performs image transmission according to the corresponding clock mode; when the transmission rate of the image sensor to the FPGA and the processing rate of the FPGA need to be changed, the configuration module in the FPGA is switched to another configuration mode in the M configuration mode, and the switched configuration modes are sequentially transmitted to the register module and the clock module, so that the register module and the clock module are sequentially switched to the corresponding register mode and the corresponding clock mode.
2. The system according to claim 1, further comprising a processing terminal connected to said configuration module for triggering said configuration module to select one of M configuration modes.
3. The dynamic image processing system according to claim 1, wherein said configuration module is connected to said register module via an SPI interface.
4. The dynamic image processing system according to claim 1, wherein the image generating module and the receiving processing module are connected via a transmission interface, and the transmission interface comprises a data transmission interface, a row selection interface and a column selection interface.
5. An image processing method, characterized by comprising the steps of:
s01: the configuration module in the FPGA selects one of M configuration modes, and transmits the configuration mode to the register module and the clock module in sequence, so that the register module and the clock module select the corresponding register mode and clock mode in sequence; the FPGA comprises a clock module, a configuration module and a receiving and processing module, and the image sensor comprises a register module and an image generation module;
s02: the register module and the clock module transmit the corresponding register mode and the clock mode to the image generation module, so that the image generation module performs image transmission according to the selected clock mode;
s03: when the transmission rate of the image sensor to the FPGA needs to be changed, the processing end triggers the configuration module in the FPGA to switch another configuration mode among the M configuration modes, and transmits the switched configuration modes to the register module and the clock module in sequence, so that the register module and the clock module switch the corresponding register mode and the clock mode in sequence;
s04: the register module and the clock module are connected to the image generation module and transmit the switched register mode and clock mode to the image generation module, so that the image generation module transmits images according to the switched clock mode.
6. The image processing method according to claim 5, wherein said configuration module is connected to a processing terminal, and said processing terminal triggers said configuration module to select one of M configuration modes in said step S01.
7. The image processing method according to claim 6, wherein the processing side is a PC side.
8. The image processing method according to claim 5, wherein said configuration module sends an SPI signal to said register module in said step S01, controlling it to select a corresponding register mode.
9. The image processing method according to claim 5, wherein the image generating module sends the image to the receiving processing module through a transmission interface in step S02, wherein the transmission interface comprises a data transmission interface, a row selection interface and a column selection interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910491736.6A CN110336963B (en) | 2019-06-06 | 2019-06-06 | Dynamic image processing system and image processing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910491736.6A CN110336963B (en) | 2019-06-06 | 2019-06-06 | Dynamic image processing system and image processing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110336963A CN110336963A (en) | 2019-10-15 |
| CN110336963B true CN110336963B (en) | 2022-03-29 |
Family
ID=68140921
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910491736.6A Active CN110336963B (en) | 2019-06-06 | 2019-06-06 | Dynamic image processing system and image processing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110336963B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113163113B (en) * | 2021-03-29 | 2022-06-07 | 广州安凯微电子股份有限公司 | Image sensor frame rate and exposure control system and method |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6947070B2 (en) * | 2001-05-21 | 2005-09-20 | Pentax Corporation | Video scope utilized in electronic endoscope system |
| US8624999B2 (en) * | 2009-12-01 | 2014-01-07 | Ricoh Company, Ltd. | Imaging apparatus |
| CN102055894A (en) * | 2010-11-23 | 2011-05-11 | 无锡市博阳精密机械制造有限公司 | Modularized CCD industrial camera |
| CN102665049B (en) * | 2012-03-29 | 2014-09-17 | 中国科学院半导体研究所 | Programmable visual chip-based visual image processing system |
| CN104427232B (en) * | 2013-08-30 | 2017-11-24 | 安凯(广州)微电子技术有限公司 | A kind of method, apparatus and system for realizing IMAQ |
| CN103647901B (en) * | 2013-12-24 | 2017-06-20 | 中国科学院半导体研究所 | The inexpensive image data acquiring Transmission system without external memory based on FPGA |
| US9219870B1 (en) * | 2014-07-31 | 2015-12-22 | Apple Inc. | Sensor data rescaler for image signal processing |
| CN206195934U (en) * | 2016-11-08 | 2017-05-24 | 中国科学院西安光学精密机械研究所 | High -speed CMOS camera imaging system |
-
2019
- 2019-06-06 CN CN201910491736.6A patent/CN110336963B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN110336963A (en) | 2019-10-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109830204A (en) | A kind of sequence controller, display driving method, display device | |
| CN110336963B (en) | Dynamic image processing system and image processing method | |
| CN107733546B (en) | Time information synchronization system and method | |
| CN103065587A (en) | Transmitting-card-free low-cost light emitting diode (LED) synchronous display controlling system | |
| US20240087500A1 (en) | Led driving circuit, led display system and display control method | |
| CN102625086B (en) | DDR2 (Double Data Rate 2) storage method and system for high-definition digital matrix | |
| CN102641598A (en) | Toy control method, remote controller and system | |
| US20190088192A1 (en) | Display device and driving method thereof | |
| CN102821257A (en) | Imaging apparatus and imaging system | |
| CN203910232U (en) | Gray scale display control device for field emission display | |
| CN111212285A (en) | Hardware video coding system and control method of hardware video coding system | |
| CN204577065U (en) | The device of MIPI Signal transmissions adjustment is realized based on FPGA | |
| CN102854624A (en) | Stereoscopic glasses and operation method thereof | |
| CN116155843B (en) | PYNQ-based pulse neural network chip data communication method and system | |
| CN102857230B (en) | High-speed program controller on basis of lossless compression data transmission technology | |
| CN202362765U (en) | Picture signal source generating device with format changeable | |
| CN111739455A (en) | Device and method for converting self-adaptive arbitrary frame frequency digital video signal and VGA (video graphics array) | |
| CN105376550A (en) | Image synchronizing method and system | |
| CN100397885C (en) | Image data processing device | |
| CN114826821B (en) | Communication method and system | |
| CN202495967U (en) | Data acquisition system | |
| CN109656199B (en) | Servo control method based on clock excitation feedback quantity synchronous processing | |
| CN116074481A (en) | Data transmission system for online configuration of communication link, transmission box and LED display screen | |
| CN108627251B (en) | Active radiation infrared scene conversion system | |
| CN112558126B (en) | Method and related device for adaptively adjusting transmitting power of RTK reference station |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |