CN110335828A - A kind of chip packaging method and encapsulating structure increasing redistributing layer binding force - Google Patents
A kind of chip packaging method and encapsulating structure increasing redistributing layer binding force Download PDFInfo
- Publication number
- CN110335828A CN110335828A CN201910456224.6A CN201910456224A CN110335828A CN 110335828 A CN110335828 A CN 110335828A CN 201910456224 A CN201910456224 A CN 201910456224A CN 110335828 A CN110335828 A CN 110335828A
- Authority
- CN
- China
- Prior art keywords
- layer
- redistributing
- binding force
- opening
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02373—Layout of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02381—Side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/111—Manufacture and pre-treatment of the bump connector preform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13008—Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
- H01L2224/13018—Shape in side view comprising protrusions or indentations
- H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention discloses a kind of chip packaging methods for increasing redistributing layer binding force, baking processing is carried out by the surface to redistributing layer, increase the roughness on redistributing layer surface, enhance binding force of the redistributing layer in subsequent encapsulation procedure, tolerance is stronger in reliability test, meets the stress demand of chip；In addition, due to the passivation layer answered force request, can save under redistributing layer in the prior art for meeting chip after the coarse processing of redistributing layer, relative simplicity packaging technology process has saved production cost.The invention also discloses the encapsulating structures that the chip packaging method using the increase redistributing layer binding force is formed.The present invention compared with the existing technology, has the advantages that packaging technology is simple, packaging cost is low and high reliablity, and chip tolerance in reliability test is stronger after encapsulation, has excellent performance, is suitable for all kinds of electronic component products.
Description
Technical field
The present invention relates to the manufacturing technology field of semiconductor more particularly to a kind of chip envelopes for increasing redistributing layer binding force
Dress method and encapsulating structure.
Background technique
The major function of chip package includes: to provide mechanical support and environmental protection for semiconductor chip, and it is steady to provide chip
Fixed reliable working environment；The electric appliance for providing semiconductor chip and external system connects, including power supply and signal；Signal is provided
Output and input access；Thermal energy access is provided, guarantees chip proper heat reduction.Chip package directly affects integrated circuit and device
Electricity, heat, light and mechanical performance, have an effect on its reliability and manufacturing cost.
As semiconductor variable must become increasingly complex, small size, lightening, high pin, high speed and low cost are encapsulation
The major driving factor of technology development.Traditional encapsulation technology, such as leadframe package, flexible package, rigid encapsulation technology, no
These demands are able to satisfy, wafer stage chip encapsulation technology is come into being.Wafer stage chip encapsulation technology is carried out to full wafer wafer
It cuts to obtain the technology of single finished product chip again after packaging and testing, the chip size after encapsulation is consistent with bare die.Wafer stage chip
Scale packaging techniques change the mode of conventional package, have complied with market increasingly light to microelectronic product, small, short, thinning and low price
Change and requires.Chip size after the encapsulation of crystal wafer chip dimension encapsulation technology has reached and has been highly miniaturized, chip cost with
The reduction of chip size and the increase of wafer size and significantly reduce.Crystal wafer chip dimension encapsulation technology is can to set IC
Meter, wafer manufacture, packaging and testing, substrate manufacture the technology integrated, are hot spot and the future development in current encapsulation field
Trend.
In the chip surface of wafer packaging structure, redistribution technology is mostly used to rearrange I/O pad greatly, then again
Salient point is prepared on the solder joint of distribution, the interconnection between circuit is realized with this.Using redistribution technology, the weld pad of chip center can be weighed
It is newly distributed to the periphery, two sides or unilateral side of chip, by this variation, designer can consider to encapsulate chip more flexiblely
Modes of emplacement, such as stacked vertical, intersecting, side by side stacking etc. modes arrange.Redistribution encapsulation in the prior art
Process flow is relatively cumbersome, at high cost, under the environment of existing market product competition fierceness, it is necessary to develop high-performance, Gao Ke
By the chip of property and lower cost, to improve the market competitiveness.
Summary of the invention
The purpose of the present invention is to provide a kind of chip packaging method and encapsulating structures, to overcome core in the prior art
The technical problem that piece packaging technology process is relatively cumbersome, higher cost and performance are bad.
A kind of chip packaging method increasing redistributing layer binding force, comprising the following steps:
The wafer that surface has the first passivation layer is provided, the wafer is equipped with weld pad, opens up on first passivation layer
There is the first opening exposed for the weld pad；
The first metal layer is formed in first opening；
Redistributing layer is formed on the first metal layer and first passivation layer, and to the surface of the redistributing layer
It is toasted, so that the surface roughening of the redistributing layer；
The second passivation layer is formed on the surface of the redistributing layer, forms the second opening on second passivation layer, it is described
Second opening, which exposes, needs turning part；
Second metal layer is formed in second opening；
The salient point with weld pad electrical contact is formed in the second metal layer.
Further, baking temperature is 100~200 DEG C, 10~30min of baking time.
Further, the redistributing layer is formed by electrochemical deposition method, and the first metal layer passes through electrochemistry
The mode that deposition perhaps sputters forms the second metal layer and is formed by way of electrochemical deposition or sputtering.
Further, second passivation layer is formed by coating method；Second opening passes through laser ablation or wet
The mode of method corrosion is formed.
Further, the salient point is formed by depositing or planting ball mode；The ingredient of the salient point is single metal or gold
Belong to alloy.
Further, it is formed in the second metal layer before the salient point being in electrical contact with the weld pad, further includes: production
Ball lower metal layer；The ball lower metal layer is formed by way of electrochemical deposition or sputtering.
Correspondingly, the present invention provides a kind of chip-packaging structure, including insulating layer, conductive layer, salient point, redistributing layer and tool
There is the wafer of weld pad；The insulating layer includes the first passivation layer and the second passivation layer, and first passivation layer is set to the wafer
Surface, first passivation layer have first opening, it is described first opening exposes the weld pad；The redistributing layer is formed
Between first passivation layer and second passivation layer, for redistributing the weld pad, the redistributing layer has thick
Roughened surface；Second passivation layer has the second opening, and second opening, which exposes, needs turning part；The conductive layer
It is electrically connected with the weld pad, the conductive layer includes the first metal layer and second metal layer, and the first metal layer is formed in institute
It states in the first opening, the second metal layer is formed in second opening；The salient point is formed in the second metal layer
On, the salient point is electrically connected with the weld pad.
Further, the roughened surface of the redistributing layer is formed by roasting mode.
Further, baking temperature is 100~200 DEG C, 10~30min of baking time.
Further, the roughened surface of the redistributing layer is formed by plasma etching mode.
The invention has the following beneficial effects:
The chip packaging method and encapsulating structure of increase redistributing layer binding force of the invention, pass through the table to redistributing layer
Face carries out baking processing, increases the roughness on redistributing layer surface, enhances knot of the redistributing layer in subsequent encapsulation procedure
With joint efforts, tolerance is stronger in reliability test, meets the stress demand of chip；In addition, in the prior art under redistributing layer
Stress is buffered equipped with passivation layer, since meet chip after the coarse processing of redistributing layer answers force request, can be saved existing
Passivation layer in technology under redistributing layer, relative simplicity process flow, has saved packaging cost.Increase redistribution of the invention
The chip packaging method and structure of layer binding force, have the advantages that simple process, at low cost and high reliablity, chip exists after encapsulation
Tolerance is stronger in reliability test, has excellent performance, and is suitable for all kinds of electronic component products.
Detailed description of the invention
It in order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology and advantage, below will be to implementation
Example or attached drawing needed to be used in the description of the prior art are briefly described, it should be apparent that, the accompanying drawings in the following description is only
It is only some embodiments of the present invention, for those of ordinary skill in the art, without creative efforts,
It can also be obtained according to these attached drawings other attached drawings.
Fig. 1 is the flow diagram of chip packaging method of the invention；
Fig. 2-8 is the diagrammatic cross-section that process is packaged according to Fig. 1；
Fig. 9 be embodiment 1 the coarse processing of redistributing layer before 50 times of microscope photo of amplification；
Figure 10 be embodiment 1 the coarse processing of redistributing layer after 50 times of microscope photo of amplification；
Figure 11 be embodiment 1 the coarse processing of redistributing layer before 100 times of microscope photo of amplification；
Figure 12 be embodiment 1 the coarse processing of redistributing layer after 100 times of microscope photo of amplification；
Wherein, appended drawing reference is corresponding in figure are as follows: 1- wafer, 2- weld pad, the first passivation layer of 3-, 4- the first metal layer, 5- are again
Distribution layer, the second passivation layer of 6-, 7- second metal layer, 8- ball lower metal layer, 9- salient point.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with embodiment to the present invention make into
One step it is described in detail.Obviously, described embodiments are only a part of the embodiments of the present invention, rather than whole implementation
Example.Based on the embodiments of the present invention, those of ordinary skill in the art are obtained without creative labor
Every other embodiment, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that, term " first ", " second ", " third " etc. are for distinguishing class
As object, without being used to describe a particular order or precedence order.It should be understood that the data used in this way are in appropriate situation
Under can be interchanged, so that the embodiment of the present invention described herein can be other than those of illustrating or describing herein
Sequence is implemented.
In the present invention unless specifically defined or limited otherwise, the terms such as term " connected ", " connection " should do broad sense reason
Solution, for example, it may be being fixedly connected, may be a detachable connection, or integral；It can be mechanical connection, be also possible to electricity
Connection；It can be directly connected, being connected inside two elements or two can also be can be indirectly connected through an intermediary
The interaction relationship of element.For the ordinary skill in the art, above-mentioned term can be understood as the case may be
Concrete meaning in the present invention.
Refering to fig. 1-8, the present invention provides a kind of chip packaging methods for increasing redistributing layer binding force, including following step
It is rapid:
The wafer 1 that surface has the first passivation layer 3 is provided, wafer 1 is equipped with weld pad 2, offers confession on the first passivation layer 3
The first opening that weld pad 2 exposes；
The first metal layer 4 is formed in the first opening；
Redistributing layer 5 is formed on the first metal layer 4 and the first passivation layer 3, and the surface of redistributing layer 5 is dried
It is roasting, so that the surface roughening of redistributing layer 5；
The second passivation layer 6 is formed on the surface of redistributing layer 5, forms the second opening on the second passivation layer 6, the second opening is sudden and violent
Exposing needs turning part；
Second metal layer 7 is formed in the second opening；
The salient point 9 being in electrical contact with weld pad 2 is formed in second metal layer 7.
In order to further illustrate the present invention, increase redistributing layer provided by the invention is combined below in conjunction with specific embodiment
The chip packaging method and encapsulating structure of power are described in detail.
Embodiment 1
Present embodiments provide a kind of chip packaging method for increasing redistributing layer binding force, comprising the following steps:
The wafer 1 that surface has the first passivation layer 3 is provided, wafer 1 is equipped with weld pad 2, offers confession on the first passivation layer 3
The first opening that weld pad 2 exposes；
The first metal layer 4 is formed by way of one layer of metal of electrochemical deposition in the first opening；
Redistributing layer 5 is formed by way of electrochemical deposition on the first metal layer 4 and the first passivation layer 3, and to again
Distribution layer 5 is toasted, and baking temperature is 150 DEG C, baking time 20min；
Second by way of laser ablation after the second passivation layer 6 of the surface of redistributing layer 5 coating, exposure development
The second opening is formed on passivation layer 6, the second opening, which exposes, needs turning part；
The mode of one layer of metal of electrochemical deposition forms second metal layer 7 in being open second；
The salient point 9 being in electrical contact with weld pad 2 is formed by depositional mode in second metal layer 7, the ingredient of salient point 9 is single
Metal.
In the present embodiment, coarse processing is carried out to redistributing layer 5 by roasting mode, there is roughening effect well.
The parametric synthesis such as binding force size, process costs according to needed for follow-up process of the temperature and time of baking consider, to be expired
The surface roughness of the redistributing layer 5 of sufficient condition.
Embodiment 2
The chip packaging method provided in this embodiment for increasing redistributing layer binding force, on the basis of the above embodiments,
Optionally, the first metal layer 4 is formed by way of electrochemical deposition multiple layer metal in the first opening, using this method, work
Skill is relatively easy, and the ingredient and thickness of the film deposited are easy to control, and has preferable uniformity.Multiple layer metal is met
The requirement of higher chip density.
Embodiment 3
The chip packaging method provided in this embodiment for increasing redistributing layer binding force, on the basis of the above embodiments,
Optionally, the first metal layer 4 is formed by way of sputtering one layer of metal in the first opening.
Embodiment 4
The chip packaging method provided in this embodiment for increasing redistributing layer binding force, on the basis of the above embodiments,
Optionally, the first metal layer 4 is formed by way of sputtering multiple layer metal in the first opening.
Embodiment 5
The chip packaging method provided in this embodiment for increasing redistributing layer binding force, on the basis of the above embodiments,
Optionally, baking temperature is 125 DEG C, baking time 25min.
Embodiment 6
The chip packaging method provided in this embodiment for increasing redistributing layer binding force, on the basis of the above embodiments,
Optionally, baking temperature is 100 DEG C, baking time 30min.
Embodiment 7
The chip packaging method provided in this embodiment for increasing redistributing layer binding force, on the basis of the above embodiments,
Optionally, baking temperature is 175 DEG C, baking time 15min.
Embodiment 8
The chip packaging method provided in this embodiment for increasing redistributing layer binding force, on the basis of the above embodiments,
Optionally, baking temperature is 200 DEG C, baking time 10min.
Embodiment 9
The chip packaging method provided in this embodiment for increasing redistributing layer binding force, on the basis of the above embodiments,
Optionally, baking temperature is 125 DEG C, baking time 30min.
Embodiment 10
The chip packaging method provided in this embodiment for increasing redistributing layer binding force, on the basis of the above embodiments,
Optionally, baking temperature is 175 DEG C, baking time 10min.
Embodiment 11
The chip packaging method provided in this embodiment for increasing redistributing layer binding force, on the basis of the above embodiments,
Optionally, roughened surface is formed by plasma etching to redistributing layer 5.
Embodiment 12
The chip packaging method provided in this embodiment for increasing redistributing layer binding force, on the basis of the above embodiments,
Optionally, the second opening is formed by way of wet etching on the second passivation layer 6.
Embodiment 13
The chip packaging method provided in this embodiment for increasing redistributing layer binding force, on the basis of the above embodiments,
Optionally, the mode of electrochemical deposition multiple layer metal forms second metal layer 7 in being open second.
Embodiment 14
The chip packaging method provided in this embodiment for increasing redistributing layer binding force, on the basis of the above embodiments,
Optionally, the mode of one layer of metal of sputtering forms second metal layer 7 in the second opening.
Embodiment 15
The chip packaging method provided in this embodiment for increasing redistributing layer binding force, on the basis of the above embodiments,
Optionally, the mode of sputtering multiple layer metal forms second metal layer 7 in the second opening.
Embodiment 16
The chip packaging method provided in this embodiment for increasing redistributing layer binding force, on the basis of the above embodiments,
Optionally, the salient point 9 being in electrical contact with weld pad 2 is formed by depositional mode in second metal layer 7, the ingredient of salient point 9 is metal
Alloy.
Embodiment 17
The chip packaging method provided in this embodiment for increasing redistributing layer binding force, on the basis of the above embodiments,
Optionally, the salient point 9 being in electrical contact with weld pad 2 is formed by planting ball mode in second metal layer 7, the ingredient of salient point 9 is single
Metal.
Embodiment 18
The chip packaging method provided in this embodiment for increasing redistributing layer binding force, on the basis of the above embodiments,
Optionally, the salient point 9 being in electrical contact with weld pad 2 is formed by planting ball mode in second metal layer 7, the ingredient of salient point 9 is metal
Alloy.
Embodiment 19
The packaging method of chip provided in this embodiment, on the basis of the above embodiments, further, in the second metal
It is formed on layer 7 before the salient point 9 being in electrical contact with weld pad 2, further includes production ball lower metal layer 8, ball lower metal layer 8 passes through electrochemistry
Deposition or the mode of sputtering are formed, and to guarantee well contacting for salient point 9 and weld pad 2, guarantee the signal stabilization and reliably of chip
Property.
In order to further verify beneficial effects of the present invention, toasted with the redistributing layer 5 in micro- sem observation embodiment 1
Surface before and after the processing, refering to Fig. 9-12,5 surface color of redistributing layer after baking can be deep compared with normal.At baking
Before reason, 5 surfacing of redistributing layer, without apparent particle；After toasted processing, observed respectively under 50 times and 100 times of microscope,
It can be seen that the surface of redistributing layer 5 becomes coarse by smooth, granular sensation is obvious, passes through shearing force size and failure mode pipe
Control, the roughness on 5 surface of redistributing layer meet the binding force with follow-up process.Moreover, not passing through relative to redistributing layer 5
The chip product of processing is toasted, the tolerance in reliability test of the chip product after increasing baking is stronger, meets chip
Stress demand plays the purpose for saving packaging cost so as to save one layer before sputtering passivation layer again.
Embodiment 20
The present embodiment provides a kind of chip-packaging structure, which is combined using the increase redistributing layer in embodiment as above
The chip packaging method of power is formed, including insulating layer, conductive layer, salient point 9, redistributing layer 5 and with the wafer 1 of weld pad 2；Insulation
Layer includes the first passivation layer 3 and the second passivation layer 6, and the first passivation layer 3 is set to the surface of wafer 1, and the first passivation layer 3 has first
Opening, the first opening expose weld pad 2；Redistributing layer 5 is formed between the first passivation layer 3 and the second passivation layer 6, for again
It is distributed weld pad 2, redistributing layer 5 has roughened surface, and roughened surface increases the binding force with follow-up process；Second passivation
Layer 6 has the second opening, and the second opening, which exposes, needs turning part；Conductive layer is electrically connected with weld pad 2, and conductive layer includes first
Metal layer 4 and second metal layer 7, the first metal layer 4 are formed in the first opening, and second metal layer 7 is formed in the second opening；
Salient point 9 is formed in second metal layer 7, and salient point 9 is electrically connected with weld pad 2.
In the present embodiment, redistributing layer 5 primarily serves the effect to the rational deployment again of weld pad 2, and redistributing layer 5 has made
5 surface of redistributing layer is subjected to coarse processing using roasting mode at rear, 5 surface roughening of Lai Shixian redistributing layer has very
Good roughening effect, increases the binding force of redistributing layer 5 Yu follow-up process.Moreover, treated that chip product exists for baking
Tolerance is stronger in reliability test, meets the stress demand of chip, so as to save one layer before sputtering passivation layer again,
Play the purpose for saving packaging cost.
In the present embodiment, optionally, the roughened surface of redistributing layer 5 can be formed by plasma etching.
In the present embodiment, according to the density requirements of chip, the first metal layer 4 is single layer structure or multilayered structure, the second gold medal
Belonging to layer 7 is single layer structure or multilayered structure.
In another embodiment of the invention, the encapsulating structure of chip further includes ball lower metal layer 8,8 shape of ball lower metal layer
At between second metal layer 7 and salient point 9, there is extraordinary adhesiveness between second metal layer 7, as the substrate of salient point 9,
Ball lower metal layer 8 can guarantee that salient point 9 is contacted with the good of weld pad 2, guarantee the signal stabilization and reliability of chip.
The above embodiment of the present invention has the following beneficial effects:
The chip packaging method and encapsulating structure of increase redistributing layer binding force of the invention, pass through the table to redistributing layer
Face carries out baking processing, increases the roughness on redistributing layer surface, enhances knot of the redistributing layer in subsequent encapsulation procedure
With joint efforts, tolerance is stronger in reliability test, meets the stress demand of chip；In addition, in the prior art under redistributing layer
Stress is buffered equipped with passivation layer, since meet chip after the coarse processing of redistributing layer answers force request, can be saved existing
Passivation layer in technology under redistributing layer, relative simplicity process flow, has saved packaging cost.Increase redistribution of the invention
The chip packaging method and structure of layer binding force, have the advantages that simple process, at low cost and high reliablity, chip exists after encapsulation
Tolerance is stronger in reliability test, has excellent performance, and is suitable for all kinds of electronic component products.
The above is several preferred embodiments of the invention, it is noted that for the ordinary skill of the art
For personnel, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications
It is considered as protection scope of the present invention.
Claims (10)
1. a kind of chip packaging method for increasing redistributing layer binding force, which comprises the following steps:
The wafer (1) that surface has the first passivation layer (3) is provided, the wafer (1) is equipped with weld pad (2), first passivation
The first opening exposed for the weld pad (2) is offered on layer (3)；
The first metal layer (4) are formed in first opening；
Redistributing layer (5) are formed on the first metal layer (4) and first passivation layer (3), and to the redistributing layer
(5) surface is toasted, so that the surface roughening of the redistributing layer (5)；
The second passivation layer (6) are formed on the surface of the redistributing layer (5), form the second opening on second passivation layer (6),
Second opening, which exposes, needs turning part；
Second metal layer (7) are formed in second opening；
The salient point (9) with the weld pad (2) electrical contact is formed on the second metal layer (7).
2. the chip packaging method according to claim 1 for increasing redistributing layer binding force, which is characterized in that baking temperature
It is 100~200 DEG C, 10~30min of baking time.
3. the chip packaging method according to claim 1 for increasing redistributing layer binding force, which is characterized in that described to divide again
Layer of cloth (5) is formed by electrochemical deposition method, the first metal layer (4) shape by way of electrochemical deposition or sputtering
At the second metal layer (7) is formed by way of electrochemical deposition or sputtering.
4. the chip packaging method according to claim 1 for increasing redistributing layer binding force, which is characterized in that described second
Passivation layer (6) is formed by coating method；Second opening is formed by way of laser ablation or wet etching.
5. the chip packaging method according to claim 1 for increasing redistributing layer binding force, which is characterized in that the salient point
(9) it is formed by depositing or planting ball mode；The ingredient of the salient point (9) is single metal or metal alloy.
6. the chip packaging method according to claim 1 for increasing redistributing layer binding force, which is characterized in that described the
It is formed on two metal layers (7) before the salient point (9) being in electrical contact with the weld pad (2), further includes: production ball lower metal layer (8)；Institute
Ball lower metal layer (8) is stated to be formed by way of electrochemical deposition or sputtering.
7. a kind of chip-packaging structure, which is characterized in that including insulating layer, conductive layer, salient point (9), redistributing layer (5) and have
The wafer (1) of weld pad (2)；
The insulating layer includes the first passivation layer (3) and the second passivation layer (6), and first passivation layer (3) is set to the wafer
(1) surface, first passivation layer (3) have the first opening, and first opening exposes the weld pad (2)；It is described again
Distribution layer (5) is formed between first passivation layer (3) and second passivation layer (6), for redistributing the weld pad
(2), the redistributing layer (5) has roughened surface；Second passivation layer (6) has the second opening, second opening
It exposes and needs turning part；
The conductive layer is electrically connected with the weld pad (2), and the conductive layer includes the first metal layer (4) and second metal layer (7),
The first metal layer (4) is formed in first opening, and the second metal layer (7) is formed in second opening；
The salient point (9) is formed on the second metal layer (7), and the salient point (9) is electrically connected with the weld pad (2).
8. the chip packaging method according to claim 7 for increasing redistributing layer binding force, which is characterized in that described to divide again
The roughened surface of layer of cloth (5) is formed by roasting mode.
9. the chip packaging method according to claim 8 for increasing redistributing layer binding force, which is characterized in that baking temperature
It is 100~200 DEG C, 10~30min of baking time.
10. it is according to claim 7 increase redistributing layer binding force chip packaging method, which is characterized in that it is described again
The roughened surface of distribution layer (5) is formed by plasma etching mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910456224.6A CN110335828A (en) | 2019-05-29 | 2019-05-29 | A kind of chip packaging method and encapsulating structure increasing redistributing layer binding force |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910456224.6A CN110335828A (en) | 2019-05-29 | 2019-05-29 | A kind of chip packaging method and encapsulating structure increasing redistributing layer binding force |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110335828A true CN110335828A (en) | 2019-10-15 |
Family
ID=68141139
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910456224.6A Pending CN110335828A (en) | 2019-05-29 | 2019-05-29 | A kind of chip packaging method and encapsulating structure increasing redistributing layer binding force |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110335828A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102148210A (en) * | 2009-12-25 | 2011-08-10 | 富士通半导体股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN105070665A (en) * | 2015-07-16 | 2015-11-18 | 北京工业大学 | Wafer level chip packaging process |
| CN109285928A (en) * | 2018-09-28 | 2019-01-29 | 厦门乾照光电股份有限公司 | A kind of flip LED chips and preparation method thereof |
-
2019
- 2019-05-29 CN CN201910456224.6A patent/CN110335828A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102148210A (en) * | 2009-12-25 | 2011-08-10 | 富士通半导体股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN105070665A (en) * | 2015-07-16 | 2015-11-18 | 北京工业大学 | Wafer level chip packaging process |
| CN109285928A (en) * | 2018-09-28 | 2019-01-29 | 厦门乾照光电股份有限公司 | A kind of flip LED chips and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI260060B (en) | Chip electrical connection structure and fabrication method thereof | |
| JPH0220848Y2 (en) | ||
| JP3186941B2 (en) | Semiconductor chips and multi-chip semiconductor modules | |
| TWI233172B (en) | Non-leaded semiconductor package and method of fabricating the same | |
| TW200537672A (en) | Land grid array packaged device and method of forming same | |
| WO2022012422A1 (en) | Package substrate manufacturing method | |
| TWI389281B (en) | Method of forming flip-chip bump carrier type package | |
| TW200818453A (en) | Semiconductor package on which a semiconductor device is stacked and production method thereof | |
| TW200807588A (en) | Semiconductor device, built-up type semiconductor device using the same, base substrate, and manufacturing method of semiconductor device | |
| TWI233188B (en) | Quad flat no-lead package structure and manufacturing method thereof | |
| CN102738131B (en) | Semiconductor module, encapsulating structure and method for packing thereof | |
| TWI263284B (en) | Method of fabricating wafer level package | |
| US20220115356A1 (en) | Fan-out encapsulation structure and encapsulation method for chip | |
| TWI243471B (en) | Semiconductor device and its manufacturing method | |
| US20040222520A1 (en) | Integrated circuit package with flat metal bump and manufacturing method therefor | |
| US11538617B2 (en) | Integrated magnetic core inductors on glass core substrates | |
| CN109427726A (en) | Electronic packaging structure, packaging substrate thereof and manufacturing method thereof | |
| TW200845246A (en) | High-density fine line package structure and method for fabricating the same | |
| TWI240390B (en) | Semiconductor package structure and method for fabricating the same | |
| TW200535944A (en) | Method for manufactruing semiconductor device and method for deciding position of semiconductor element | |
| TW200406906A (en) | Electronic circuit apparatus and integrated circuit device | |
| CN110299330A (en) | A kind of encapsulating structure and packaging method of wafer stage chip | |
| TW201019457A (en) | Multi-chips package and manufacturing method thereof | |
| CN110335828A (en) | A kind of chip packaging method and encapsulating structure increasing redistributing layer binding force | |
| TW201143018A (en) | A three dimensional chip stacking electronic package with bonding wires |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20191015 |