CN110335323B - Bit stream imaging method of field programmable gate array device - Google Patents

Abstract

The invention discloses a bit stream imaging method of a field programmable gate array device, which comprises imaging and automatic labeling; imaging: 1.1), removing irrelevant information: locking data in a CLB part in a logic part of FPGA programmable logic, and omitting the rest information from consideration in the bit stream imaging process; 1.2) carrying out image restoration on the single CLB, and splicing the single CLB restoration images according to the two-dimensional array arrangement row number in the Device image to form a whole bit stream restoration image; automatic labeling: specifying the resource region range and bitstream output file name utilized by the implementation process. The invention provides a brand-new algorithm for converting information for describing configurable resources in a bit stream into a two-dimensional image with a strong mapping relation by combining two-dimensional physical distribution of FPGA logical resources, and realizes automatic labeling of module functions.

Description

Bit stream imaging method of field programmable gate array device

Technical Field

The invention relates to the Field of imaging of Field Programmable Gate Array (FPGA) bit streams, in particular to an imaging and automatic labeling technology of a bit stream programming logic configurable resource part combined with a two-dimensional structure of FPGA resources.

Background

Field programmable gate arrays have become one of the most widely used advanced digital systems during the last two decades. The great reason is the flexibility of FPGA products, mainly due to the property that FPGAs can use bit streams to reconfigure internal logic.

The FPGA bit stream updates an Intellectual Property core (IP) on the FPGA or adds a new IP core by configuring Configurable resources inside the FPGA, including a Configurable Logic Block (CLB), an Input/Output Block (IOB), a Block memory (BRAM) and the like, thereby realizing rapid updating. Obtaining information from an FPGA bitstream is generally divided into three steps: (1) acquiring a bit stream, (2) decrypting the bit stream, and (3) establishing a mapping relation between the FPGA netlist and the bit stream file. In step three, the most common is the reverse engineering technique of the bit stream.

In the bit stream imaging process, there are two problems. Firstly, the picture is oversized; and secondly, the mapping relation between the image and the device is insufficient, namely the correlation with the structure of the FPGA device cannot be shown. One reason for the problem is that the bit stream generated by the FPGA configuration is large, and the bit stream generated by the FPGA of the same model is fixed, for example, the bit stream generated by the XilinxZYNQ-7000702 FPGA is 3.85 mbytes (3,951 kbytes). The data are all used for generating images without loss, so that the pixel size of the image reaches more than 2000 multiplied by 2000 orders of magnitude, and the running speed is extremely low during machine learning training; on the other hand, according to the FPGA user manual, the content actually used for configuring the Configurable Logic Block (CLB) in the bitstream only accounts for 60% of the total data volume, and the resources used by the actual FPGA implementation algorithm are much less and less, so that there is a large amount of data irrelevant to the resource configuration in the bitstream, resulting in an oversized picture. As for the second problem, on one hand, the influence of the large amount of irrelevant data is generated, and on the other hand, a reasonable imaging algorithm which fully combines the bit stream structure and the FPGA physical resource distribution is lacked, so that the bit stream cannot be converted into a visual and clear image. In fact, however, the FPGA resource itself has two-dimensional physical distribution, and if it can be organically combined with the physical location information of the device in the imaging process, the mapping relationship of bit stream imaging can be greatly improved.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a bit stream imaging method of a field programmable gate array device.

In order to solve the technical problem, the invention provides a bit stream imaging method of a field programmable gate array device, and provides a method for converting information for describing configurable resources in a bit stream into a two-dimensional image with strong readability by combining two-dimensional physical distribution of FPGA logical resources, and automatic labeling is realized.

A Field Programmable Gate Array (FPGA) device, one of the most widespread digital systems, is mainly characterized by the feature that its internal resources can be reconfigured by a bitstream. The invention analyzes the bit stream file structure of the model FPGA of ZYNQ series of Xilinx company, and extracts the content of FDRI part for describing FPGA programmable point and connection relation by analyzing the identifier of file head and file tail. And then, comparing and analyzing the configuration information with the real layout wiring diagram of the FPGA to find out the mapping relation between the use condition of the hardware resources and the binary code value in the bit stream file. According to the position of the configuration node of the binary code value on the actual FPGA, a method for converting a bit stream file into a visual image reflecting the layout relation of the configurable node is provided, meanwhile, the automatic labeling of the label of the image is realized, and a picture set for training and testing of machine learning is generated.

The scheme provided by the invention is as follows: a bit stream imaging method of a field programmable gate array device comprises the following steps of imaging and automatic labeling:

firstly, imaging:

1.1), removing irrelevant information:

locking data in a CLB part in a logic part of FPGA programmable logic, and omitting the rest information from consideration in the bit stream imaging process;

1.2) carrying out image restoration on the single CLB, and splicing the single CLB restoration images according to the two-dimensional array arrangement row number in the Device image to form a whole bit stream restoration image;

II, automatic labeling:

specifying the resource region range and bitstream output file name utilized by the implementation process.

The improvement of the bit stream imaging method of the field programmable logic gate array device of the invention is as follows:

the 1.1) is as follows:

confirming the length of an FDRI (Frame Data Register) part by reading two words at the end of a header (Head-of-File) of a bitstream File; removing a file header and a file tail (End-of-Flie), and extracting the content of the FDRI part; FDRI data is stored as a minimum configuration unit in a frame form, and the length of a frame is determined according to the model of the FPGA (when the model of the FPGA is Xilinx ZYNQ-7000ZC702, the length of the frame is 10008; when the model of the FPGA is Xilinx ZYNQ-7000ZC703, the length of the frame is 14796; and when the model of the FPGA is Xilinx ZYNQ UltraScale + ZCU102, the length of the frame is 71260); the method comprises the steps that the lower left corner coordinates (Xmin, Ymin) and the upper right corner coordinates (Xmax, Ymax) of a CLB resource region are restrained during comprehensive implementation, and the difference between bit streams implemented under different restraint conditions is compared to obtain a bit stream configuration principle, namely the specific position of a CLB in an FDRI; and extracting data configuring the CLB part in the FDRI according to the position information to be used as final imaging data.

The 1.2) is as follows: dividing the obtained data configured with the CLB into a plurality of data blocks, wherein each data block comprises a certain number of continuous frames, and the length of each frame depends on the type of the FPGA; for ZC702 and ZC703, two words at the same position of all frames in a data block are taken to form a CLB image block; for ZCU102, 1.5 words of the same position are taken to form a CLB image block; thus, one data block can obtain a plurality of image blocks; all the data blocks form a CLB image block according to the method; splicing the image blocks according to the positions of the image blocks in a Device image to obtain a complete bit stream recovery image; the image finally recovered by the method has high mapping relation with the Device image.

The automatic labeling of the second step is as follows: in the process of generating the bit stream file, the position and the size of the comprehensive realization area are restricted by using a Tcl scripting language, and the output bit stream file is named as a Function _ Xmin _ Ymin _ Xmax _ Ymax _ bit format, which indicates the functional module and the position information thereof contained in the output bit stream file.

Note: in the process of using the bit stream imaging method provided by the invention, the file name is read to generate a label file, and the file content comprises the functional module and the position information thereof.

The bit stream imaging method of the field programmable logic gate array device is further improved as follows:

the automatic labeling of the second step is as follows:

2.1) newly building a project, and designing a circuit with a Function;

2.2) performing function simulation and synthesis;

2.3), restricting the resource area (including position and size, determined by coordinates (Xmin, Ymin) and (Xmax, Ymax) used by physical implementation, and carrying out physical implementation;

2.4), generating an export bit stream, and naming the bit stream file as a Function _ Xmin _ Ymin _ Xmax _ Ymax.bit format;

2.5) reading a bit stream file with a file name format of Function _ Xmin _ Ymin _ Xmax _ Ymax.bit;

2.6) generating a required label file according to the file name information, wherein the content of the label file comprises the module type and the position information of the module type;

2.7) imaging the bit stream by using the imaging method in the first step to obtain a recovery image;

2.8), numbering in the order from 0, and naming the image and the label file as the same number;

2.9) judging whether the generated image number meets the requirement or not according to the planned generated bit stream image number; if the judgment result is yes, ending the automatic labeling; and if the judgment result is negative, entering the step 2.1).

The bit stream imaging method of the field programmable logic gate array device is further improved as follows:

the imaging method in the first step specifically comprises the following steps:

1) starting imaging;

2) opening a bit stream file according to bytes and removing a file head and a file tail; obtaining an FDRI part;

3) reading the next frame of the FDRI;

4) judging whether the FDRI is traversed or not according to a judgment rule for judging whether reading is successful or not; if the judgment result is yes, entering the step 5); if the judgment result is negative, entering step 6);

5) splicing all CLB image blocks according to the positions of the CLB image blocks in the Device image to obtain a complete recovery image; finishing the imaging;

6) judging whether the current frame is the initial frame of the frame configured with the CLB or not according to the bit stream configuration principle as a judgment rule; if yes, entering step 7); if the judgment result is negative, entering the step 3);

7) and reads and saves continuous multi-frame data including the frame (36 frames for ZC702 and ZC 703; for ZCU102, Slice _ L is 29 frames and Slice _ M is 79 frames); obtaining a CLB data block;

8) reading the next word of all frames in the CLB data block;

9) judging whether the CLB data block is traversed or not according to a judgment rule for judging whether reading is successful or not; if the judgment result is yes, entering the step 3); if the judgment result is negative, entering the step 10);

10) and judging whether the words are idle words or not by taking the result obtained by analyzing the structure of the bit stream file as a judgment rule (for ZC702 and ZC703, the 51 st word is an idle word; for ZCU102, words 46, 47, 48 are idle words); if yes, entering step 8); if the judgment result is negative, entering the step 11);

11) sequentially filling the words into the CLB image block according to the channel sequence; step 8) is entered.

The invention mainly relates to two aspects of imaging and automatic labeling. Automatic labeling mainly works on the process of acquiring a bitstream. When generating bit stream engineering in batches, it is inevitably necessary to use the Tcl scripting language to implement script batch operations. When the Tcl is used to operate the project, the resource area range and the bit stream output file name used by the implementation process can be specified, so after the implementation area is specified, the bit stream Function information and the area position information can be stored and output in the format of the bit stream file name (Function _ Xmin _ Ymin _ Xmax _ ymax). After a large amount of bit streams are obtained, imaging operation is carried out on the bit streams, the file name content of the bit streams is read at the same time, a label file is generated, and an automatic labeling function is achieved.

In the imaging process, aiming at two defects of directly converting the bit stream into a gray image according to bytes in the bit stream imaging work: (1) the picture size is too large; (2) the mapping relationship is insufficient. So that the valid data in the bitstream needs to be specified first. The FPGA programmable logic can be divided into five parts, namely a logic part, a special resource (BRAM, DSP48E1), a general Input and Output (IOB), a communication interface, other programmable logic expansion interfaces and the like. The logic part comprises Configurable Logic Blocks (CLBs) and input and output blocks for interfaces, each CLB comprises two slices, each Slice comprises 4 Lookup tables (LUTs) and 8 Flip-flops (FFs) in Xilinx ZYNQ-7000ZC702 and ZC703FPGA devices, and each CLB comprises one Slice in ZCU102FPGA devices, and the Slice comprises two types of Slice _ L and Slice _ M, each type comprises 8 LUTs and 16 FFs for realizing combinational circuits and sequential logic circuits, and embodies the internal logic connection relationship of the FPGA. Since the invention is concerned with the parts of the bitstream actually used to implement the combinational and sequential logic circuits, as well as the logical connections, the CLB part that locks the data in the logical parts is finally determined, meaning that the rest is independent of the CLB configuration, i.e. the logical connections of the algorithms implemented by the FPGA, and is therefore left out of consideration during the bitstream imaging process.

In order to solve the problem of the excessive size of the visualization, according to the analysis of the internal structure of the bitstream, a header-of-File (Head-of-File) and a footer (End-of-Flie) which are not related to the configuration information may be removed, and only an FDRI (Frame Data Register, InputRegister) Data part remains. The data of the FDRI part is stored in a frame form as a minimum configuration unit, the length of the frame depends on the model of the FPGA, for example, a ZC702 and a ZC703 take 101 words (32 bits) as one frame, and a ZC102 takes 93 words (32 bits) as one frame. These frames configure general purpose input output, special resources and logic, etc. Data of the CLB in which the logical part is configured is extracted. Typically, frames used to configure CLBs in FPGAs account for only around 60% of the total size. This step may reduce the amount of data that needs to be imaged.

The conventional imaging operation is to arrange the obtained data in order to obtain an image, but this operation has the problems of too large image and insufficient mapping relationship. In order to obtain a better mapping relation, a Vivado tool is combined to realize a Device graph format in design, CLBs in an FPGA are distributed in a two-dimensional array mode, and for example, the CLBs in the FPGA are distributed (unfilled) in a Xilinx ZYNQ-7000ZC702 by adopting a 150X 57 size array. Therefore, in order to improve the mapping relation between the final image and the two-dimensional distribution of the FPGA, the invention carries out image restoration on the single CLB, and splices the single CLB restoration images according to the two-dimensional array arrangement row number in the Device image to form the whole bit stream restoration image.

In order to obtain an image with high mapping relation with a Device, the obtained data configuring the CLBs is divided into parts for describing each CLB, each column of CLBs in an FPGA Device is described by using a certain number of continuous frames in a bit stream through analyzing the structure of the FPGA bit stream (for example, each 36 frames in ZC702 and ZC703 describe one column of CLBs; each 29 frames in ZCU102 describe one column of Slice _ L, and each 79 frames describe one column of Slice _ M), in the continuous frames, each frame in ZC702 and ZC703 provides two words to describe one CLB, and each frame in ZCU102 provides 1.5 words (with a big end and a small end problem), the data for describing each CLB can be extracted through the rules, and finally, a single CLB corresponding image is generated in a sequential arrangement mode, and the single CLB recovery images are spliced according to the two-dimensional array arrangement row number in the Device image to form the whole bit stream recovery image. The image finally recovered by the method has high mapping relation with the Device image.

The invention provides a brand-new algorithm for converting information for describing configurable resources in a bit stream into a two-dimensional image with a strong mapping relation by combining two-dimensional physical distribution of FPGA logical resources, and realizes automatic labeling of module functions. The invention is successfully implemented in Xilinx ZYNQ-7000SoC series ZC702 and ZC703, and Ultrascale + MPSOC ZCU102 FPGA.

The invention has the following technical advantages:

1. the data of non-CLB in FDRI is removed by removing the header and the tail of the bit stream file, thereby solving the problem of overlarge image size in the prior art;

2. the CLB data blocks are imaged and then spliced, so that the problem of insufficient mapping relation between images and devices in the prior art is solved.

Drawings

The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.

FIG. 1 shows the last two words of the header of example 1;

FIG. 2 is a ZC702 bitstream file structure in embodiment 1;

FIG. 3 is a schematic view of an evaluation platform Device of Xilinx ZYNQ-7000ZC702 in example 1;

FIG. 4 is a ZC702 bit stream configuration principle in embodiment 1;

fig. 5 is a corresponding relationship of image blocks in embodiment 1;

fig. 6 is a flowchart of imaging in example 1.

Detailed Description

The invention will be further described with reference to specific examples, but the scope of the invention is not limited thereto.

The invention can finally convert the information for configuring the CLB in the known bit stream into an image without loss, has a position corresponding relation with the original FPGA two-dimensional structure, and can output the corresponding position information and the function information for automatic marking, thereby being used as a training set and a test set for relevant research in machine learning.

The following embodiment 1 is to apply the present invention to perform target detection and identification on the bit stream used for the Hash algorithm on the Xilinx ZYNQ-7000ZC702FPGA device.

Embodiment 1, realizing the bit stream reverse engineering imaging target recognition work under the Xilinx ZYNQ-7000ZC702 evaluation platform:

shown in fig. 1 are two words 0x30004000, 0x500F6C78 at the end of the bitstream header. The previous word indicates writing data to the register with address 00010, i.e. writing data to the FDRI register. The latter word represents a word of write data of length 0x0F6C78 (decimal representation: 1010808). The data of the FDRI part can thus be extracted (as indicated by the dashed box in fig. 1).

As shown in fig. 2, the FDRI part of the bitstream file structure includes the contents of 6 clock domains, the start frame of each clock domain is marked in fig. 2, and the start frames of the CLB columns in clock domain 1, each of which includes 50 CLBs. After the FDRI completes the configuration of one row of CLBs, the next row of CLBs is configured.

FIG. 3 is a FPGADevice diagram, including PS and PL portions. The distribution of 6 clock domains is given in the PL section. The CLB rows, columns that each clock domain contains are also given in fig. 3. The 6 clock domains consist of a total of 150 × 57 CLB blocks. The contents of each CLB block are configured by the data in the FDRI.

Fig. 4 shows the bit stream configuration principle of the complete ZC702, in which the start frame of the configuration information of each CLB column in the FDRI part is given for each clock domain, and each CLB column is configured by 36 frames. Frames not within this range configure the non-CLB portion and need to be discarded when imaging.

As shown in fig. 5, one CLB in the Xilinx ZYNQ-7000ZC702 shares a 36 × 2 word configuration, and one CLB is composed of two slices, that is, each Slice uses 36 words, 36 × 4 bytes, 144 bytes, and is divided into three channels of RGB, so that the Slice of each channel only contains 144/3 bytes, 48 bytes, in order to make the length and width of the final image size as close as possible, the image pixel size is selected to be 8 × 6 × 3, each pixel point value is 0-255 corresponding to exactly one 8-bit byte, and the bytes used for describing the CLB module are spliced in array order. Finally, all the 6 × 8 × 3 image blocks are merged to form a restored image, and the pixel size of the whole image corresponding to ZC702 is (150 × 6) × (57 × 8 × 2) × 3, i.e., 900 × 912 × 3.

As shown in fig. 6, for a complete bit stream imaging process, for a bit stream image, the file header and the file trailer are removed first to obtain the FDRI part. And then sequentially searching CLB head frames in the FDRI, reading multi-frame data including the head frames to obtain a CLB data block, sequentially filling the data blocks to obtain image blocks, and finally splicing all the image blocks to obtain a complete recovery graph.

The size of the image imaged using this method is about 2.34Mbyte, which is 60% of the size of the bitstream file (3.85 Mbyte). The problem that the direct imaging size of the bit stream file is too large is solved.

Since the purpose of this example is to identify the bitstream function by bitstream imaging, the actually required training set is a picture into which a plurality of types of bitstreams of different functions are converted, and the function and position information thereof is used as a label. On the premise of selecting ten different Hash algorithms as the engineering of the functional tags, the manufacturing of the training set can be generally divided into two steps, wherein the first step is to generate a large number of different bit streams with the same function in batches through a Tcl script language, and the second step is to use a Python language to perform imaging processing on the obtained bit stream file and convert the bit stream file into the training set which accords with the machine learning input format (picture + tag).

In order to generate a plurality of types of bit streams with the same function but different content forms, the method adopted by the invention for generating each type is to carry out constraint limitation on the implementation area of a project, namely, each project generates different bit stream sets as one type, and a plurality of types are generated by repeatedly operating the replacement project, wherein the method comprises the following operation steps:

1) newly building a project, designing and realizing a type of Hash algorithm, and naming the Hash algorithm as Function;

2) performing functional simulation and synthesis;

3) restricting a resource area (comprising a position and a size, determined by coordinates (Xmin, Ymin) and (Xmax, Ymax)) used by physical implementation to perform physical implementation;

4) generating an export bit stream, and naming the bit stream file as a Function _ Xmin _ Ymin _ Xmax _ Ymax.

5) Judging whether the generated bit stream quantity meets the requirement or not according to the planned generated bit stream quantity; if the judgment result is negative, entering the step 3); if the judgment result is yes, entering the step 6);

6) judging whether the generated category meets the requirements or not according to the category of the Hash algorithm generated by the plan; if the judgment result is negative, entering the step 1); if the judgment result is yes, entering the step 7);

7) and ending the bit stream generation.

Because the invention needs to generate a large amount of bit streams and the graphical interface has low operation efficiency, the Tcl script language is adopted to carry out the steps and automatically generate the bit streams in batches.

In order to perform imaging processing on a large number of bit stream files and extract module type and position information from the bit stream files to generate label files, the automatic labeling method provided by the invention is adopted to perform imaging processing on a large number of bit streams. The method mainly comprises the following steps:

1) reading a bit stream file with a file name format of Function _ Xmin _ Ymin _ Xmax _ Ymax.bit;

2) generating a required label file according to the file name information, wherein the content of the label file comprises the module category and the position information of the module category;

3) imaging the bit stream by using the imaging method (as shown in fig. 5) provided by the invention to obtain a recovery graph;

4) numbering the images and the label files in the sequence from 0, and naming the images and the label files as the same number;

5) judging whether all bit streams are processed or not according to the number of the generated bit stream files; if the judgment result is yes, ending the automatic labeling; and if the judgment result is negative, entering the step 1).

The method can rapidly generate a large number of bit stream images and corresponding label files thereof in batches without manual operation, and the bit stream images and the corresponding label files are used as a training set and a test set of the deep neural network model.

Finally, it should also be noted that the above-mentioned embodiments illustrate only specific embodiments of the invention. It is obvious that the invention is not limited to the above embodiments only. All modifications which can be derived or suggested by a person skilled in the art from the disclosure of the invention are considered to be within the scope of the invention.

Claims (5)

1. The bit stream imaging method of the field programmable gate array device is characterized by comprising the following steps of imaging and automatic labeling:

step one, imaging:

1.1), removing irrelevant information:

locking data in a CLB part in a logic part of FPGA programmable logic, and omitting the rest information from consideration in the bit stream imaging process;

1.2) carrying out image restoration on the single CLB, and splicing the single CLB restoration images according to the two-dimensional array arrangement row number in the Device image to form a whole bit stream restoration image;

step two, automatic labeling:

specifying the resource region range and bitstream output file name utilized by the implementation process:

in the process of generating the bit stream file, the position and the size of the comprehensive realization area are restricted by using a Tcl scripting language, and the output bit stream file is named as a Function _ Xmin _ Ymin _ Xmax _ Ymax _ bit format, which indicates the functional module and the position information thereof contained in the output bit stream file.

2. The bit stream imaging method of a field programmable gate array device according to claim 1, wherein:

the 1.1) is as follows:

confirming the length of the FDRI part by reading two words at the tail end of the file header of the bit stream file; removing a file header and a file tail, and extracting the content of the FDRI part; FDRI data is stored as a minimum configuration unit in a frame form, and the length of the frame is determined according to the model of the FPGA; the method comprises the steps that the lower left corner coordinates (Xmin, Ymin) and the upper right corner coordinates (Xmax, Ymax) of a CLB resource region are restrained during comprehensive implementation, and the difference between bit streams implemented under different restraint conditions is compared to obtain a bit stream configuration principle, namely the specific position of a CLB in an FDRI; and extracting data configuring the CLB part in the FDRI according to the position information to be used as final imaging data.

3. The bit stream imaging method of the field programmable gate array device according to claim 2, wherein:

the 1.2) is as follows: dividing the obtained data configured with the CLB into a plurality of data blocks, wherein each data block comprises a certain number of continuous frames, and the length of each frame depends on the type of the FPGA; for ZC702 and ZC703, two words at the same position of all frames in a data block are taken to form a CLB image block; for ZCU102, 1.5 words of the same position are taken to form a CLB image block; thus, one data block can obtain a plurality of image blocks; all the data blocks form a CLB image block according to the method; splicing the image blocks according to the positions of the image blocks in a Device image to obtain a complete bit stream recovery image; the image finally recovered by the method has high mapping relation with the Device image.

4. The bit stream imaging method of a field programmable gate array device according to claim 3,

the automatic labeling of the second step is as follows:

2.1) newly building a project, and designing a circuit with a Function;

2.2) performing function simulation and synthesis;

2.3) restricting the resource area used by physical realization to carry out physical realization;

2.4), generating an export bit stream, and naming the bit stream file as a Function _ Xmin _ Ymin _ Xmax _ Ymax.bit format;

2.5) reading a bit stream file with a file name format of Function _ Xmin _ Ymin _ Xmax _ Ymax.bit;

2.6) generating a required label file according to the file name information, wherein the content of the label file comprises the module type and the position information of the module type;

2.7) imaging the bit stream by using the imaging method in the first step to obtain a recovery image;

2.8), numbering in the order from 0, and naming the image and the label file as the same number;

2.9) judging whether the generated image number meets the requirement or not according to the planned generated bit stream image number; if the judgment result is yes, ending the automatic labeling; and if the judgment result is negative, entering the step 2.1).

5. The bit stream imaging method of the field programmable gate array device according to any of claims 1 to 3, characterized in that:

the imaging method in the first step specifically comprises the following steps:

1) starting imaging;

2) opening a bit stream file according to bytes and removing a file head and a file tail; obtaining an FDRI part;

3) reading the next frame of the FDRI;

4) judging whether the FDRI is traversed or not according to a judgment rule for judging whether reading is successful or not; if the judgment result is yes, entering the step 5); if the judgment result is negative, entering step 6);

5) splicing all CLB image blocks according to the positions of the CLB image blocks in the Device image to obtain a complete recovery image; finishing the imaging;

6) judging whether the current frame is the initial frame of the frame configured with the CLB or not according to the bit stream configuration principle as a judgment rule; if yes, entering step 7); if the judgment result is negative, entering the step 3);

7) reading and storing continuous multi-frame data including the frame, wherein 36 frames are used for the ZC702 and the ZC 703; for ZCU102, Slice _ L is 29 frames and Slice _ M is 79 frames; obtaining a CLB data block;

8) reading the next word of all frames in the CLB data block;

9) judging whether the CLB data block is traversed or not according to a judgment rule for judging whether reading is successful or not; if the judgment result is yes, entering the step 3); if the judgment result is negative, entering the step 10);

10) judging whether the words are idle words or not according to a judgment rule which is a result obtained by analyzing the structure of the bit stream file; if yes, entering step 8); if the judgment result is negative, entering the step 11);

11) sequentially filling the words into the CLB image block according to the channel sequence; step 8) is entered.

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