CN110335323A - The bit stream image conversion method of field programmable gate array device - Google Patents

Abstract

The invention discloses a kind of bit stream image conversion methods of field programmable gate array device, including image conversion and automatic marking；Image conversion: 1.1) removal, to irrelevant information: by the part CLB of the data interlock in the logical gate of FPGA programmable logic, remaining information is cast out during bit stream image conversion not to be considered；1.2) image recovery, is carried out using to single CLB, and these single CLB recovery figures are spliced according to the two-dimensional array line number in Device figure, whole picture bit stream is formed and restores figure；Automatic marking: the resource area range and bit stream export file name that specified realization process is utilized.The present invention provides a kind of completely new combination fpga logic resource two-dimensional physical distributions, convert the information for being used to describe configurable resource in bit stream to the algorithm of the stronger two dimensional image of mapping relations, and realize the automatic marking of functions of modules.

Description

The bit stream image conversion method of field programmable gate array device

Technical field

The present invention relates to field programmable gate array (FPGA, Field Programmable Gate Array) ratios The image conversion field of spy's stream, specially proposes a kind of bit stream programmed logic configurable resource of combination FPGA resource two-dimensional structure Partial image conversion and automatic marking technology.

Background technique

Field programmable gate array became one of the most widely used advanced digital systems in the past two during the decade. Wherein very big reason is the flexibility of FPGA product, and essentially consisting in FPGA can be used bit stream to carry out weight to internal logic Configure this characteristic.

FPGA bit stream is by configuring configurable resource inside FPGA, including configurable logic blocks (Configurable Logic Block, CLB), input/output module (Input/Output Block, IOB), block storage (BRAM) etc., to FPGA Upper IP core (Intellectual Property, IP) is updated or adds new IP kernel, to realize efficiently more It is new to regenerate.Information is obtained from FPGA bit stream and is generally divided into three steps: (1) obtaining bit stream, (2) decrypted bitstream, and (3) are established The mapping relations of FPGA netlist and bit stream file.In step 3, the most commonly used is the reverse engineering techniques of bit stream.

During bit stream image conversion, there are problems that two o'clock.First is that dimension of picture is excessive；Second is that image and device reflect Relationship deficiency is penetrated, i.e., can not show the correlation with FPGA device structure.On the one hand one Producing reason of problem is that FPGA matches The excessive problem of the bit stream set, the bit stream size that the FPGA of same serial model No. is generated be it is fixed, such as XilinxZYNQ- Bit stream fixed size caused by 7000 702FPGA is 3.85M byte (i.e. 3,951K byte).These data are completely used for Lossless generation image will lead to picture pixels size and reach 2000 × 2000 orders of magnitude or more, will lead to machine learning training luck Scanning frequency degree is extremely slow；On the other hand, practical in the bitstream for configuring configurable logic block (CLB) according to FPGA user's manual Content only account for the 60% of total amount of data, and wherein actual FPGA realizes that the resource that is used of algorithm is even more fewer and fewer, So there are data largely unrelated with resource distribution in the bitstream, it is excessive to result in dimension of picture.As for problem two, a side Face be since the influence of above-mentioned a large amount of extraneous datas generates, be on the other hand then it is reasonable due to lacking one, sufficiently combine than Special flow structure and the image conversion algorithm of FPGA physical resource distribution, can not convert bit stream in a visual and clear figure Picture.However in fact, FPGA resource inherently has two-dimensional physical distribution, if can during image conversion with the physical bit of device Confidence breath organically combines, and will substantially improve the mapping relations of bit stream image conversion.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of bit stream pictures of field programmable gate array device Change method.

In order to solve the above technical problem, the present invention provides a kind of bit flow graphs of field programmable gate array device Pictureization method proposes a kind of combination fpga logic resource two-dimensional physical distribution, will be used to describe configurable resource in bit stream The method that information is converted into readable strong two dimensional image, and realize automatic marking.

Field programmable gate array (FPGA) device essentially consists in it as one of most commonly used digital display circuit Portion's resource can reconfigure this characteristic by bit stream.Bit stream of the present invention to the model FPGA of Xilinx company ZYNQ series File structure is analyzed, and by the identifier of Study document head and end-of-file, is extracted and be may be programmed point for describing FPGA With the content of the part FDRI of connection relationship.Then configuration information and the true placement-and-routing's figure of FPGA are compared and analyzed, Have found the mapping relations of binary code value in hardware resource service condition and bit stream file.According to the configuration of binary code value Position of the node in actual FPGA, propose it is a kind of convert bit stream file to reflect configurable node layout's relationship can Method depending on changing image, while realizing the automatic marking of the label of image, generate the figure of the training and test for machine learning Piece collection.

Scheme provided by the invention are as follows: a kind of bit stream image conversion method of field programmable gate array device, packet Include image conversion and automatic marking:

One, image conversion:

1.1), to the removal of irrelevant information:

By CLB part of the data interlock in the logical gate of FPGA programmable logic, remaining information is in bit stream picture Cast out during changing and does not consider；

1.2) image recovery, is carried out using to single CLB, and according to the two-dimensional array line number in Device figure to this A little single CLB recovery figures are spliced, and are formed whole picture bit stream and are restored figure；

Two, automatic marking:

The resource area range and bit stream export file name that specified realization process is utilized.

The improvement of bit stream image conversion method as field programmable gate array device of the invention:

It is described 1.1) are as follows:

Two words by reading end file header (Head-of-File) of bit stream file confirm FDRI (Frame Data Register, Input Register) part length；File header and end-of-file (End-of-Flie) are removed, is extracted The content of the part FDRI；FDRI data in the form of frame as minimal configuration unit store, frame length depending on FPGA model (when When FPGA model Xilinx ZYNQ-7000ZC702, frame length 10008；When FPGA signal is Xilinx ZYNQ- When 7000ZC703, frame length 14796；As FPGA model Xilinx ZYNQ UltraScale+ZCU102, frame length For 71260)；By being sat in comprehensive realize to the lower-left angular coordinate (Xmin, Ymin) of the CLB resource area used and the upper right corner Mark (Xmax, Ymax) is constrained, and is compared the difference between the bit stream realized under various boundary conditions, is obtained bit stream configuration The specific location of principle, i.e. CLB in FDRI；According to location information, the data that the part CLB is configured in FDRI are extracted, as The data of final image.

It is described 1.2) are as follows: for obtain configuration CLB data, be divided into multiple data blocks, each data block packet Containing continuous a certain number of frames, frame length is depending on FPGA model；For ZC702 and ZC703, takes in a data block and own Two words of frame same position constitute a CLB image block；For ZCU102,1.5 words of same position is taken to constitute a CLB Image block；Therefore the available multiple images block of a data block；All data blocks are constituted into CLB image according to the method described above Block；These image blocks are spliced according to its position in Device figure, complete bit stream is obtained and restores image；Pass through Image and Device figure that the above method finally recovers have the mapping relations of height.

The automatic marking of the step 2 are as follows: in generating bit stream file processes, using Tcl scripting language to comprehensive real The position in existing region and its size are constrained, and are Function_Xmin_Ymin_ by the bit stream file designation of output Xmax_Ymax.bit format, show it includes functional module and its location information.

Note: it during using special stream picture method proposed by the present invention, reads filename and generates label file, text Part content includes functional module and its location information.

Bit stream image conversion further improvements in methods as field programmable gate array device of the invention:

The automatic marking of the step 2 be the following steps are included:

2.1), new construction, design realize that function is the circuit of Function；

2.2) functional simulation, synthesis, are carried out；

2.3), constrain resource area used in physics realization (including position and size, by coordinate (Xmin, Ymin) and (Xmax, Ymax) is determined), carry out physics realization；

2.4) export bit stream, is generated, is Function_Xmin_Ymin_Xmax_ by bit stream file designation Ymax.bit format；

2.5) the bit stream file that file name formats are Function_Xmin_Ymin_Xmax_Ymax.bit, is read；

2.6), according to file name information, required label file is generated, content includes module classification and its position letter Breath；

2.7), using image conversion method described in step 1, image conversion is carried out to bit stream, be restored figure；

2.8), by the serial number since 0, image is named as with label file and is identically numbered；

2.9), the bit stream picture number generated according to plan, judges whether generated picture number reaches requirement；Such as Fruit judging result is yes, end automatic marking；If it is judged that be it is no, enter step 2.1).

Bit stream image conversion further improvements in methods as field programmable gate array device of the invention:

The image conversion method of step 1 specifically includes the following steps:

1), start image conversion；

2) bit stream file, is opened by byte and removes file header, tail；Obtain the part FDRI；

3) FDRI next frame, is read；

4), according to read whether successful judgment rule, judge whether FDRI traverses completion；If it is judged that be it is yes, It enters step 5)；If it is judged that be it is no, enter step 6)；

5) all CLB image blocks are spliced by its position in Device figure, obtain a width completely recovery figure； Terminate image conversion；

6), according to bit stream equipping rules as judgment rule, judge whether present frame is the starting for configuring the frame of CLB Frame；When judging result be it is yes, enter step 7)；When judging result be it is no, enter step 3)；

7), reading and saving the continuous multiframe data including the frame (is 36 frames for ZC702 and ZC703；For ZCU102, Slice_L are 29 frames, and Slice_M is 79 frames)；Obtain CLB data block；

8) next word of all frames in CLB data block, is read；

9), according to read whether successful judgment rule, judge whether CLB data block traverses completion；If it is judged that Be it is yes, enter step 3)；If it is judged that be it is no, enter step 10)；

10), the result that foundation bit stream document structure analysis obtains judges whether these words are " empty as judgment rule (for ZC702 and ZC703, the 51st word is free word to not busy word "；For ZCU102, the 46th, 47,48 word is free word)；When Judging result be it is yes, enter step 8)；When judging result be it is no, enter step 11)；

11) these words, are sequentially filled CLB image block according to channel sequence；It enters step 8).

The invention mainly relates to two aspects of image conversion and automatic marking.Automatic marking mainly acts on acquisition bit and flows through Journey.When Mass production bit stream engineering, inevitably need to realize script batch operation using Tcl scripting language.And When being operated using Tcl to engineering, it is possible to specify resource area range and the bit stream output that realization process is utilized Therefore filename behind specified realization region, can store bit stream functional information and zone position information and with bit The format (Function_Xmin_Ymin_Xmax_Ymax.bit) of stream file name exports.It is compared after obtaining a large amount of bit streams Spy's stream carries out image conversion operation, and reads bit stream filename content simultaneously, generates label file, and realize automatic marking function Energy.

During image conversion, for bit stream image conversion work in directly convert gray level image by byte for bit stream The big disadvantage of two had: (1) dimension of picture is excessive；(2) mapping relations are insufficient.Therefore firstly the need of having in clear bit stream Imitate data.FPGA programmable logic can be divided into logical gate, special resource (BRAM, DSP48E1), and universal input exports (IOB), Five parts such as communication interface and other programmable logic expansion interfaces.Wherein logical gate by configurable logic block (CLB) and Input/output block for interface forms, and in Xilinx ZYNQ-7000ZC702 and ZC703FPGA device, each CLB is by two A Slice composition, each Slice include 4 look-up tables (Lookup Table, LUT) and 8 triggers (Flip-Flop, FF), then each CLB is made of a Slice and in ZCU102FPGA device, and Slice has Slice_L and Slice_M two Seed type, each type includes 8 LUT and 16 FF to realize combinational circuit and sequential logical circuit, and embodies FPGA Internal logic connection relationship.It is actually used in realization combination and sequential logical circuit since the present invention is concerned in bit stream, with And logical connection part, therefore the final part CLB determined by data interlock in logical gate, it is meant that rest part with The logical connection of the realized algorithm of the configuration of CLB, i.e. FPGA is unrelated, therefore casts out during bit stream image conversion and not examine Consider.

In order to solve the problems, such as that image conversion is oversized, according to the analysis to bit stream internal structure, it can remove and match Confidence ceases unrelated file header (Head-of-File) and end-of-file (End-of-Flie), only remains FDRI (Frame Data Register, InputRegister) data portion.The data of the part FDRI are stored in the form of frame as minimal configuration unit, frame Length depending on FPGA model, as ZC702 and ZC703 with 101 words (32 bit) be a frame, and ZC102 then with 93 words (32 ratio It is special) it is a frame.These frames configure universal input output, special resource and logical gate etc..Wherein configuration is extracted to patrol Collect the data of the CLB of part.60% or so of total size is only accounted for for configuring the frame of CLB in usual FPGA.This step can subtract The small data bulk for needing image conversion.

Common image conversion operation, which arranges the data obtained sequence, obtains image, but this operation will generate image mistake Big and mapping relations deficiency problem.To obtain better mapping relations, Device figure in design is realized in conjunction with Vivado tool Format, the CLB in FPGA is with the formal distribution of two-dimensional array, as used 150 × 57 sizes in Xilinx ZYNQ-7000ZC702 Array distribution (is not filled by full).It therefore, is the mapping relations for improving final image and FPGA Two dimensional Distribution, the present invention is used to list A CLB carries out image recovery, and spells according to the two-dimensional array line number in Device figure to these single CLB recovery figures It connects, forms whole picture bit stream and restore figure.

There is with Device the image of high mapping relations in order to obtain, the data of obtained configuration CLB are divided into and are retouched The part for stating each CLB, by analyzing FPGA bit stream structure, each column CLB can be using in bit stream continuous one in FPGA device To describe, (every 36 frame delineation one arranges CLB to the frame of fixed number amount in such as ZC702 and ZC703；Every 29 frame delineation one arranges in ZCU102 Slice_L, every 79 frame delineation one arrange Slice_M), and in the continuous frame of this section, every frame can provide two in ZC702 and ZC703 A word describes a CLB, and then every frame provides 1.5 words (there are problems that big small end) to ZCU102, extractable out by the rule For describing the data of each CLB, single CLB correspondence image finally is generated according still further to tactic mode, and according to Two-dimensional array line number in Device figure splices these single CLB recovery figures, forms whole picture bit stream and restores figure Picture.The image and Device figure that are finally recovered by the above method have the mapping relations of height.

The present invention provides a kind of completely new combination fpga logic resource two-dimensional physical distributions, will be used to describe in bit stream The information of configurable resource is converted into the algorithm of the stronger two dimensional image of mapping relations, and realizes the automatic marking of functions of modules. The present invention is finally in Xilinx ZYNQ-7000SoC series ZC702 and ZC703 and Ultrascale+MPSOC ZCU102FPGA successful implementation.

The present invention has following technical advantage:

1, by removal bit stream file header, end-of-file, the data of non-CLB in FDRI are removed, to solve existing at present The problem for having picture size present in technology excessive；

2, image conversion is carried out by CLB data block, then CLB image block is spliced, to solve existing at present There is the problem of the mapping relations of image present in technology and device deficiency.

Detailed description of the invention

Specific embodiments of the present invention will be described in further detail with reference to the accompanying drawing.

Fig. 1 is two words at 1 file header end of embodiment；

Fig. 2 is ZC702 bit stream file structure in embodiment 1；

Fig. 3 is embodiment 1Xilinx ZYNQ-7000ZC702 Evaluation Platform Device schematic diagram；

Fig. 4 is ZC702 bit stream equipping rules in embodiment 1；

Fig. 5 is image block corresponding relationship in embodiment 1；

Fig. 6 is image conversion flow chart in embodiment 1.

Specific embodiment

The present invention is described further combined with specific embodiments below, but protection scope of the present invention is not limited in This.

The present invention can finally convert the information lossless for being used to configure CLB in known bits stream to image, and with former FPGA Two-dimensional structure has position corresponding relationship, while also exportable corresponding position information and functional information carry out automatic marking, thus Correlative study can be carried out as training set and test set in machine learning.

Following example 1 is that the application present invention is calculated for Hash on Xilinx ZYNQ-7000ZC702FPGA device The bit stream of method carries out target detection and identification work.

Embodiment 1 realizes bit stream reverse engineering image conversion target under Xilinx ZYNQ-7000ZC702 Evaluation Platform Identify work:

It is as shown in Figure 1 two words 0x30004000, the 0x500F6C78 at bit stream file header end.Previous word indicates Data are written to the register that address is 00010, i.e., data are written to FDRI register.The latter word indicates the length of write-in data Degree is 0x0F6C78 (decimal representation: 1010808) a word.It is possible thereby to extract the data (dotted line as shown in figure 1 of the part FDRI Frame content).

It is illustrated in figure 2 bit stream file structure, the part FDRI includes the content of 6 clock domains, is marked out in Fig. 2 The start frame of the start frame of each clock domain and each CLB column in clock domain 1, each CLB column include 50 CLB. One column CLB of FDRI completion, which matches to postpone, again configures next column CLB.

It include the part PS and PL if Fig. 3 is FPGADevice figure.The distribution feelings of 6 clock domains are given in the part PL Condition.The CLB row, column that each clock domain includes also has been presented in Fig. 3.6 clock domains are total by 150 × 57 CLB blocks.Each The content of CLB block is all configured by the data in FDRI.

Such as the bit stream equipping rules that Fig. 4 is complete ZC702, there is shown what each clock domain, each CLB were arranged to match Confidence ceases the start frame in the part FDRI, and each CLB is arranged to be completed to configure by 36 frames.Frame within this range is not to the non-portion CLB Divide and configured, needs to give up in image conversion.

As shown in figure 5, shared 36 × 2 words configuration of a CLB in Xilinx ZYNQ-7000ZC702, and a CLB It being made of two Slice, i.e., each Slice 36 word=36 × 4 bytes=144 bytes are classified as tri- channels RGB, So the Slice in each channel only includes 144/3=48 byte, and to keep final image size length and width close as far as possible, image slices Element is sized to 8 × 6 × 3, and each pixel point value 0~255 corresponds to an octet just, will be used to describe the CLB module Byte by array order splice.Finally 6 × 8 × 3 all image blocks are stitched together as recovery figure, ZC702 is corresponding The pixel size of entire image is (150 × 6) × (57 × 8 × 2) × 3, i.e., 900 × 912 × 3.

It is illustrated in figure 6 complete bit stream image conversion process, for a bit stream picture, removes its file header first The part FDRI is obtained with end-of-file.Then the CLB head frame in FDRI is successively found, the multiframe data including head frame are read, A CLB data block is obtained, data block is filled in order then and obtains image block, finally splices to have obtained by all image blocks Whole recovery figure.

The image size obtained using this method image conversion is about 2.34Mbyte, is bit stream file (3.85Mbyte) big Small 60%.Solve the problems, such as that bit stream file through imageization is oversized.

Since the purpose of this example is to identify bit stream function by bit stream image conversion, so practically necessary instruction Practice the picture that is transformed of bit stream that collection is multiclass different function, and using its function and location information as label.It is choosing Under the premise of engineering of the ten class difference hash algorithms as functional label, the production of training set can generally be divided into two steps, and first Step then uses Python by Tcl scripting language, a large amount of different bit streams of the same function of Mass production multiclass, second step Obtained bit stream file is subjected to image conversion processing, and is converted into the instruction for meeting machine learning input format (picture+label) Practice collection.

In order to generate that multiclass function is identical but bit stream that content-form is different, the present invention generates the method that every class is taken It is that restrict is carried out to the realization region of an engineering, i.e. each engineering generates different bit stream set and is used as one kind, Replacement engineering operates repeatedly generates multiclass, and operating procedure is as follows:

1), new construction, design realize a kind of hash algorithm, are named as Function；

2) functional simulation, synthesis, are carried out；

3), constrain resource area used in physics realization (including position and size, by coordinate (Xmin, Ymin) and (Xmax, Ymax) is determined), carry out physics realization；

4) export bit stream, is generated, is Function_Xmin_Ymin_Xmax_Ymax.bit by bit stream file designation Format；

5), such bit stream quantity generated according to plan, judgement have generated whether bit stream quantity reaches requirement；If Judging result be it is no, enter step 3)；If it is judged that be it is yes, enter step 6)；

6), the hash algorithm classification generated according to plan, judges whether generated classification reaches requirement；If it is determined that knot Fruit be it is no, enter step 1)；If it is judged that be it is yes, enter step 7)；

7), end bit stream generates.

Since the present invention will generate a large amount of bit streams, graphic interface operating efficiency is low, thus using Tcl scripting language into Row above-mentioned steps, Lai Zidong Mass production.

In order to carry out image conversion processing to a large amount of bit stream file, and from bit stream file extraction module classification and position Information generates label file, the automatic marking method mentioned using the present invention, carries out image conversion processing to a large amount of bit stream.It is main The step is wanted to include:

1) the bit stream file that file name formats are Function_Xmin_Ymin_Xmax_Ymax.bit, is read；

2), according to file name information, required label file is generated, content includes module classification and its location information；

3), using image conversion method (as shown in Figure 5) proposed by the present invention, image conversion is carried out to bit stream, is restored Figure；

4), by the serial number since 0, image is named as with label file and is identically numbered；

5), according to the bit stream number of files of generation, judge whether to handle all bit streams；If it is determined that knot Fruit is yes, end automatic marking；If it is judged that be it is no, enter step 1).

This method can in the case where not needing manual operation quickly, a large amount of bit stream picture of Mass production and its right The label file answered, training set and test set as deep neural network model.

Finally, also needing it is worth noting that, listed above is only specific embodiments of the present invention.Obviously the present invention It is not limited only to above embodiments.Those skilled in the art directly can export or associate from present disclosure All deformations, be considered protection scope of the present invention.

Claims (6)

1. the bit stream image conversion method of field programmable gate array device, it is characterised in that including image conversion and automatic mark Note:

One, image conversion:

1.1), to the removal of irrelevant information:

By CLB part of the data interlock in the logical gate of FPGA programmable logic, remaining information is in bit stream image conversion mistake Cast out in journey and does not consider；

1.2) image recovery, is carried out using to single CLB, and according to the two-dimensional array line number in Device figure to these lists A CLB recovery figure is spliced, and is formed whole picture bit stream and is restored figure；

Two, automatic marking:

The resource area range and bit stream export file name that specified realization process is utilized.

2. the bit stream image conversion method of field programmable gate array device according to claim 1, feature exist In:

It is described 1.1) are as follows:

Two words by reading the file header end of bit stream file confirm the length of the part FDRI；Remove file header and file Tail extracts the content of the part FDRI；FDRI data in the form of frame as minimal configuration unit store, frame length regard FPGA model and It is fixed；By in comprehensive realize to the lower-left angular coordinate (Xmin, Ymin) and upper right angular coordinate of the CLB resource area used (Xmax, Ymax) is constrained, and the difference between the bit stream realized under various boundary conditions is compared, and it is former to obtain bit stream configuration Then, i.e. specific location of the CLB in FDRI；According to location information, the data that the part CLB is configured in FDRI are extracted, as most The data of whole image conversion.

3. the bit stream image conversion method of field programmable gate array device according to claim 2, feature exist In:

It is described 1.2) are as follows: for the data of obtained configuration CLB, be divided into multiple data blocks, each data block includes to connect Continuous a certain number of frames, frame length is depending on FPGA model；For ZC702 and ZC703, all frame phases in a data block are taken Two words with position constitute a CLB image block；For ZCU102,1.5 words of same position is taken to constitute a CLB image Block；Therefore the available multiple images block of a data block；All data blocks are constituted into CLB image block according to the method described above； These image blocks are spliced according to its position in Device figure, complete bit stream is obtained and restores image；By upper State the mapping relations that the image that method finally recovers has height with Device figure.

4. the bit stream image conversion method of any field programmable gate array device according to claim 1~3, It is characterized in that:

The automatic marking of the step 2 are as follows: in generating bit stream file processes, realize area to comprehensive using Tcl scripting language The position in domain and its size are constrained, and are Function_Xmin_Ymin_Xmax_ by the bit stream file designation of output Ymax.bit format, show it includes functional module and its location information.

5. the bit stream image conversion method of field programmable gate array device according to claim 4, feature exist In,

The automatic marking of the step 2 be the following steps are included:

2.1), new construction, design realize that function is the circuit of Function；

2.2) functional simulation, synthesis, are carried out；

2.3) resource area used in physics realization, is constrained, physics realization is carried out；

2.4) export bit stream, is generated, is Function_Xmin_Ymin_Xmax_Ymax.bit lattice by bit stream file designation Formula；

2.5) the bit stream file that file name formats are Function_Xmin_Ymin_Xmax_Ymax.bit, is read；

2.6), according to file name information, required label file is generated, content includes module classification and its location information；

2.7), using image conversion method described in step 1, image conversion is carried out to bit stream, be restored figure；

2.8), by the serial number since 0, image is named as with label file and is identically numbered；

2.9), the bit stream picture number generated according to plan, judges whether generated picture number reaches requirement；If sentenced Disconnected result is yes, end automatic marking；If it is judged that be it is no, enter step 2.1).

6. the bit stream image conversion method of any field programmable gate array device according to claim 1~3, It is characterized in that:

The image conversion method of step 1 specifically includes the following steps:

1), start image conversion；

2) bit stream file, is opened by byte and removes file header, tail；Obtain the part FDRI；

3) FDRI next frame, is read；

4), according to read whether successful judgment rule, judge whether FDRI traverses completion；If it is judged that being yes, entrance Step 5)；If it is judged that be it is no, enter step 6)；

5) all CLB image blocks are spliced by its position in Device figure, obtain a width completely recovery figure；Terminate Image conversion；

6), according to bit stream equipping rules as judgment rule, judge whether present frame is the start frame for configuring the frame of CLB；When Judging result be it is yes, enter step 7)；When judging result be it is no, enter step 3)；

7), reading and saving the continuous multiframe data including the frame (is 36 frames for ZC702 and ZC703；For ZCU102, Slice_L are 29 frames, and Slice_M is 79 frames)；Obtain CLB data block；

8) next word of all frames in CLB data block, is read；

9), according to read whether successful judgment rule, judge whether CLB data block traverses completion；If it is judged that be it is yes, It enters step 3)；If it is judged that be it is no, enter step 10)；

10), the result that foundation bit stream document structure analysis obtains judges whether these words are " idle as judgment rule Word "；When judging result be it is yes, enter step 8)；When judging result be it is no, enter step 11)；

11) these words, are sequentially filled CLB image block according to channel sequence；It enters step 8).