CN109492337B - Information flow tracking model generation method of programmable logic device - Google Patents
Information flow tracking model generation method of programmable logic device Download PDFInfo
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Abstract
The invention relates to a generation method of a base high-precision information flow tracking model, which is characterized in that programmable logic device codes are input according to work category classification, instantiated module names in the codes are identified, the module names are matched with module names in a netlist library corresponding to the programmable logic devices, if the module names are consistent, the codes are in a gate level, otherwise, the codes are in an RTL level, display flows in the RTL level are processed, all inputs are traversed, assignment statement output is calculated, and results are converted into a truth table; inputting an original truth table by using a gate-level information flow theory to generate a truth table of a full input-output information flow stain label; and converting the Carnot diagram simplification truth table into information flow tracking logic, processing the implicit flow in the RTL level layer, and realizing the information flow processing of the RTL level layer code. And processing the information flow of the gate level. And generating an information flow tracking model of the programmable logic device by classifying RTL level hierarchical codes and gate level hierarchical codes in the programmable logic device and respectively performing information flow tracking processing.
Description
Technical Field
The invention relates to the field of integrated circuit security detection, in particular to a method for generating an information flow tracking model of a programmable logic device.
Background
In programmable logic devices, there may be some security concerns including bugs left unintentionally by designers or hardware trojans maliciously implanted by attackers. The gate-level information flow technology is a technology capable of capturing all binary bit data flow in integrated circuit design, can effectively detect bugs or malicious codes in the design, most of the existing gate-level information flow tracking technologies are designed for ASIC (application specific integrated circuit), and the existing gate-level information flow technology for generating a programmable logic device information flow tracking model has the following defects:
the applicability is poor. The existing gate-level information flow technology uses Design Compiler synthesized netlist for ASIC Design, and only AND, OR, or and non-equal basic logic units are in the gate-level netlist. For the design of programmable logic devices, the combinational logic in the gate-level netlist is realized by a look-up table (LUT), so the prior art cannot be completely suitable for supporting the design of programmable logic devices such as xlnx, altera and the like.
The information flow accuracy is not high. Because the traditional gate-level information flow technology cannot process the cells such as LUT in the programmable logic device netlist, the cells can only be blacked for generating the information flow tracking model, and the generated information flow model has low accuracy.
Disclosure of Invention
The invention aims to provide a high-precision information flow tracking model generation method of a programmable logic device based on black-and-white box classification processing, which is used for solving the problems in the prior art.
The invention discloses a high-precision information flow tracking model generation method of a programmable logic device based on black and white box classification processing, which comprises the following steps: step 1: inputting a code to be tested; and 2, step: analyzing the type of the code to be tested line by line, matching the name of the instantiated module in the code to be tested with the name of the module in the netlist library corresponding to the programmable logic device, if the name of the instantiated module in the code to be tested is consistent with the name of the module in the netlist library corresponding to the programmable logic device, judging that the code to be tested is in a gate level, performing step 10, and if not, judging that the code to be tested is in an RTL level, and performing step 3; and step 3: judging the type of the code information flow to be detected, if the type is an implicit flow, performing the step 4, and if the type is an explicit flow, performing the step 6; and 4, step 4: converting condition branches in the implicit flow code to be tested into logic equivalent selector modules; and 5: replacing the selector module with a selector module with information flow tracing logic, wherein the selector module with the information flow tracing logic is a module with the information flow tracing logic and the selector logic, and going to step 9; and 6: generating a truth table for displaying the flow statement; and 7: converting a truth table of a display flow statement into a truth table of a stain label of a full input and output information flow; and 8: converting the truth table into a logic expression, and adding the logic expression into the original logic; and step 9: judging whether the processing of the code to be detected is completed or not, if not, returning to the step 3, otherwise, performing the step 17; step 10: selecting an information flow tracking library of a device corresponding to the gate level hierarchical code; step 11: selecting the next unit in the gate level hierarchical code, judging the type, executing the step 12 if the unit is a lookup table module, and otherwise, executing the step 15; step 12: generating a stored truth table according to the configuration parameters of the lookup table module; step 13: converting the stored truth table into a truth table of a full input and output information flow stain label; step 14: simplifying the truth table, converting the truth table into a logic expression, adding the converted logic expression into the original lookup table module, and performing the step 16; step 15: automatically replacing the selection unit with a corresponding logic unit in the selected information flow tracking library; step 16: judging whether the processing of the code to be detected is finished, if not, returning to the step 11, otherwise, performing the step 17; and step 17: and integrating the codes to be detected after information flow processing to generate the information flow tracking model of the programmable logic device.
According to an embodiment of the method for generating an information flow tracking model of a programmable logic device, in step 7, a truth table of a display flow statement is converted into a truth table of a full input/output information flow stain label according to a gate-level information flow theory.
According to an embodiment of the information flow tracking model generation method of the programmable logic device, in step 8, the truth table is simplified by using the carnot diagram principle and converted into the logic expression.
In an embodiment of the method for generating an information flow tracking model of a programmable logic device according to the present invention, in step 13, the truth table is converted into a truth table of a full-input-output information flow stain label according to a gate-level information flow theory.
In an embodiment of the information flow tracking model generation method for a programmable logic device according to the present invention, step 14: and converting the original simplified value table of the Carnot graph into a logic expression.
The invention provides a method for generating an information flow tracking model of a programmable logic device for mixed level processing.
Compared with other information flow tracking model generation methods, the method has the following advantages:
(1) The method is suitable for various programmable logic devices. The information flow tracing model generation method of the programmable logic device can select a corresponding information flow tracing library according to the programmable logic device corresponding to the netlist code, and is therefore suitable for various programmable logic devices such as XILINX and ALTERA.
(2) The information flow tracking accuracy is high. According to the information flow tracking model generation method of the programmable logic device, information flow processing is respectively carried out on RTL level layers and gate level layers in the programmable logic device, and LUT (look-up table) and other units in the gate level layers are accurately tracked according to the device model, so that the generated information flow tracking model is high in accuracy.
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FIG. 1 is a general schematic diagram of a method for generating an information flow tracking model of a programmable logic device according to the present invention;
fig. 2 is a flow chart of a method for generating an information flow tracking model of a programmable logic device according to the present invention.
Detailed Description
In order to make the objects, contents, and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.
Fig. 1 is a general schematic diagram of a method for generating an information flow tracking model of a programmable logic device according to the present invention, fig. 2 is a flowchart of the method for generating the information flow tracking model of the programmable logic device according to the present invention, and as shown in fig. 1 and fig. 2, the method for generating the information flow tracking model of the programmable logic device according to the present invention includes:
as shown in fig. 1, a method for generating an information flow tracking model of a programmable logic device includes the following steps:
step 1: inputting a code v/vhd to be tested;
step 2: analyzing the type of the code to be tested, matching the name of the instantiated module in the code with the name of the module in the netlist library corresponding to the programmable logic device, if the name of the instantiated module in the code is consistent with the name of the module in the netlist library corresponding to the programmable logic device, performing the step 10, otherwise, performing the step 3;
and step 3: selecting the next row of codes, judging the type of the information flow, if the information flow is an implicit flow, performing the step 4, and if the information flow is an explicit flow, performing the step 6;
and 4, step 4: the selector module is a combinational logic circuit which selects a specified one from a group of input signals according to given input signals and sends the selected one to an output end, and the selector module is equivalent to the conditional branch, but is easier to realize information flow processing;
and 5: replacing the selector module with a selector module with information flow tracing logic, wherein the selector module with the information flow tracing logic is a module with the information flow tracing logic and the selector logic, and going to step 9;
and 6: generating a truth table for displaying the flow statement;
and 7: converting a truth table of a display flow statement into a truth table of a full input and output information flow stain label according to a gate-level information flow theory;
and 8: simplifying the truth table by using a Carnot diagram principle, converting the truth table into a logic expression, and adding the logic into the original logic;
and step 9: judging whether the processing of the code to be detected is finished, if not, returning to the step 3, otherwise, performing the step 17;
step 10: manually selecting an information flow tracking library of a device corresponding to the gate level hierarchical code, wherein the information flow tracking library is a set of minimum gate level units generated according to a gate level information flow theory;
step 11: selecting the next unit in the gate level hierarchical code, judging the type of the next unit, if the next unit is an LUT module, executing the step 12, and if the next unit is not the LUT module, executing the step 15;
step 12: generating a stored truth table according to the configuration parameters of the LUT module;
step 13: converting the truth table into a truth table of a full input and output information flow stain label according to a gate level information flow theory;
step 14: converting the original carnot diagram simplification value table into a logic expression, adding the logic into the original LUT module, and performing step 16;
step 15: automatically replacing the selection unit with a corresponding logic unit in the selected information flow tracking library;
step 16: judging whether the processing of the code to be detected is finished, if not, returning to the step 11, otherwise, performing the step 17;
and step 17: and integrating the codes to be detected after information flow processing to generate the information flow tracking model of the programmable logic device.
As shown in fig. 1, the method for generating a base high-precision information flow tracking model according to the present invention classifies according to the working categories, and includes: the method comprises three parts of (1) classification of programmable logic device design codes, (2) RTL level information flow processing and (3) gate level information flow processing.
(1) Classifying the programmable logic device design code includes:
the main role of code classification is to classify various types of codes in programmable logic device design into two types, namely RTL level hierarchy and gate level hierarchy. Programmable logic device designs typically include code from different sources: one is handwritten code, which is written manually by a designer, belonging to the RTL level hierarchy (register transfer level). The other is third party IP core code, which is provided by a third party vendor, and these IP cores are usually gate-level netlists in order to protect property rights. The following is a code classification processing method: first, a programmable logic device code is input. Then, the module name instantiated in the code is identified. And finally, matching the module name with the module name in the netlist library corresponding to the programmable logic device, wherein if the module name is consistent with the module name in the netlist library, the code is in a gate level, and otherwise, the code is in an RTL level.
(2) The RTL level hierarchical information flow processing comprises the following steps:
the RTL level hierarchical information flow processing is used for designing RTL level hierarchical code for the programmable logic device and adding information flow tracking logic.
First, the display stream in the RTL level hierarchy is processed. Display flows are usually accompanied by direct movement of data, common explicit flows are assignment statements. The specific method comprises the following steps:
traversing all inputs, calculating assignment statement output, and converting a result into a truth table;
inputting an original truth table by using a gate-level information flow theory to generate a truth table of a full input-output information flow stain label;
the carnot diagram simplification truth table is used for converting into information flow tracking logic.
Then, processing the implicit flow in the RTL level hierarchy to realize the information flow processing of the RTL level hierarchy code. Implicit flows stem from the uncertain behavior of the system, such as conditional branches, conditional loops. The specific method comprises the following steps:
converting the conditional statement into a logically equivalent selector;
the selector module is replaced with a selector module with information flow tracing logic.
(3) The gate level hierarchical information flow processing comprises the following steps:
most of the IP cores in the design of the programmable logic device are gate-level netlist codes. The gate level hierarchical code information flow processing is used for adding information flow tracking logic to gate level hierarchical codes in the programmable logic device design.
Firstly, inputting a gate-level netlist code, manually selecting an information flow tracking library of a device corresponding to the netlist code, wherein the information flow tracking library is a set of minimum gate-level units generated according to a gate-level information flow theory, and the information flow tracking library can be repeatedly used after being established.
Then, information flow tracking logic of a look-up table (LUT) is generated. Besides basic logic units, the netlist is also provided with a lookup table (LUT) module, information flow tracing logic of the LUT module is generated according to parameters of the LUT, and the tracing logic is added into the LUT module. The combinational logic in the programmable logic device is realized by a truth table in an LUT memory, and the LUT information flow tracking logic is generated by the following method:
1) The logic of the LUT is determined by the configuration parameters, so a truth table in the LUT memory under full input is generated according to the parameters of the LUT;
2) Inputting an original truth table by using a gate-level information flow theory to generate a truth table of a full input-output information flow stain label;
3) The carnot diagram is used to simplify the truth table, translate to information flow tracking logic, and add the logic to the original LUT block.
And finally, replacing other logic units (such as IBUF, FDCP and the like) in the netlist with corresponding logic units in the selected information flow tracking library to realize the information flow processing of the gate level.
Compared with other information flow tracking model generation methods, the information flow tracking model generation method of the programmable logic device has the following advantages that:
(1) The method is suitable for various programmable logic devices. The information flow tracing model generation method of the programmable logic device can select a corresponding information flow tracing library according to the programmable logic device corresponding to the netlist code, and is suitable for various programmable logic devices such as XILINX, ALTERA and the like.
(2) The information flow tracking accuracy is high. The information flow tracking model generation method of the programmable logic device respectively processes information flows of a white box and a black box in the programmable logic device, and accurately tracks information flows of an LUT (look-up table) and other units in the black box according to the model of the device, so that the generated information flow tracking model is high in accuracy.
The method has the following advantages:
(1) The method is suitable for various programmable logic devices. The information flow tracing model generation method of the programmable logic device can select a corresponding information flow tracing library according to the programmable logic device corresponding to the netlist code, and is suitable for various programmable logic devices such as XILINX, ALTERA and the like.
(2) The information flow tracking accuracy is high. The information flow tracking model generation method of the programmable logic device respectively processes information flow of RTL level layers and gate level layers in the programmable logic device, and accurately tracks information flow of LUTs and other units in the gate level layers according to the device model, so that the generated information flow tracking model is high in accuracy.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (5)
1. A high-precision information flow tracking model generation method of a programmable logic device based on black-and-white box classification processing is characterized by comprising the following steps:
step 1: inputting a code to be tested;
step 2: analyzing the type of the code to be tested line by line, matching the name of the instantiated module in the code to be tested with the name of the module in the netlist library corresponding to the programmable logic device, if the name of the instantiated module in the code to be tested is consistent with the name of the module in the netlist library corresponding to the programmable logic device, judging that the code to be tested is in a gate level, performing step 10, and if not, judging that the code to be tested is in an RTL level, and performing step 3;
and step 3: judging the type of the code information flow to be detected, if the type is an implicit flow, performing the step 4, and if the type is an explicit flow, performing the step 6;
and 4, step 4: converting condition branches in the implicit flow code to be tested into a logically equivalent selector module;
and 5: replacing the selector module with a selector module with information flow tracing logic, wherein the selector module with the information flow tracing logic is a module with the information flow tracing logic and the selector logic, and going to step 9;
step 6: generating a truth table for displaying the flow statement;
and 7: converting a truth table of a display flow statement into a truth table of a full input and output information flow stain label;
and 8: converting the truth table into a logic expression, and adding the logic expression into the original logic;
and step 9: judging whether the processing of the code to be detected is finished, if not, returning to the step 3, otherwise, performing the step 17;
step 10: selecting an information flow tracking library of a device corresponding to the gate level hierarchical code;
step 11: selecting the next unit in the gate level hierarchical code, judging the type, executing the step 12 if the unit is a lookup table module, and otherwise, executing the step 15;
step 12: generating a stored truth table according to the configuration parameters of the lookup table module;
step 13: converting the stored truth table into a truth table of a full input and output information flow stain label;
step 14: simplifying the truth table, converting the truth table into a logic expression, adding the converted logic expression into the original lookup table module, and performing the step 16;
step 15: automatically replacing the selection unit with a corresponding logic unit in the selected information flow tracking library;
step 16: judging whether the processing of the code to be detected is finished, if not, returning to the step 11, otherwise, performing the step 17;
and step 17: and integrating the codes to be detected after information flow processing to generate a programmable logic device information flow tracking model.
2. The method for generating a high-precision information flow tracking model of a programmable logic device based on black-and-white box classification processing according to claim 1, wherein the step 7: and converting the truth table of the display flow statement into the truth table of the stain label of the full input and output information flow according to a gate-level information flow theory.
3. The method for generating a high-precision information flow tracking model of a programmable logic device based on black-and-white box classification processing according to claim 1, wherein the step 8: simplifying the truth table by using the Kano diagram principle, converting the truth table into a logic expression, and adding the logic into the original logic.
4. The method for generating a high-precision information flow tracking model of a programmable logic device based on black-and-white box classification processing according to claim 1, wherein the step 13: and converting the truth table into a truth table of the full input and output information flow stain labels according to a gate-level information flow theory.
5. The method for generating a high-precision information flow tracking model of a programmable logic device based on black-and-white box classification processing according to claim 1, wherein the step 14: and converting the original simplified value table of the Carnot graph into a logic expression.
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| CN111221690B (en) * | 2019-12-20 | 2023-09-22 | 北京天下行知科技有限公司 | Model determination method and device for integrated circuit design and terminal |
| CN111427799A (en) * | 2020-04-14 | 2020-07-17 | 北京计算机技术及应用研究所 | IP core security path selection and cut-off method |
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