CN110323282A - It is a kind of based on quasi-zero dimension contact two-dimensional film bury grid field effect transistor - Google Patents
It is a kind of based on quasi-zero dimension contact two-dimensional film bury grid field effect transistor Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
- H10K10/80—Constructional details
- H10K10/82—Electrodes
- H10K10/84—Ohmic electrodes, e.g. source or drain electrodes
Abstract
The invention proposes a kind of two-dimensional films based on quasi-zero dimension contact to bury grid field effect transistor, belong to FET device field, transistor of the present invention includes the substrate stacked gradually, buried gate electrode, buries gate dielectric layer and two-dimensional film, the two-dimensional film side is sequentially laminated with quasi-zero dimension structure forming layer and the first electrode as quasi-zero dimension source metal, which is laminated with the second electrode of ground connection；Quasi-zero dimension structure forming layer is made up of insulating material of graphical and deposition process, for forming filamentous conductive path in the quasi-zero dimension structural generation layer by the metal electromigration characteristic of first electrode, to form quasi-zero dimension contact between first electrode and two-dimensional film.Field effect transistor may be implemented in the present invention has extremely low contact resistance, very high current on-off ratio under lower gate control voltage；The transistor also for 5nm following characteristics size provides solution simultaneously.
Description
Technical field
The present invention relates to FET device fields more particularly to a kind of two-dimensional film based on quasi-zero dimension contact to bury
Grid field effect transistor.
Background technique
With the development of Moore's Law, the characteristic size of transistor is smaller and smaller in integrated circuit, and circuit scale is increasingly
Greatly.However as the diminution of size, the short-channel effect of si-substrate integrated circuit is also just more obvious, results even in circuit mistake
Effect.And two-dimensional film has the characteristic for overcoming short-channel effect, replacement silica-base material becomes integrated circuit mainstay material with huge
Big potentiality.At the same time, circuit scale, which constantly expands, proposes more the driving capability and current on/off ratio of single transistor
High requirement, however it is existing for how to reduce transistor, the especially contact resistance of two-dimensional material transistor, increase transistor
Current on/off ratio to obtain the emphasis that higher driving capability is still research.
Contact between traditional transistor electrodes and two-dimensional material is prepared using the method for sputtering and electron beam evaporation,
Although this method possesses simple process, is easy to the advantages that large area preparation, but as caused by sputtering and electron beam evaporation
Target metal nuclear energy is high, is very easy to cause the surface damage of two-dimensional material, so that more surface energy levels are introduced, so that connecing
Touching potential barrier is got higher, and transistor performance is deteriorated.
In order to improve the driving capability of two-dimensional material transistor, contact resistance is reduced, currently used method includes electrode
Transfer method and quasi- one-dimensional contact method.
Electrode shifts (perfect face contact) method, is to glue glutinous two dimensional crystal repeatedly in the way of adhesive tape etc. and utilize organic matter
Two-dimensional material is attached on organic matter by (such as PDMS), and using microscope alignment, fixed point is transferred to the crystal for having prepared and having finished
On pipe electrode, to complete the preparation of two dimensional crystal pipe.Electrodeposition can be greatly reduced in the process for two dimension using this method
The damage of material reduces electrode-two-dimensional material contact surface energy level, to reduce contact berrier, improves transistor on-state current.
But there is the disadvantages of being not easy to prepare complicated circuit and being difficult to traditional silicon substrate process compatible in this method.
Quasi- one-dimensional contact (line contact) method is using materials such as EDGE CONTACT and carbon nanotubes, so that contact formation is quasi- one-dimensional
Contact, the experimental verification contact can promote contact performance.Disadvantage is however that preparation process is complicated, it is difficult to which integrated and preparation is multiple
Strays road.
At the same time, it is limited due to silicon-based transistor based on hot carrier emission principle, there are subthreshold swing 60mV/
The theoretical limit of dec, but novel super steep subthreshold swing device can greatly reduce Leakage Current, reduce quiescent dissipation, therefore
It has received widespread attention, current super steep subthreshold swing device is broadly divided into three classes: tunneling transistor, negative capacitance transistor,
Receive electrodynamic relay.
Tunneling transistor is mainly using the semiconductor material of phase contra-doping on substrate to complete lower subthreshold swing.
The working principle of tunneling transistor mainly passes through control grid voltage, to complete the variation of intrinsic region energy band, and then control because
Quantum tunneling effect and the electric current that generates and obtain low subthreshold swing.
Negative capacitance transistor mainly utilizes ferroelectric material to complete lower subthreshold swing on grid.Negative capacitance crystal
The working principle of pipe is mainly to utilize the negative capacitance characteristic of ferroelectric material, to complete the amplification for grid voltage, with reality
Existing low subthreshold swing.
Electrodynamic relay of receiving mainly utilizes the relay of transverse actuating to complete lower subthreshold swing.Receive it is electronic after
The working principle of electric appliance is mainly using the electrostatic force between overarm and drain electrode, to complete lifting and closing for device, to realize
Low subthreshold swing.
From the above statement it can be shown that reducing the dimension of contact, be conducive to the performance for promoting transistor.But currently, no matter
It is prevailing technology, or is in scientific research, electrode is all unable to reach the contact of quasi-zero dimension with channel material (point connects in transistor
Touching).How transistor quasi-zero dimension contact under is realized to improve the performance of two-dimensional material transistor, and improve two-dimentional material simultaneously
The driving current performance for expecting transistor, becomes urgent problem to be solved.
Summary of the invention
In view of the above-mentioned problems existing in the prior art, the present invention provides a kind of two-dimensional films based on quasi-zero dimension contact to bury
Grid field effect transistor；The present invention is analyzed using contact resistance transmission line theory and proposes a kind of completely new quasi-zero dimension contact side
Method can further decrease transistor contacts resistance, improve the ability of transistor driving back-end circuit, substantially reduce subthreshold value pendulum
Width has high on-off ratio.
To achieve the goals above, the present invention adopts the following technical scheme:
A kind of two-dimensional film based on quasi-zero dimension contact proposed by the present invention buries grid field effect transistor, which is characterized in that
Include:
The substrate that stacks gradually, buries gate dielectric layer and two-dimensional film at buried gate electrode, and the two-dimensional film side stacks gradually
There are quasi-zero dimension structure forming layer and the first electrode as quasi-zero dimension source metal, the two-dimensional film other side is laminated with ground connection
Second electrode；Wherein,
The buried gate electrode is made of metal, conductive non-metals or flexible electrode material, for conducting the field-effect
The voltage control signal of transistor；
It is described to bury gate dielectric layer, be made of metal oxide, two-dimentional insulator or flexible insulator, be used to form electric field,
And it is used for being isolated between the buried gate electrode and the channel formed in the two-dimensional film；
The two-dimensional film, for the two-dimensional film with characteristic of semiconductor, by the two-dimensional film to the electricity of its interior raceway groove
Resistance is regulated and controled, and then realizes the regulation to the switch with field-effect transistors characteristic；
The quasi-zero dimension structure forming layer is made up of lithographic images and deposition process using insulating material, is used for
Filamentous conductive path is formed in the quasi-zero dimension structural generation layer by the metal electromigration characteristic of the first electrode,
To form quasi-zero dimension contact between the first electrode and two-dimensional film.
Further, the quasi-zero dimension structure is cambial with a thickness of 0.7nm~300nm.
Further, the two-dimensional film uses two-dimentional Transition-metal dichalcogenide film, dirac two-dimensional film, has
Machine two-dimensional film or flexible two-dimensional film.
Feature of the present invention and the utility model has the advantages that
The present invention proposes a completely new solution for the contact problems of field effect transistor.Its principle is to pass through
Using electrode metal electromigration characteristic under strong electric field, so that forming a conduction between channel in source-drain electrode and two-dimensional film
Filament access, the conductive filament channel are made of metallic atom.Since conductive filament possesses minimum cross-sectional area,
Horizontal direction thinks zero-dimension structural subject to the metallic conduction filament structure formed between source-drain electrode and channel, so that standard zero
Dimension contact is formed between source-drain electrode and channel.By the transmission line model using contact resistance, discovery subtracts with contact dimension
Few, conducting carriers scatter reduction in channel layer, are conducive to carrier and longitudinally transmit, greatly improve contact performance and crystalline substance
The size of body pipe on-state current.In addition common electrode material is in deposition process, due to using the works such as sputtering, electron beam evaporation
Skill, electrode material energy is higher, can cause to damage to two-dimensional material, to introduce more surface energy levels, contact performance is deteriorated.And
There is the cambial isolation of quasi-zero dimension structure using quasi-zero dimension structure, between electrode material and two-dimensional material, has protection to two-dimensional material
Effect, to reduce the introducing of surface energy level, on the other hand to reach the minimum theoretical limit of Schottky contact barrier.To
Further improve the on-state current and rear end driving capability of transistor.For quasi-zero dimension metallic conduction filament structure, keep
Time is long, can be more than 1350 hours in embodiment, therefore the two-dimensional film of the invention based on quasi-zero dimension contact buries grid field effect
Answer transistor that there is good robustness.In addition, two-dimensional material with its ultra-thin thickness, possesses and breaks through existing silicon-based transistor ruler
The limitation of very little diminution maintains Moore's Law further to develop, can be applied to characteristic size 5nm new chip technique below.It buries
The application of grid structure, further controls electric leakage of the grid, reduces the operating voltage of transistor, so that the two dimension based on quasi-zero dimension contact
Film buries grid field effect transistor and can run under the conditions of low-voltage, low-power consumption.The preparation process of the device and traditional silicon substrate
Process compatible, can be integrated with silicon-based electronic circuits.Two-dimensional film based on quasi-zero dimension contact buries grid field effect transistor and solves silicon
The driving problems of single transistor under the diminution of base circuit size and high integration, in large-scale analog circuit and Digital Logical Circuits
Have broad application prospects and space.
Detailed description of the invention
Fig. 1 is the main view that the two-dimensional film contacted in the embodiment of the present invention based on quasi-zero dimension buries grid field effect transistor structure
Figure；
Fig. 2 is the right view that the two-dimensional film contacted in the embodiment of the present invention based on quasi-zero dimension buries grid field effect transistor structure
Figure；
Fig. 3 is that the two-dimensional film based on quasi-zero dimension contact in the embodiment of the present invention buries grid field effect transistor preparation method stream
Cheng Tu；
Fig. 4 is that the two-dimensional film based on quasi-zero dimension contact in the embodiment of the present invention buries grid field effect transistor driving current spy
Property with conventional three-dimensional contact driving current Property comparison schematic diagram；Wherein, (a) is the performance schematic diagram of the embodiment of the present invention, (b)
It is the performance schematic diagram of conventional three-dimensional contact.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without creative efforts, shall fall within the protection scope of the present invention.
A kind of two-dimensional film based on quasi-zero dimension contact provided in an embodiment of the present invention buries grid field effect transistor, structure
It is the main view and right view of the transistor arrangement respectively, including substrate 111, the buried gate electrode stacked gradually referring to Fig. 1, Fig. 2
101, gate dielectric layer 102 and two-dimensional film 103 are buried, 103 side of two-dimensional film stacks gradually quasi-zero dimension structure forming layer 104 and makees
For quasi-zero dimension source metal (the quasi-zero dimension source metal, which refers to, to form the metal source of quasi-zero dimension structure, generally metal electrode)
First electrode 105, the other side are laminated with the second electrode 106 of ground connection；It buried gate electrode 101 and buries gate dielectric layer 102 and collectively forms
Bury coral structure.Wherein, it buries coral structure to be made by graphical and deposition process, buried gate electrode 101 is for conducting this transistor
Voltage control signal, burying gate dielectric layer 102, (area for burying gate dielectric layer covering buried gate electrode depends on burying grid Jie completely or partially
The preparation method of matter layer, such as conventional atomic layer deposition method, using being completely covered；The side such as sputtered again using first photoetching
Gate dielectric layer is buried in method preparation, covers using part；No matter above-mentioned which kind of method is used, it is then necessary for channel corresponding part
It is completely covered) covering buried gate electrode 101, it is used to form electric field and is used for buried gate electrode 101 and is formed in two-dimensional film 103
Channel between isolation；Quasi-zero dimension structure forming layer 104 is (described by photolithography patterning and deposition process by insulating material
Deposition process includes conventional magnetron sputtering, electron beam evaporation, chemical vapor deposition and physical vapor deposition methods) it is made, lead to
Cross the application external electrical field (10 in first electrode 1056V/m~109V/m), so that the metallic atom of first electrode 105 is moved in electricity
Under the action of moving, filamentous conductive path is formed in quasi-zero dimension structural generation layer 104, thus in first electrode 105 and two
Formation quasi-zero dimension contacts between tieing up film 103, so as to improve the galvanic contact performance between first electrode and two-dimensional film interior raceway groove.
The specific implementation and function of each synthesizer part are respectively described below in the embodiment of the present invention:
The substrate 111, using insulating materials, (the present embodiment selects thermally grown 300nm SiO on silicon substrate2Crystalline substance afterwards
Circle) it is made, for providing physical support and electric isolation for entire transistor, 111 upper surface of substrate is connected with buried gate electrode 101
It connects；
The buried gate electrode 101, upper surface and buries gate dielectric layer 102 and (in the present embodiment, buries 102 part of gate dielectric layer and cover
Lid buried gate electrode 101；In another embodiment, bury gate dielectric layer 102 and buried gate electrode 101 be completely covered) it is connected, by burying grid
The voltage control signal of this transistor of the conduction of electrode 101；The material that buried gate electrode 101 is made includes metal, conductive non-metals (example
Highly-doped p-type and n-type silicon or germanium semiconductor such as can be used) and flexible electrode material (the present embodiment uses Pt)；Buried gate electrode
101 width is 100nm~100um, with a thickness of 10nm~50nm.
It is described to bury gate dielectric layer 102, this bury the upper and lower surface of gate dielectric layer 102 respectively with two-dimensional film 103 and bury grid electricity
Pole 101 is connected, for the isolation between 103 interior raceway groove of grid and two-dimensional film；Being made and burying the material of gate dielectric layer 102 includes gold
Belong to any one in oxide, two-dimentional insulator and flexible insulator, for the present embodiment, to use atomic layer deposition
15nm thickness hafnium oxide material.Grid-control scanning voltage, optimization gate dielectric layer electric leakage situation can be reduced using buried gate electrode 101.
The two-dimensional film 103, lower surface are connect with gate dielectric layer 102 is buried, upper surface respectively with second electrode 106 and standard
Zero-dimension structural forming layer 104 connects, and does not contact between second electrode 106 and quasi-zero dimension structure forming layer 104, in the two-dimensional film
Interior formation fieldistor channel regulates and controls its interior raceway groove resistance by two-dimensional film, and then realizes to this field-effect
Any two-dimensional film with characteristic of semiconductor can be selected in the regulation of transistor switch characteristic, 103 material of two-dimensional film, such as
Using in two-dimentional Transition-metal dichalcogenide film, dirac two-dimensional film, organic two-dimensional film or flexible two-dimensional film
Any one, thickness range is in 0.33nm-50nm, for the present embodiment, thick for the 2nm with higher carrier mobility
Molybdenum disulfide.
Quasi-zero dimension structure forming layer 104 is core of the invention, the upper and lower surface difference of the quasi-zero dimension structure forming layer 104
It is connected with first electrode 105 and two-dimensional film 103, the material for constituting quasi-zero dimension structure forming layer 104 is generally insulator material
Material is capable of forming the material of conductive filament, quasi-zero dimension structure shape including metal oxide and other metallic atoms inside it
Stratification 104 is 0.7nm~300nm.For the present embodiment, for use atomic layer deposition 8nm thickness hafnium oxide material.It is logical
It crosses using in strong electrical field (106V/m~109V/m the metal electromigration characteristic of first electrode 105 under), so that in source-drain electrode and two dimension
A conductive filament access is formed between channel in film 103, which is made of metallic atom.Due to conduction
Filament possesses nm grades evenThe cross-sectional area of grade, thus think in the horizontal direction with source-drain electrode and two-dimensional film interior raceway groove it
Between zero-dimension structural subject to the metallic conduction filament structure that is formed so that quasi-zero dimension contact is in source-drain electrode and two-dimensional film septal fossula
It is formed between road.By the transmission line model using contact resistance, discovery is with the reduction of contact dimension, and conducting carriers are in ditch
Scattering is reduced in channel layer, is conducive to carrier and is longitudinally transmitted, greatly improves the size of contact performance and transistor on-state current.
On the other hand, using quasi-zero dimension structure, have between first electrode 105 and two-dimensional film 103 quasi-zero dimension structure forming layer 104 every
From, there is protective effect to two-dimensional film 103, thus the introducing of reduction surface energy level on the other hand, to reach schottky junctions
The minimum theoretical limit for touching potential barrier, to further improve the on-state current and rear end driving capability of this transistor.
The first electrode 105, the material for constituting the first electrode 105 includes that aluminium, silver, copper etc. can generate electromigration
Material, for the present embodiment, for the Ag of sputtering.
The second electrode 106, the material for constituting the second electrode 106 includes metal and other conductive non-metals, doping
Semiconductor, flexible electrode material combine for the present embodiment for the Pt/Ti of sputtering.
It is that the two-dimensional film based on quasi-zero dimension contact in the various embodiments described above of the present invention buries gate field-effect crystal referring to Fig. 3
The preparation method flow chart of pipe, method includes the following steps:
S201: being prepared buried gate electrode 101 and buried gate dielectric layer 102 on substrate 111 using graphical and deposition process, right
For the present embodiment, buried gate electrode 101 is completed using the corresponding manufacture craft such as mask exposure or electron beam exposure technique
Preparation, the preparation for burying gate dielectric layer 102 is completed using the mode of atomic layer deposition.
S202: two-dimensional material is transferred to and buries gate dielectric layer 102 using dry method (mechanical stripping method) or wet process transfer method
On, and pass through graphical, two-dimensional film 103 of the lithographic method preparation with conducting channel, the patterned mode are as follows: mask
The corresponding manufacture craft such as version exposure or electron beam exposure technique, the lithographic method are that plasma dry etch or chemistry are anti-
Answer etch.
S203: the corresponding manufacture craft such as mask exposure or electron beam exposure technique is used, is made in two-dimensional film 103
Standby second electrode 106.
S204: quasi-zero dimension knot is prepared in two-dimensional film 103 in the way of chemical vapor deposition or physical vapour deposition (PVD)
Configuration stratification 104.And by graphical, lithographic method determines that quasi-zero dimension structure forming layer 104 is specific in two-dimensional film 103
Position, the patterned mode are as follows: the corresponding manufacture craft such as mask exposure or electron beam exposure technique, the etching side
Method is plasma dry etch or chemical reaction etch.
S205: using with S201 method, first electrode 105 is prepared on quasi-zero dimension structure forming layer 104.
S206: gate electrode exit 110 is prepared on buried gate electrode 101 using with S201 method.
Validation verification of the embodiment of the present invention:
In order to verify the effect of the embodiment of the present invention, the first electrode 105 in transistor shown in Fig. 1 is passed through into conducting wire and one
The positive terminal of a source and drain signal input apparatus connects, and the negative pole end of the source and drain signal input apparatus passes through conducting wire and second electrode
106 connections, on buried gate electrode 101 gate electrode exit 110 being arranged, (material that buried gate electrode exit 110 is made includes
Metal, conductive non-metals (such as highly-doped p-type and n-type silicon or germanium semiconductor can be used), flexible electrode material etc., are made and bury grid
The material of electrode leads to client 110 can be identical as buried gate electrode 101, can also be different from buried gate electrode 101, and the present embodiment uses
Pt metal), which accesses second electrode 106 and the input of source and drain signal by gate control signal input unit
The common end of device negative pole end.
It referring to fig. 4, is that the two-dimensional film contacted in the embodiment of the present invention based on quasi-zero dimension buries grid field effect transistor electric current
Switching characteristic and on-state current are compared with the schematic diagram that Three-Dimensional contact compares, wherein (a) is result figure of the embodiment of the present invention, is (b) existing
Some Three-Dimensional contact result figures；Drain current reference axis 301, grid voltage scanning 302, electric leakage of the grid reference axis 303.
When drain voltage is 6V, when gated sweep is from -2V to 11V, channel current transmission curve 304 and grid leakage current
305 is available with the variation of grid voltage: the channel current switch for burying grid two-dimensional film transistor based on quasi-zero dimension contact
Than in 2.6e9；And buried grid structure uses so that gated sweep voltage range becomes smaller, and electric leakage of the grid is low, and device performance is good.Phase
It is compared to the grid leakage current 307 of the two dimensional crystal pipe of common Three-Dimensional contact, quasi-zero dimension contact can make ON state in the present invention
Electric current improves nearly 50 times, greatly reduces the contact resistance of device, improves transistor current driving capability.
Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
Present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: it still may be used
To modify the technical solutions described in the foregoing embodiments or equivalent replacement of some of the technical features；
And these are modified or replaceed, technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution spirit and
Range.
Claims (9)
1. a kind of two-dimensional film based on quasi-zero dimension contact buries grid field effect transistor characterized by comprising
The substrate that stacks gradually, buries gate dielectric layer and two-dimensional film at buried gate electrode, and the two-dimensional film side is sequentially laminated with standard
Zero-dimension structural forming layer and first electrode as quasi-zero dimension source metal, the two-dimensional film other side is laminated with the second of ground connection
Electrode；Wherein,
The buried gate electrode is made of metal, conductive non-metals or flexible electrode material, for conducting the field effect transistor
The voltage control signal of pipe；
It is described to bury gate dielectric layer, it is made of metal oxide, two-dimentional insulator or flexible insulator, is used to form electric field, is used in combination
Being isolated between the buried gate electrode and the channel formed in the two-dimensional film；
The two-dimensional film, for the two-dimensional film with characteristic of semiconductor, by the two-dimensional film to the resistance of its interior raceway groove into
Row regulation, and then realize the regulation to the switch with field-effect transistors characteristic；
The quasi-zero dimension structure forming layer is made up, for passing through of lithographic images and deposition process using insulating material
The metal electromigration characteristic of the first electrode forms filamentous conductive path in the quasi-zero dimension structural generation layer, thus
Quasi-zero dimension contact is formed between the first electrode and two-dimensional film.
2. field effect transistor according to claim 1, which is characterized in that the quasi-zero dimension structure it is cambial with a thickness of
0.7nm~300nm.
3. field effect transistor according to claim 1, which is characterized in that prepare the quasi-zero dimension structure forming layer and adopted
Deposition process includes magnetron sputtering, electron beam evaporation, chemical vapor deposition and physical vapor deposition methods.
4. field effect transistor according to claim 1, which is characterized in that the two-dimensional film is using two-dimentional transition metal
Chalcogenide film, dirac two-dimensional film, organic two-dimensional film or flexible two-dimensional film.
5. field effect transistor according to claim 1, which is characterized in that the two-dimensional film with a thickness of 0.33nm-
50nm。
6. field effect transistor according to claim 1, which is characterized in that the first electrode, use can generate electricity
The material migrated is made.
7. field effect transistor according to claim 6, which is characterized in that the first electrode uses aluminium, silver or copper
?.
8. field effect transistor according to claim 1, which is characterized in that the second electrode, it is non-using metal, conduction
Metal or flexible electrode material are made.
9. field effect transistor according to claim 1, which is characterized in that the substrate, which is adopted, to be made from an insulative material, and is used
In providing physical support and electric isolation for entire field effect transistor.
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