CN110322838B - Time sequence control method of AMOLED time sequence control circuit - Google Patents
Time sequence control method of AMOLED time sequence control circuit Download PDFInfo
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- CN110322838B CN110322838B CN201810267213.9A CN201810267213A CN110322838B CN 110322838 B CN110322838 B CN 110322838B CN 201810267213 A CN201810267213 A CN 201810267213A CN 110322838 B CN110322838 B CN 110322838B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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Abstract
The invention relates to the technical field of display, and discloses a time sequence control method of an AMOLED time sequence control circuit, which comprises an initialization stage: the power voltage is in a low potential state, the data signal wire is in a turn-off state or a low potential state, so that no current passes through the organic light emitting diode, and the organic light emitting diode does not emit light; and (3) adjusting: the second thin film transistor is turned on; a data writing stage: the second node writes in the voltage provided by the data signal line, and the second thin film transistor is closed; a maintaining stage: the second node holds the voltage provided by the data signal line written in the data writing stage; a driving stage: the second thin film transistor, the fourth thin film transistor and the fifth thin film transistor are turned on, and the organic light emitting diode emits light. In the time sequence control method, the brightness of the organic light emitting diode is controlled by adjusting the high and low levels of the power supply voltage, and the delay time is reduced and the adjusting effect of the organic light emitting diode is improved by controlling the high and low levels of the power supply voltage.
Description
Technical Field
The invention relates to the technical field of display, in particular to a time sequence control method of an AMOLED time sequence control circuit.
Background
As shown in fig. 1, the conventional AMOLED timing control circuit has an AMOLED pixel driving circuit with a 7T1C structure, that is, a structure of seven tfts plus one capacitor, and includes a first tft T10, a second tft T20, a third tft T30, a fourth tft T40, a fifth tft T50, a sixth tft T60, a seventh tft T70, and a capacitor C10, wherein a gate of the first tft T10 is electrically connected to a second scan control signal line S2, a first end of the first tft T10 is electrically connected to a DATA signal line DATA, and a second end of the first tft T20 is electrically connected to a first end of the second tft T20 and a first end of the fourth tft T40 via a first node N10; a gate of the second thin film transistor T20 is electrically connected to the second node N20, a first terminal is electrically connected to the first node N10, and a second terminal is electrically connected to the third node N30; a gate of the third tft T30 is electrically connected to the second scan control signal line S2, a first terminal of the third tft T30 is electrically connected to the third node N30, and a second terminal of the third tft T30 is electrically connected to the second node N20 and the first terminal of the sixth tft T60; a gate of the fourth thin film transistor T40 is electrically connected to the light emitting signal line En, a first terminal of the fourth thin film transistor T40 is electrically connected to the first node N10, and a second terminal of the fourth thin film transistor T40 is electrically connected to the power voltage ELVDD; a gate of the fifth thin film transistor T50 is electrically connected to the light emitting signal line En, a first terminal of the fifth thin film transistor T50 is electrically connected to the third node N30, and a second terminal of the fifth thin film transistor T50 is electrically connected to the anode of the organic light emitting diode D10 and the second terminal of the seventh thin film transistor T70; a gate of the sixth thin film transistor T60 is electrically connected to the first scan control signal line S1, a first end of the sixth thin film transistor T60 is electrically connected to the second end of the third thin film transistor T30, and a second end of the sixth thin film transistor T60 is electrically connected to the first end of the seventh thin film transistor T70 and the reference voltage signal line VINT; a gate of the seventh thin film transistor T70 is connected to the second scan control signal line S2, a first end of the seventh thin film transistor T70 is electrically connected to the second end of the sixth thin film transistor T60 and the reference voltage signal line VINT, and a second end of the seventh thin film transistor T70 is electrically connected to the second end of the fifth thin film transistor T50 and the anode of the organic light emitting diode D10; a first end of the capacitor C10 is electrically connected to the second node N20, and the other end is connected to the power voltage ELVDD; the anode of the organic light emitting diode D10 is electrically connected to the second terminal of the fifth tft T50 and the second terminal of the seventh tft T70, and the cathode is grounded.
In the AMOLED timing control circuit, the brightness of the organic light emitting diode is adjusted by controlling the power on/off of the power supply voltage, but the adjustment effect of the organic light emitting diode is poor due to the delay time existing in the power on/off process of the power supply voltage.
Disclosure of Invention
The invention provides a time sequence control method of an AMOLED time sequence control circuit, which realizes the control of brightness of an organic light emitting diode by adjusting the high and low levels of a power supply voltage.
To achieve the above object, the present invention provides a timing control method for an AMOLED timing control circuit, including:
entering an initialization stage, wherein the power voltage is in a low potential state, the light-emitting signal line provides a low potential, the fourth thin film transistor and the fifth thin film transistor are turned on, the voltage of a third node is equal to the voltage of the anode of the organic light-emitting diode, the scanning control signal line provides a low potential, the first thin film transistor and the third thin film transistor are turned on, the voltage of a second node is equal to the voltage of the anode of the organic light-emitting diode, the second thin film transistor is turned on, the power voltage is in a low potential state, the data signal line is in a turn-off state or provides a low potential to enable no current to pass through the organic light-emitting diode, and;
entering an adjusting stage, wherein when the adjusting stage is finished, the power supply voltage is equal to the negative voltage of the power supply or a high potential state is provided, the light-emitting signal line provides a high potential, the fourth thin film transistor and the fifth thin film transistor are closed, the organic light-emitting diode does not emit light, the scanning control signal line provides a high potential, the first thin film transistor and the third thin film transistor are closed, the voltage of a second node is kept equal to the voltage of the anode of the organic light-emitting diode, and the second thin film transistor is opened;
entering a data writing stage, wherein the power voltage is in a low potential state, the light-emitting signal line provides a high potential, the fourth thin film transistor and the fifth thin film transistor are closed, the organic light-emitting diode does not emit light, the scanning control signal line provides a low potential, the first thin film transistor and the third thin film transistor are opened, the data signal line provides a high potential, the second node writes the voltage provided by the data signal line, and the second thin film transistor is closed;
entering a holding stage, wherein the power supply voltage is equal to the negative voltage of the power supply or provides a high potential state, the light-emitting signal line provides a high potential, the fourth thin film transistor and the fifth thin film transistor are closed, the organic light-emitting diode does not emit light, the scanning control signal line provides a high potential, the first thin film transistor and the third thin film transistor are closed, the second node holds the voltage provided by the data signal line written in the data writing stage, and the second thin film transistor is closed;
and entering a driving stage, wherein the scanning control signal line provides a high potential, the first thin film transistor and the third thin film transistor are closed, the power supply voltage provides a high potential, the light-emitting signal line provides a low potential, the fourth thin film transistor and the fifth thin film transistor are opened, the second thin film transistor is in an open state, and the organic light-emitting diode emits light.
In the time sequence control method of the AMOLED time sequence control circuit, the brightness of the organic light emitting diode is controlled by adjusting the high and low levels of the power supply voltage, the delay time is reduced by controlling the high and low levels of the power supply voltage, and the adjusting effect of the organic light emitting diode is improved.
Preferably, the adjusting stage comprises:
in the first adjustment stage, the power voltage is equal to the negative voltage of the power supply, the light-emitting signal line provides a low potential, the fourth thin film transistor and the fifth thin film transistor are turned on, the scanning control signal line provides a high potential, the first thin film transistor and the third thin film transistor are turned off, the voltage of the second node is kept equal to the voltage of the anode of the organic light-emitting diode, the second thin film transistor is in an on state but no current passes through, and the organic light-emitting diode does not emit light at the moment;
in the second adjustment stage, the power voltage is equal to the negative voltage of the power supply or provides a high potential state, the light-emitting signal line provides a high potential, the fourth thin film transistor and the fifth thin film transistor are closed, the organic light-emitting diode does not emit light, the scanning control signal line provides a high potential, the first thin film transistor and the third thin film transistor are closed, the voltage of the second node is kept equal to the voltage of the anode of the organic light-emitting diode, and the second thin film transistor is opened.
Preferably, when the AMOLED timing control circuit includes the sixth thin film transistor and the seventh thin film transistor:
in the initialization stage, the power voltage is in a low potential state, the light emitting signal line provides a low potential, the fourth thin film transistor and the fifth thin film transistor are turned on, the voltage of the third node is equal to the voltage of the anode of the organic light emitting diode, the scanning control signal line provides a low potential, the first thin film transistor and the third thin film transistor are turned on, the voltage of the second node is equal to the voltage of the anode of the organic light emitting diode, the second thin film transistor, the sixth thin film transistor and the seventh thin film transistor are turned on, the power voltage is in a low potential state, the data signal line is in a turn-off state or provides a low potential, so that no current passes through the organic light emitting diode, and the organic light emitting;
in the adjusting stage, when the adjusting stage is finished, the power supply voltage is equal to the negative voltage of the power supply or a high potential state is provided, the light-emitting signal line provides a high potential, the fourth thin film transistor and the fifth thin film transistor are closed, the organic light-emitting diode does not emit light, the scanning control signal line provides a high potential, the first thin film transistor and the third thin film transistor are closed, the voltage of the second node is kept equal to the voltage of the anode of the organic light-emitting diode, the second thin film transistor is opened, and the sixth thin film transistor and the seventh thin film transistor are opened;
in the data writing stage, the power voltage is in a low potential state, the light-emitting signal line provides a high potential, the fourth thin film transistor and the fifth thin film transistor are turned off, the scanning control signal line provides a low potential, the first thin film transistor and the third thin film transistor are turned on, the data signal line provides a high potential, the sixth thin film transistor is firstly in an on state, the voltage provided by the data signal line is written into the second node through the first thin film transistor, the sixth thin film transistor and the third thin film transistor, when the voltage of the second node, namely the gate of the sixth thin film transistor reaches Vdata + Vth6, the sixth thin film transistor is turned off, the second thin film transistor and the seventh thin film transistor are turned off, wherein Vth6 is the threshold voltage of the sixth thin film transistor, and Vdata is the voltage provided by the data signal;
in the holding stage, the power supply voltage is equal to the negative power supply voltage or a high potential state is provided, the light emitting signal line provides a high potential, the fourth thin film transistor and the fifth thin film transistor are turned off, the organic light emitting diode does not emit light, the scanning control signal line provides a high potential, the first thin film transistor and the third thin film transistor are turned off, the voltage of the second node holds the voltage provided by the data signal line written in the data writing stage, the second thin film transistor is turned off, and the sixth thin film transistor and the seventh thin film transistor are turned off;
in the driving stage, the scan control signal line provides a high potential, the first thin film transistor and the third thin film transistor are turned off, the power voltage provides a high potential, the light emitting signal line provides a low potential, the fourth thin film transistor and the fifth thin film transistor are turned on, the second thin film transistor, the sixth thin film transistor and the seventh thin film transistor are in an on state, and the organic light emitting diode emits light.
Preferably, when the AMOLED timing control circuit includes the sixth thin film transistor and the seventh thin film transistor:
the adjusting stage comprises:
in the first adjustment stage, the power voltage is equal to the negative voltage of the power supply, the light-emitting signal line provides a low potential, the fourth thin film transistor and the fifth thin film transistor are turned on, the scanning control signal line provides a high potential, the first thin film transistor and the third thin film transistor are turned off, the voltage of the second node is kept equal to the voltage of the anode of the organic light-emitting diode, the second thin film transistor, the sixth thin film transistor and the seventh thin film transistor are turned on, no current passes through the second thin film transistor, and the organic light-emitting diode does not emit light at the moment;
in the second adjustment stage, the power voltage is equal to the negative voltage of the power supply or provides a high potential state, the light-emitting signal line provides a high potential, the fourth thin film transistor and the fifth thin film transistor are closed, the organic light-emitting diode does not emit light, the scanning control signal line provides a high potential, the first thin film transistor and the third thin film transistor are closed, the voltage of the second node is kept equal to the voltage of the anode of the organic light-emitting diode, and the second thin film transistor, the sixth thin film transistor and the seventh thin film transistor are opened.
Preferably, the signal provided by the scanning control signal line includes two pulses or more, and at least one pulse of the same time for all rows and one pulse of progressive scanning.
Preferably, the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, the sixth thin film transistor and the seventh thin film transistor are all low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors or amorphous silicon thin film transistors.
Drawings
FIG. 1 is a prior art AMOLED timing control circuit;
FIG. 2 is a first AMOLED timing control circuit provided in the present invention;
FIG. 3 is a second AMOLED timing control circuit provided by the present invention;
FIG. 4 is a timing diagram of the AMOLED timing control circuit shown in FIG. 3;
FIG. 5 is a circuit diagram of the AMOLED timing control circuit shown in FIG. 3 at an initialization stage;
FIG. 6 is a circuit diagram of the AMOLED timing control circuit shown in FIG. 3 at a first adjustment stage;
FIG. 7 is a circuit diagram of the AMOLED timing control circuit shown in FIG. 3 at a second adjustment stage;
FIG. 8 is a circuit diagram of the AMOLED timing control circuit shown in FIG. 3 during a data write phase;
FIG. 9 is a circuit diagram of the AMOLED timing control circuit shown in FIG. 3 during a hold phase;
FIG. 10 is a circuit diagram of the AMOLED timing control circuit shown in FIG. 3 at a driving stage.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 2, the present invention provides an AMOLED timing control circuit, which includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, a capacitor C1, and an organic light emitting diode D1;
a gate of the first thin film transistor T1 is electrically connected to the scan control signal line Sn, a first end is electrically connected to the Data signal line Data, and a second end is electrically connected to the first node N1;
a gate of the second thin film transistor T2 is electrically connected to the second node N2, a first terminal is electrically connected to the first node N1, and a second terminal is electrically connected to the third node N3;
a gate of the third tft T3 is electrically connected to the scan control signal line Sn, a first terminal of the third tft T3 is electrically connected to the second node N2, and a second terminal of the third tft T3 is electrically connected to the third node N3;
a gate of the fourth thin film transistor T4 is electrically connected to the light emitting signal line En, a first terminal is electrically connected to the power voltage ELVDD, and a second terminal is electrically connected to the first node N1;
a gate of the fifth thin film transistor T5 is electrically connected to the light emitting signal line En, a first terminal of the fifth thin film transistor T5 is electrically connected to the third node N3, and a second terminal of the fifth thin film transistor T5 is electrically connected to the anode of the organic light emitting diode D1;
a first end of the capacitor C1 is electrically connected to the second node N2; the second end is electrically connected to the power voltage ELVDD;
the anode of the organic light emitting diode D1 is electrically connected to the second end of the fifth thin film transistor T5, and the cathode is grounded;
the second thin film transistor T2 is a driving thin film transistor.
The AMOLED timing control circuit adopts a 5T1C structure, the threshold voltage of the driving thin film transistor is compensated through the third thin film transistor, and the AMOLED timing control circuit reduces scanning signal lines and reference voltage signal lines and reduces wiring inside a panel so as to adapt to small-size pixel space.
Referring to fig. 3, the AMOLED timing control circuit further includes:
a seventh tft T7 disposed between the second end of the first tft T1 and the first node N1, wherein a gate of the seventh tft T7 is electrically connected to the second node N2, a first end of the seventh tft T7 is electrically connected to the second end of the first tft T1, and a second end of the seventh tft T7 is electrically connected to the first node N1;
a sixth tft T6 disposed between the second end of the first tft T1 and the third tft T3, wherein a gate of the sixth tft T6 is electrically connected to the second node N2 and the first end of the capacitor C1, and shares a gate with the second tft T2, the first end is electrically connected to the second end of the first tft T1, and the second end is electrically connected to the second end of the third tft T3 and the third node N3.
The AMOLED timing control circuit adopts a 7T1C structure, and realizes the function of compensating the threshold voltage of the driving thin film transistor by symmetrically arranging a sixth thin film transistor and a second thin film transistor with equal threshold voltages, so that the current flowing through the organic light emitting diode is unrelated to the threshold voltage of the second thin film transistor, namely the driving transistor; the AMOLED timing control circuit reduces scanning signal lines and reference voltage signal lines and reduces wiring inside a panel to adapt to a small-sized pixel space.
Specifically, the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7 are all low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors. The sixth tft T6 and the second tft T2 are symmetrically disposed and have the same channel width, so that the threshold voltages of the sixth tft T6 and the second tft T2 are equal, and the threshold voltage of the sixth tft T6 can compensate the threshold voltage of the second tft T2, i.e., the driving tft, so that the current flowing through the organic light emitting diode is independent of the threshold voltage of the second tft T2. The two tfts T2 are driving tfts, and the sixth tft T6 is a mirror image tft.
Specifically, the input end of the scan control signal line Sn and the input end of the light emitting signal line En are each provided with a connection terminal for connection with an external timing controller. The scan control signal line Sn and the light emitting signal line En are provided through an external sequential circuit.
The invention also provides a timing control method of any AMOLED timing circuit in the technical scheme, which comprises the following steps:
entering an initialization stage 1, wherein the power voltage ELVDD is in a low potential state, and the voltage of the anode of the organic light emitting diode D1 is substantially equal to ELVSS voltage-3V; the light emitting signal line En provides a low potential, the fourth thin film transistor T4 and the fifth thin film transistor T5 are turned on, the voltage of the third node N3 is equal to the voltage of the anode of the organic light emitting diode D1, the scan control signal line Sn provides a low potential, the first thin film transistor T1 and the third thin film transistor T3 are turned on, the voltage of the second node N2 is equal to the voltage of the anode of the organic light emitting diode D1, i.e., the voltage of the second node N2 is equal to-3V, the second thin film transistor T2 is turned on, the power supply voltage ELVDD is in a low potential state, the Data signal line Data is in an off state or provides a low potential so that no current passes through the organic light emitting diode D1, and the organic light emitting diode D1;
entering the first adjustment phase 2, the power voltage ELVDD is equal to the power negative voltage ELVSS and equal to-3V, the light emitting signal line En provides a low potential, the fourth thin film transistor T4 and the fifth thin film transistor T5 are turned on, the scan control signal line Sn provides a high potential, the first thin film transistor T1 and the third thin film transistor T3 are turned off, the voltage of the second node N2 remains equal to the voltage of the anode of the organic light emitting diode D1, i.e., the voltage of the second node N2 is equal to-3V, since the power voltage ELVDD is in a low potential state, the first thin film transistor T1 and the third thin film transistor T3 are in an off state, the second thin film transistor T2 is in an on state but no current passes through, and the organic light emitting diode D1 does not emit light;
entering the second adjustment phase 3, the power voltage ELVDD is equal to the power negative voltage ELVSS, i.e., the power voltage ELVDD is-3V or a high state, the light emitting signal line En provides a high voltage, the fourth thin film transistor T4 and the fifth thin film transistor T5 are turned off, the fifth thin film transistor T5 is turned off so that the organic light emitting diode D1 has no conduction path and does not emit light, the scan control signal line Sn provides a high voltage, the first thin film transistor T1 and the third thin film transistor T3 are turned off, the voltage of the second node N2 is maintained to be equal to the voltage of the anode of the organic light emitting diode D1, i.e., the voltage of the second node N2 is equal to-3V, and the second thin film transistor T2 is turned on.
Entering a Data writing stage 4, the power voltage ELVDD is in a low potential state, the light emitting signal line En provides a high potential, the fourth thin film transistor T4 and the fifth thin film transistor T5 are turned off, the fifth thin film transistor T5 is turned off so that the organic light emitting diode D1 has no conduction path and does not emit light, the scan control signal line Sn provides a low potential, the first thin film transistor T1 and the third thin film transistor T3 are turned on, the Data signal line Data provides a high potential, the second node N2 writes a voltage provided by the Data signal line Data, and the second thin film transistor T2 is turned off;
entering a holding stage 5, the power supply voltage ELVDD is equal to the power supply negative voltage ELVSS or a high potential state is provided, the light emitting signal line En provides a high potential, the fourth thin film transistor T4 and the fifth thin film transistor T5 are turned off, the fifth thin film transistor T5 is turned off so that the organic light emitting diode D1 has no conduction path and does not emit light, the scan control signal line Sn provides a high potential, the first thin film transistor T1 and the third thin film transistor T3 are turned off, the second node N2 holds the voltage provided by the Data signal line Data written in the Data writing stage, and the second thin film transistor T2 is turned off;
in the driving phase 6, the scan control signal line Sn provides a high voltage, the first thin film transistor T1 and the third thin film transistor T3 are turned off, the power voltage ELVDD provides a high voltage, the light emitting signal line En provides a low voltage, the fourth thin film transistor T4 and the fifth thin film transistor T5 are turned on, the second thin film transistor T2 is turned on, and the organic light emitting diode D1 emits light.
In the time sequence control method of the AMOLED time sequence control circuit, the brightness of the organic light emitting diode is controlled by adjusting the high and low levels of the power supply voltage, the delay time is reduced by controlling the high and low levels of the power supply voltage, and the adjusting effect of the organic light emitting diode is improved.
When the AMOLED timing control circuit includes the sixth thin film transistor T6 and the seventh thin film transistor T7, the timing control method provided by the present invention includes the following steps:
referring to fig. 4 and 5, in the initialization phase 1, the power voltage ELVDD is at a low level, and the voltage of the anode of the organic light emitting diode D1 is substantially equal to the ELVSS voltage of-3V; the light emitting signal line En provides a low potential, the fourth thin film transistor T4 and the fifth thin film transistor T5 are turned on, the voltage of the third node N3 is equal to the voltage of the anode of the organic light emitting diode D1, the scan control signal line Sn provides a low potential, the first thin film transistor T1 and the third thin film transistor T3 are turned on, the voltage of the second node N2 is equal to the voltage of the anode of the organic light emitting diode D1, that is, the voltage of the second node N2 is equal to-3V, the second thin film transistor T2, the sixth thin film transistor T6 and the seventh thin film transistor T7 are turned on, the power supply voltage ELVDD is in a low potential state, the Data signal line Data is in an off state, or the low potential is provided so that no current flows through the organic light emitting diode D1 and the organic light emitting diode D1 does;
referring to fig. 4 and fig. 6, in the first adjustment phase 2, the power voltage ELVDD is equal to the power negative voltage ELVSS, that is, the power voltage ELVDD is equal to-3V, the light emitting signal line En provides a low voltage, the fourth thin film transistor T4 and the fifth thin film transistor T5 are turned on, the scan control signal line Sn provides a high voltage, the first thin film transistor T1 and the third thin film transistor T3 are turned off, the voltage at the second node N2 is kept equal to the voltage at the anode of the organic light emitting diode D1, the second thin film transistor T2, the sixth thin film transistor T6 and the seventh thin film transistor T7 are turned on, and since the power voltage ELVDD is at the low voltage, no current passes through the second thin film transistor T2, and the first thin film transistor T1 and the third thin film transistor T3 are turned off, the organic light emitting diode D1 does not emit light;
referring to fig. 4 and 7, in the second adjustment phase 3, the power voltage ELVDD is equal to the power negative voltage ELVSS or is at a high voltage level, the light-emitting signal line En is at a high voltage level, the fourth tft T4 and the fifth tft T5 are turned off, the fifth tft T5 is turned off to make the organic light-emitting diode D1 have no conduction path and emit no light, the scan control signal line Sn is at a high voltage level, the first tft T1 and the third tft T3 are turned off, the voltage of the second node N2 is kept equal to the voltage of the anode of the organic light-emitting diode D1, and the second tft T2, the sixth tft T6 and the seventh tft T7 are turned on.
Referring to fig. 4 and 8, in the Data writing phase 4, the power voltage ELVDD is in a low level state, the light emitting signal line En provides a high level, the fourth thin film transistor T4 and the fifth thin film transistor T5 are turned off, the fifth thin film transistor T5 is turned off so that the organic light emitting diode D1 does not emit light, the scan control signal line Sn provides a low level, the first thin film transistor T1 and the third thin film transistor T3 are turned on, the Data signal line Data provides a high level, the sixth thin film transistor T6 is first in an on state, the voltage provided by the Data signal line Data is written into the second node N2 through the first thin film transistor T1, the sixth thin film transistor T6 and the third thin film transistor T3, the sixth thin film transistor T6 is turned off after the voltage of the second node N2, i.e., the gate of the sixth thin film transistor T6 reaches Vdata + 6, the second thin film transistor T2 and the seventh thin film transistor T7 are turned off, wherein Vth6 is a threshold voltage of the sixth thin film transistor T6, and Vdata is a voltage provided by the Data signal Data;
referring to fig. 4 and 9, in the hold phase 5, the power voltage ELVDD is equal to the power negative voltage ELVSS or is in a high state, the light emitting signal line En is providing a high voltage, the fourth thin film transistor T4 and the fifth thin film transistor T5 are turned off, the fifth thin film transistor T5 is turned off so that the organic light emitting diode D1 has no conduction path and does not emit light, the scan control signal line Sn is providing a high voltage, the first thin film transistor T1 and the third thin film transistor T3 are turned off, the voltage of the second node N2 holds the voltage provided by the Data signal line Data written in the Data writing phase, and the second thin film transistor T2, the sixth thin film transistor T6 and the seventh thin film transistor T7 are turned off;
referring to fig. 4 and 10, in the driving phase 6, the scan control signal line Sn provides a high voltage, the first thin film transistor T1 and the third thin film transistor T3 are turned off, the power voltage ELVDD provides a high voltage, the light emitting signal line En provides a low voltage, the fourth thin film transistor T4 and the fifth thin film transistor T5 are turned on, the second thin film transistor T2, the sixth thin film transistor T6 and the seventh thin film transistor T7 are turned on, the organic light emitting diode D1 emits light,
the current flowing through the oled D1 at this time is:
IOLED＝K[VELVDD-Vdata+Vth6－Vth2]^2
when T2 and T1 are common-gate mirror relationships, Vth 6-Vth 2 are 0;
k is a structural parameter of the thin film transistor, and the K value is relatively stable for the thin film transistors with the same structure; vth6 is the threshold voltage of the sixth thin film transistor T6, and Vdata is the voltage provided by the Data signal Data; vELVDDIs the supply voltage.
As can be seen from the above analysis and calculation, the threshold voltage of the sixth thin film transistor T6 compensates the threshold voltage of the second thin film transistor T2, i.e., the driving thin film transistor, so that the current flowing through the organic light emitting diode D1 is independent of the threshold voltage of the second thin film transistor T2.
The AMOLED time sequence control circuit and the time sequence control method reduce scanning signal lines and reference voltage signal lines, reduce wiring inside a panel and adapt to small-size pixel space.
Specifically, the signal supplied from the scanning control signal line Sn is greater than or equal to two pulses, and includes at least one pulse of the same time for all rows and one pulse of progressive scanning.
It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (6)
1. A timing control method of an AMOLED timing control circuit is characterized by comprising the following steps:
entering an initialization stage, the power supply voltage (ELVDD) is in a low potential state, the light emitting signal line (En) provides a low potential, the fourth thin film transistor (T4) and the fifth thin film transistor (T5) are turned on, the voltage of the third node (N3) is equal to the voltage of the anode of the organic light emitting diode (D1), the scan control signal line (Sn) provides a low potential, the first thin film transistor (T1) and the third thin film transistor (T3) are turned on, the voltage of the second node (N2) is equal to the voltage of the anode of the organic light emitting diode (D1), the second thin film transistor (T2) is turned on, the power supply voltage (ELVDD) is in a low potential state, the Data signal line (Data) is in an off state or a low potential is provided so that a current flows through the organic light emitting diode (D1), and the organic light emitting diode (D1) does not emit;
entering a regulation phase, when the regulation phase is finished, the power supply voltage (ELVDD) is equal to the power supply negative voltage (ELVSS) or a high potential state is provided, the light emitting signal line (En) provides a high potential, the fourth thin film transistor (T4) and the fifth thin film transistor (T5) are turned off, the organic light emitting diode (D1) does not emit light, the scan control signal line (Sn) provides a high potential, the first thin film transistor (T1) and the third thin film transistor (T3) are turned off, the voltage of the second node (N2) is kept equal to the voltage of the anode of the organic light emitting diode (D1), and the second thin film transistor (T2) is turned on;
entering a Data writing phase, wherein the power supply voltage (ELVDD) is in a low potential state, the light emitting signal line (En) provides a high potential, the fourth thin film transistor (T4) and the fifth thin film transistor (T5) are turned off, the organic light emitting diode (D1) does not emit light, the scan control signal line (Sn) provides a low potential, the first thin film transistor (T1) and the third thin film transistor (T3) are turned on, the Data signal line (Data) provides a high potential, the second node (N2) writes a voltage provided by the Data signal line (Data), and the second thin film transistor (T2) is turned off;
entering a holding phase, wherein the power supply voltage (ELVDD) is equal to the power supply negative voltage (ELVSS) or provides a high potential state, the light emitting signal line (En) provides a high potential, the fourth thin film transistor (T4) and the fifth thin film transistor (T5) are turned off, the organic light emitting diode (D1) does not emit light, the scan control signal line (Sn) provides a high potential, the first thin film transistor (T1) and the third thin film transistor (T3) are turned off, the second node (N2) holds the voltage provided by the Data signal line (Data) written in the Data writing phase, and the second thin film transistor (T2) is turned off;
entering a driving stage, wherein the scanning control signal line (Sn) provides a high potential, the first thin film transistor (T1) and the third thin film transistor (T3) are turned off, the power supply voltage (ELVDD) provides a high potential, the light emitting signal line (En) provides a low potential, the fourth thin film transistor (T4) and the fifth thin film transistor (T5) are turned on, the second thin film transistor (T2) is in an on state, and the organic light emitting diode (D1) emits light;
wherein, the grid of the first thin film transistor (T1) is electrically connected with the scanning control signal line (Sn), the first end is electrically connected with the Data signal line (Data), and the second end is electrically connected with the first node (N1);
a gate of the second thin film transistor (T2) is electrically connected to the second node (N2), a first terminal is electrically connected to the first node (N1), and a second terminal is electrically connected to the third node (N3);
a gate of the third thin film transistor (T3) is electrically connected to the scan control signal line (Sn), a first terminal is electrically connected to the second node (N2), and a second terminal is electrically connected to the third node (N3);
a gate of the fourth thin film transistor (T4) is electrically connected to the light emitting signal line (En), a first terminal is electrically connected to the power voltage (ELVDD), and a second terminal is electrically connected to the first node (N1);
a gate of the fifth thin film transistor (T5) is electrically connected to the light emitting signal line (En), a first terminal of the fifth thin film transistor is electrically connected to the third node (N3), and a second terminal of the fifth thin film transistor is electrically connected to an anode of the organic light emitting diode (D1);
a first end of the capacitor (C1) is electrically connected to the second node (N2); the second end is electrically connected to the power voltage (ELVDD);
the anode of the organic light emitting diode (D1) is electrically connected to the second end of the fifth thin film transistor (T5), and the cathode is grounded.
2. The method of claim 1,
the adjusting stage comprises:
in a first adjustment phase, the power voltage (ELVDD) is equal to the negative power voltage (ELVSS), the light emitting signal line (En) provides a low potential, the fourth thin film transistor (T4) and the fifth thin film transistor (T5) are turned on, the scan control signal line (Sn) provides a high potential, the first thin film transistor (T1) and the third thin film transistor (T3) are turned off, the voltage at the second node (N2) is maintained equal to the voltage at the anode of the organic light emitting diode (D1), the second thin film transistor (T2) is in an on state but no current passes through, and the organic light emitting diode (D1) does not emit light;
in the second adjustment phase, the power voltage (ELVDD) is equal to the power negative voltage (ELVSS) or a high state, the light emitting signal line (En) provides a high voltage, the fourth thin film transistor (T4) and the fifth thin film transistor (T5) are turned off, the organic light emitting diode (D1) does not emit light, the scan control signal line (Sn) provides a high voltage, the first thin film transistor (T1) and the third thin film transistor (T3) are turned off, the voltage of the second node (N2) is maintained equal to the voltage of the anode of the organic light emitting diode (D1), and the second thin film transistor (T2) is turned on.
3. The method of claim 1, wherein when the AMOLED timing control circuit includes a sixth thin film transistor (T6) and a seventh thin film transistor (T7):
in the initialization stage, the power voltage (ELVDD) is in a low potential state, the light emitting signal line (En) provides a low potential, the fourth thin film transistor (T4) and the fifth thin film transistor (T5) are turned on, the voltage of the third node (N3) is equal to the voltage of the anode of the organic light emitting diode (D1), the scan control signal line (Sn) provides a low potential, the first thin film transistor (T1) and the third thin film transistor (T3) are turned on, the voltage of the second node (N2) is equal to the voltage of the anode of the organic light emitting diode (D1), the second thin film transistor (T2), the sixth thin film transistor (T6) and the seventh thin film transistor (T7) are turned on, the power voltage (ELVDD) is in a low potential state, the Data signal line (Data) is in an off state, or a low potential is provided such that no current passes through the organic light emitting diode (D1) and the organic light emitting diode (D1) does not emit light;
in the adjusting phase, when the adjusting phase is finished, the power voltage (ELVDD) is equal to the power negative voltage (ELVSS) or is in a high potential state, the light emitting signal line (En) provides a high potential, the fourth thin film transistor (T4) and the fifth thin film transistor (T5) are turned off, the organic light emitting diode (D1) does not emit light, the scan control signal line (Sn) provides a high potential, the first thin film transistor (T1) and the third thin film transistor (T3) are turned off, the voltage of the second node (N2) is kept equal to the voltage of the anode of the organic light emitting diode (D1), the second thin film transistor (T2) is turned on, and the sixth thin film transistor (T6) and the seventh thin film transistor (T7) are turned on;
in the Data writing stage, the power voltage (ELVDD) is in a low potential state, the light emitting signal line (En) provides a high potential, the fourth thin film transistor (T4) and the fifth thin film transistor (T5) are turned off, the scan control signal line (Sn) provides a low potential, the first thin film transistor (T1) and the third thin film transistor (T3) are turned on, the Data signal line (Data) provides a high potential, the sixth thin film transistor (T6) is first turned on, the voltage provided by the Data signal line (Data) is written into the second node (N2) through the first thin film transistor (T1), the sixth thin film transistor (T6) and the third thin film transistor (T3), and when the voltage of the second node (N2), i.e., the gate of the sixth thin film transistor (T6), reaches Vdata + Vth6, the sixth thin film transistor (T6) is turned off, the second thin film transistor (T2) and the seventh thin film transistor (T7) are turned off, wherein Vth6 is a threshold voltage of the sixth thin film transistor (T6), and Vdata is a voltage supplied by the Data signal (Data);
in the above-mentioned holding period, the power supply voltage (ELVDD) is equal to the power supply negative voltage (ELVSS) or a high potential state is supplied, the light emitting signal line (En) supplies a high potential, the fourth thin film transistor (T4) and the fifth thin film transistor (T5) are turned off, the organic light emitting diode (D1) does not emit light, the scan control signal line (Sn) supplies a high potential, the first thin film transistor (T1) and the third thin film transistor (T3) are turned off, the voltage of the second node (N2) holds the voltage supplied from the Data signal line (Data) written in the Data writing period, the second thin film transistor (T2) is turned off, and the sixth thin film transistor (T6) and the seventh thin film transistor (T7) are turned off;
in the driving stage, the scan control signal line (Sn) is supplied with a high voltage, the first thin film transistor (T1) and the third thin film transistor (T3) are turned off, the power supply voltage (ELVDD) is supplied with a high voltage, the light emitting signal line (En) is supplied with a low voltage, the fourth thin film transistor (T4) and the fifth thin film transistor (T5) are turned on, the second thin film transistor (T2), the sixth thin film transistor (T6) and the seventh thin film transistor (T7) are turned on, and the organic light emitting diode (D1) emits light.
4. The method of claim 3, wherein when the AMOLED timing control circuit includes a sixth thin film transistor (T6) and a seventh thin film transistor (T7):
the adjusting stage comprises:
in a first adjustment phase, the power voltage (ELVDD) is equal to the negative power voltage (ELVSS), the light emitting signal line (En) provides a low potential, the fourth thin film transistor (T4) and the fifth thin film transistor (T5) are turned on, the scan control signal line (Sn) provides a high potential, the first thin film transistor (T1) and the third thin film transistor (T3) are turned off, the voltage at the second node (N2) is maintained to be equal to the voltage at the anode of the organic light emitting diode (D1), the second thin film transistor (T2), the sixth thin film transistor (T6) and the seventh thin film transistor (T7) are turned on, no current flows through the second thin film transistor (T2), and the organic light emitting diode (D1) does not emit light;
in the second adjustment phase, the power voltage (ELVDD) is equal to the power negative voltage (ELVSS) or a high state, the light emitting signal line (En) provides a high voltage, the fourth thin film transistor (T4) and the fifth thin film transistor (T5) are turned off, the organic light emitting diode (D1) does not emit light, the scan control signal line (Sn) provides a high voltage, the first thin film transistor (T1) and the third thin film transistor (T3) are turned off, the voltage of the second node (N2) is maintained equal to the voltage of the anode of the organic light emitting diode (D1), and the second thin film transistor (T2), the sixth thin film transistor (T6) and the seventh thin film transistor (T7) are turned on.
5. A method according to any one of claims 1-4, characterized in that the signal supplied by the scanning control signal line (Sn) comprises more than or equal to two pulses and at least one pulse of the same time for all rows and one pulse for progressive scanning.
6. The method according to claim 3, wherein the first thin film transistor (T1), the second thin film transistor (T2), the third thin film transistor (T3), the fourth thin film transistor (T4), the fifth thin film transistor (T5), the sixth thin film transistor (T6), and the seventh thin film transistor (T7) are all low temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.
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