CN110319868A - High speed data acquisition system for MP-SCALE monitoring running state - Google Patents
High speed data acquisition system for MP-SCALE monitoring running state Download PDFInfo
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- CN110319868A CN110319868A CN201810294358.8A CN201810294358A CN110319868A CN 110319868 A CN110319868 A CN 110319868A CN 201810294358 A CN201810294358 A CN 201810294358A CN 110319868 A CN110319868 A CN 110319868A
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- G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
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Abstract
The present invention discloses a kind of high speed data acquisition system for MP-SCALE monitoring running state, including host module, one or more data acquisition modules and core bus.Data acquisition module includes multiple in electrically independent multiple A/D ALT-CH alternate channels and the FPGA circuitry controlled each A/D ALT-CH alternate channel.Each A/D ALT-CH alternate channel includes impedance inverter circuit, range conversion circuit, active low-pass filter, A/D converter, reference power supply and digital signal light electric isolator.DAQ host carries out data exchange by core bus and multiple DAQ data acquisition modules.FPGA circuitry provides sufficiently large mirror cache for each channel A/D, to guarantee that data are continuous in acquisition and recording and transmission process, breakpoint does not occur.
Description
Technical field
The present invention relates to hot fine rolling electrical equipment online measuring techniques, are used for real-time monitoring more particularly, to one kind
With the high-speed data acquiring device of the diagnosis in-oil cylinder MP-SCALE operating status of hot-rolling finishing mill AGC.
Background technique
Sensor currently used for the detection of hot-rolling finishing mill AGC oil cylinder position is mainly the MP-SCALE of Mitsubishi
The Magnescale displacement sensor of displacement sensor and Sony Corporation.Wherein Mitsubishi MP SCALE displacement sensor in
Start to be produced with U.S. INDUCTSYN company technique cooperation within 1970.
MP SCALE displacement sensor is the part for ensuring that precision is important in machine tool, precision when for temperature change
Stability, have to oil or use such as foreign matter preferably environment resistant, be easy to install and the high intensity of part material.Mitsubishi Heavy Industries Ltd will
These necessary basic performance conditions are added, and being improved out with technological development alone can be in high speed, the absolute value detection of height parsing
Product, in addition to using on the toolroom machine from society, be also sold to countries in the world toolroom machine factory use.
The magnescale displacement sensor of Sony company production is mainly used in the iron and steel thin sheet calender of metallurgical industry
Deng realization cold heat mill roll-gap high-acruracy survey.Its main function is the signal for receiving spot sensor, and differentiates magnetic scale
Moving direction, then according to generated displacement output pulse signal.Since metallurgy industry equipment is all in poor environment
Work on the spot, stability and anti-interference are particularly important, which is exactly that design thus produces, its excellent performance of grading,
Its series of products plays an important role in major milling train manufacturer, the world and steel plant.
Fig. 1 is the AGC system for including MP-SCALE displacement sensor.
MP-SCALE is feedback element important in hot-rolling finishing mill AGC system (automatic gauge control).Such as Fig. 1 institute
Show, is mounted on the feedback element that the in-oil cylinder MP-SCALE of AGC is the most outer ring of AGC hydraulic system.Once some MP-SCALE
Failure can directly result in AGC control exception, cause steel scrap.
Fig. 2 shows MP-SCALE AGC hydraulic system installation site.Dash area corresponds to MP-SCALE in AGC liquid
The installation site of pressure system.Since MP-SCALE is mounted on inside AGC oil cylinder, install, replace it is difficult.Online replacement one
MP-SCALE is usually required 8 hours or more.
MP-SCALE has very high detection accuracy and speed high, as shown in table 1 below:
The detection accuracy and speed of table 1MP-SCALE
The internal structure that MP-SCALE is shown shown in Fig. 3 may determine that MP- by the voltage signal of monitoring scale and dynamic ruler
The state of SCALE.
The scale (SIN/COS) of MP-SCALE and the waveform diagram of dynamic ruler (FBK) is shown respectively in Fig. 4 and Fig. 5.
Before the present invention, notes instrument is used to the maintenance test of MP-SCALE, notes instrument channel is limited.An and MP-
SCALE needs three channels, and 1580 hot rollings need to be equipped with 18 MP-SCALE, and therefore, notes instrument cannot achieve entirely at all
Weather is unremitting to be monitored MP-SCLAE.
In 1580 finish rolling regions, sensors with auxiliary electrode is mounted in AGC oil cylinder, once catastrophic failure, replacement needs at least 8 are small
When above time, this will cause to seriously affect to the normal operation of production line.
Present inventor has found that the damage of sensors with auxiliary electrode is mostly due to sensor magnetic according to the maintenance experience of many years
It caused by ruler is worn, and is usually all just thoroughly damage after being repeatedly abnormal, due to currently without effective, reliable prison
Control means, it is difficult in advance judge or occur primary fault after can lock reason rapidly, this for field device maintenance very
It is unfavorable.
It is found by the analysis to historical failure curve, when problem occurs for sensor magnetic scale, feedback waveform would generally be with
Be abnormal variation, if it is possible to realize to the monitoring and alarm with waveform, it will be able in advance prevent or judge that sensor is
It is no to break down, effective technological means will be provided to plant maintenance and troubleshooting, the steady production for guaranteeing rolling line will be played
Important role.
The object of the invention is to develop it is a set of can data to multiple sensors within the same time in real time online
Carry out high speed acquisition, processing and deposit.Operator can use Iba analyze software the data being saved are browsed,
Inquiry and analysis.It can be realized by this set high-speed data acquisition, processing, preservation system and eliminate AGC sensor fault in rudiment
State.
Summary of the invention
The purpose of the present invention is mainly to provide a kind of high speed data acquisition system for MP-SCALE monitoring running state, with
Improve the reliability that MP-SCALE sensor uses, cost efficiency and safety in production.
To achieve the goals above, the present invention uses following technical scheme.
A kind of DAQ high-speed data acquistion system for MP-SCALE monitoring running state and diagnosis, comprising: host mould
Block, one or more data acquisition modules and core bus, in which:
The host module is DAQ host；
The data acquisition module includes multiple converting in electrically independent multiple A/D ALT-CH alternate channels and to each A/D logical
The FPGA circuitry that road is controlled, wherein each A/D ALT-CH alternate channel includes impedance inverter circuit, range conversion circuit, has
Source low-pass filter, A/D converter, reference power supply and digital signal light electric isolator,
The DAQ host carries out data exchange by core bus and the multiple DAQ data acquisition module,
The FPGA circuitry receives the order of DAQ host, turns in the A/D that stipulated time cycle synchronisation starts each channel A/D
It changes, send chip selection signal, the A/D transformation result for receiving each A/D ALT-CH alternate channel to A/D converter, to the conversion of each channel A/D
As a result progress redundancy check, change data are deposited into corresponding data buffer area after determining correctly, are thus each channel A/D
Sufficiently large mirror cache is provided, to guarantee that data are continuous in acquisition and recording and transmission process, breakpoint does not occur.
The FPGA circuitry is field programmable logic battle array controller, its function is described by VHDL language, is led to
Cross off-line simulation, on-line testing technique modifies to it, FPGA is programmed by JTAC interface, change fpga logic
Battle array structure, realizes FPGA hardware and software.
The number of the DAQ data acquisition module is 1-9, and each DAQ data acquisition module includes 6 channels.
The number of the DAQ data acquisition module is 4, DAQ data collection system can simultaneously synchro measure 24 it is logical
The data in road.
The impedance inverter circuit of the DAQ data acquisition module is AD8221 amplifier, and input impedance reaches 1012Ω,
Input capacitance only has 2Pf；The range conversion circuit allows a variety of input data voltage ranges: 0-10V, 0-5V, ± 10V, ±
5V,0-20MA,4-20MA,±20MA,±10MA；The low-pass filter filter is second-order low-pass filter circuit, cutoff frequency
For 100kHz, quality factor q=0.707；The reference power supply is standard basis power supply REF3225, EF3225 reference power supply
Reference power supply voltage be 2.5V, temperature drift < 3PPM/0-125 DEG C, benchmark export electric current reach 10MA and low-noise current 10uA；
The A/D converter is ADS8317 16BIT high-speed a/d converter, and sampling and conversion rate reach 250KHz；The number
Word signal photoisolator is that ISO7231 is kept away for making front end analogue conversion circuit and digital circuit is being electrically isolated below
Exempt from string mould and common mode interference.
The DAQ host is the embedded industrial control board that TI AM3517 is primary processor, and the DAQ host receives to come from institute
The data ready request for stating the FPGA circuitry of DAQ data acquisition module receives signal, after confirmation request reception signal is effective,
Data reception signal successively is issued to each DAQ data acquisition module, and quickly reads the data of each DAQ data acquisition module, it is right
Received total data is packaged, and transfers data to data workstation by 10/100M Ethernet interface.
The panel of the DAQ host includes CF card slot, USB jack, and after insertion CF card or flash disk, Ethernet breaks down
When, data are automatically saved in CF card or flash disk by the DAQ host.
The core bus includes mounting groove 1-10, and wherein mounting groove 1 is for installing the DAQ host, mounting groove 2-10
For installing the DAQ data acquisition module.
The DAQ high-speed data acquisition network system based on PC and LAN that the present invention also provides a kind of, characterized by comprising:
PC machine and DAQ high-speed data acquistion system as described in one of claim 1-8, the PC machine pass through LAN, HUB or Ethernet
It is coupled with one or more DAQ high-speed data acquistion systems.
The PC machine is coupled with 2 DAQ high-speed data acquistion systems, realizes that 48 channel datas synchronize height without breakpoint for a long time
Fast continuous record.
The PC machine carries out parameter configuration and control to each channel of the DAQ high-speed data acquistion system and to each logical
The data in road are handled.
According to the present invention, it can be achieved that continuously being recorded for a long time, without breakpoint, synchronous high-speed to multichannel (48 channel) data.
Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, feature of the invention, purpose
It will be become more apparent upon with advantage.
Fig. 1 is schematic diagram of the MP-SCALE in AGC system；
Fig. 2 is installation site of the MP-SCALE in AGC system inside oil cylinder；
Fig. 3 is the internal structure of MP-SCALE；
Fig. 4 and Fig. 5 is the scale (SIN/COS) of MP-SCALE and the waveform diagram of dynamic ruler (FBK) respectively；
Fig. 6 is schematic diagram of the high speed data acquisition system according to the present invention in AGC system；
Fig. 7 is 4 DAQ data collection systems of 1PC connection according to an embodiment of the present invention；
Fig. 8 is DAQ data acquisition module/card in DAQ data collection system；
Fig. 9 is impedance inverter circuit；
Figure 10 is the relationship of typical CMRR and frequency；
The relationship of Figure 11 input offset current and voltage and temperature；
The relationship of Figure 12 gain and frequency；
Figure 13 RC active power filtering general diagram；
The active second-order low-pass filter circuit of Figure 14；
Figure 15 second-order low-pass filter amplitude-frequency characteristic；
Figure 16 AD conversion timing；
Figure 17 waveform requirements figure；
Figure 18 AD conversion result figure；
Figure 19 AD conversion schematic diagram；
Figure 20 ISO7231 pin figure；
Figure 21 is the panel of DAQ host；
The panel for the core bus that Figure 22 is；
Figure 23 is record fault waveform.
Specific embodiment
Below in conjunction with the attached drawing of the embodiment of the present invention, technical solution of the present invention is specifically described.
For existing notes instrument cannot achieve it is round-the-clock it is unremitting MP-SCLAE is monitored, the hair of the application
Bright people has carried out the DAQ high-speed data acquistion system research based on PC and LAN, and research includes the following aspects:
1, develop with standard rear panel bus can the multichannel of free configuration, high-precision, high-speed data truck (DAQ) packet
Include the corresponding FPGA control program of exploitation.
2, the data that can quickly read each DAQ card acquisition by standard rear panel bus are developed, and will be read by Ethernet
The data forwarding taken to upper workstation computer data forwarding card, including control program accordingly.
3, data processor is researched and developed, to guarantee that the data conversion collected by DAQ is simultaneous at Iba Analyze software
The data format of appearance, and can guarantee data lossless deposit for a long time.
By the studies above, present inventor develops a kind of DAQ high-speed data acquisition system based on PC and LAN
System.
One, according to an embodiment of the invention, HDAQ high-speed data acquistion system is made of following three parts:
1. with standard rear panel bus (EISA104) can free configuration multichannel, high-precision, high-speed data acquisition card
(DAQ)
One piece of data collecting card (DAQ) contains 6 data acquisition channels, and each data acquisition channel is transported by high impedance low noise
Calculate amplifier, low-pass filter and 16 speed A/D converter compositions.In order to improve the electromagnetic compatibility energy of data collection system
Power, uses between each channel independently-powered, and uses high speed photo coupling in transmission and is isolated.
2. having the data forwarding card of standard rear panel bus (EISA104)
The data of each DAQ card acquisition can be quickly read by standard rear panel bus, and pass through Ethernet for the number of reading
According to being forwarded to upper workstation computer.Data forwarding card uses Cortex-A8 embedded type CPU.
3. data workstation contains data processor, to guarantee the data conversion collected by DAQ at Iba
The data format of Analyze software compatibility, and can guarantee data lossless deposit for a long time.
Two, it is connect by 1 PC with multiple DAQ data collection systems based on the DAQ high-speed data acquistion system of PC and LAN
Composition.
An embodiment according to the present invention, 1 PC connection, 4 DAQ data collection system compositions, referring to attached drawing 7.
One DAQ data collection system installs four pieces of DAQ data acquisition modules,
Input channel that there are six one DAQ data acquisition module (card) tools,
The minimum measurement period of one DAQ data collection system is 32uS (48 channel).
One DAQ data collection system can 24 channel datas of synchro measure simultaneously.
One DAQ data collection system can be direct-connected by HUB or ethernet line and PC machine.Communication speed is 192KW/S
(4*1000*48)。
One DAQ data collection system is by a DAQ host and several pieces of DAQ data acquisition modules (card) and one piece
DAQ core bus composition.
DAQ data collection system can freely establish required measurement environment.A desk-top measuring instrument can be become after assembling
Device also may be mounted in rack and use as on-line real time monitoring instrument.Entire DAQ data collection system can be integrated in a height:
In the KBA mouse cage case of 5U.
Three, DAQ data acquisition module (card)
As shown in figure 8, there are six in electrically completely self-contained 16BITA/D ALT-CH alternate channel for DAQ data collecting card tool.Often
A channel is by impedance inverter circuit, range conversion circuit, active low-pass filter, A/D converter reference power supply, 16BIT
A/D converter and signal number optoisolator composition, as shown in Fig. 9.
1. impedance inverter circuit
Impedance inverter circuit has high input impedance, and impedance can be to avoid to quilt up to 20M Ω, high input impedance
The influence of test object.Simultaneously impedance inverter circuit have lower output impedance, lower output impedance can it is good with
Range conversion Circuit Matching can influence the precision of range conversion to avoid the internal resistance of induction signal source.
In the preferred embodiment, the impedance inverter circuit in data collecting card selects AD8221 amplifier.
D8221 is a gain programmable, high input impedance, low offset drift, low gain drift height, high-gain precision and the suppression of high common mode
High-performance instrumentation amplifier processed, common-mode rejection ratio (CMRR) highest in the industry cycle in similar product, relative to frequency.Current city
The CMRR of instrumentation amplifier is begun to decline in 200Hz on field, in contrast, AD8221 is minimum, and CMRR reaches 80dB in G=1
And it is wide to 10KHz.Relative to the high CMRR required for frequency, AD8221 can effectively inhibit broadband and line harmonic.
The input impedance of AD8221 amplifier reaches 1012Ω, input capacitance only have 2Pf.It ensure that the access of data collecting card will not be to original
System under test (SUT) generates any influence.Simultaneously the low offset drift of AD8221, low gain drift be high, high-gain precision characteristic guarantees
Signal of the capture card under longtime running transmits correct and stable.
Fig. 9 shows impedance inverter circuit according to an embodiment of the invention.
Figure 10 is the relationship (G=1) of typical CMRR and frequency.
Figure 11 is the relationship of input offset current and voltage and temperature
Figure 12 is the relationship of gain and frequency.
2. range conversion circuit
Range conversion circuit may be implemented to allow a variety of applied signal voltage ranges: 0-10V, 0-5V, ± 10V, ± 5V, 0-
20MA,4-20MA,±20MA,±10MA.To guarantee signal transmission precision, it is steady for 0.01% that range conversion circuit uses precision
The precision resister that fixed degree is 5PPM.
3. low-pass filter filters (LPF)
Filter can protrude the signal of useful frequency, the signal for unwanted frequency of decaying, and inhibit interference and noise, to reach
Improve the purpose of signal-to-noise ratio or frequency-selecting, it is contemplated that the working frequency of this system sensor is low using second order in 2KHz or less
Bandpass filter filter, effect are to filter off higher hamonic wave and noise.Requirement according to this capture card to signal, this low-pass filter
Passband gain Auf=1.6；Quality factor q=0.707；Cutoff frequency fH=100KHz；Stopband attenuation is not less than ︳ -40dB/
10oct|。
RC active filter is made of three parts circuit: RC network, amplifier, feedback network, wherein RC network filters out nothing
With frequency signal, useful frequency signal is amplified through amplifier, then output signal is fed back into amplifier in.
Figure 13 shows RC active power filtering general diagram
The effect of RC network, RC network plays a part of filtering in circuit, filters unwanted signal, to protrude
It with frequency signal, plays a crucial role in the selection to waveform, is usually mainly made of resistance and capacitor in this way,
Middle low pass filter cutoff frequency
The effect of amplifier has used homophase input amplifier in circuit, and input stage is made of differential type amplifying circuit, benefit
The performance of entire circuit can be improved with its symmetry；The main function of medium voltage amplifying stage is to improve voltage gain；Output
Grade provides certain power for load.Its closed loop gainIn-phase amplifier has input impedance very high, output
The very low feature of impedance amplify circuit can also by useful signal frequency while filtering.
The effect of feedback network, part or all by output signal pass through input amplifier, referred to as feed back,
In circuit be known as feedback network, feedback network is divided into positive-negative feedback.It is to pass through feedback element pair using output voltage that it, which is acted on,
Amplifying circuit plays adjust automatically, to restrain the variation of output voltage, finally reaches output stable equilibrium.
The transfer function of low-pass active filter (LPF), active filter are a kind of linear systems, are usually retouched with gain
The function of network is stated, that is, when primary condition is zero, the La Pula of the response (or output) and excitation (or input) of system
The ratio between this transformation, theoretically referred to as transmission function.The transfer function of step low-pass RC filter is as follows:
Wherein Au--- voltage gain
ωc--- the cut-off angular frequency of low-pass filter
4. the design of two stage RC active lowpass filter (LPF)
Low-pass filter is for by low frequency signals decay or inhibition high-frequency signal.As shown in Fig. 3 .7,
For typical second order active low-pass filter.It is made of two-stage RC filtering link with in-phase proportion computing circuit,
Wherein first order capacitor C is connected to output end, introduces suitable positive feedback, to improve amplitude-frequency characteristic.
The active second-order low-pass filter circuit of Figure 14
Figure 15 is second-order low-pass filter amplitude-versus-frequency curve.
5. circuit performance parameters
Passband gain:
Cutoff frequency (i.e. the threshold frequency of the passband of low-pass filter and stopband):
Quality factor (its size influences filter in the shape of the amplitude-frequency characteristic of stopband):
As 2 < AupWhen < 3, Q > 1, in f=f0The voltage gain at place will be greater than Aup, amplitude-frequency characteristic is in f=f0Place will raise
As shown in figures 3-8.Work as AupWhen >=3, Q=∞, active filter self-excitation.Due to by C1It is connected to output end, is given equal in front end
LPF has added some positive feedbacks, so the amplification factor in front end is raised, in some instances it may even be possible to cause self-excitation.
6, parameter calculates
The cutoff frequency of low-pass filter is set as 100kHz, quality factor q=0.707, A is obtained by formula 3-3up=
1.58, and obtained by formula 3-1Thus R is setf=9.1k Ω, R1=15k Ω；
To simplify the calculation, R is set2=R3=R, C1=C2=C；Again according to cutoff frequency, electricity is primarily determined by formula 3-2
Capacitance C1=C2=C=51P obtains R by formula 3-22=R3=3k Ω
The effect of low-pass filter is to filter off higher hamonic wave and noise.The corner frequency f of low pass filter0For 5kHz, and it is right
Signal is with -20db/ frequency doubling attenuation.
7. reference power supply
Reference power supply provides stability high standard basis power supply for A/D converter.For definitely 16 AD conversion
Precision, present invention employs REF3225 reference power supplies.The reference power supply voltage of REF3225 reference power supply is 2.5V, temperature drift
< 3PPM/0-125 DEG C, benchmark export electric current and reach 10MA and low-noise current 10uA.
8.A/D conversion circuit
A/D conversion circuit uses ADS8317 16BIT high-speed a/d converter, and sampling and conversion rate reach 250KHz,
It is not in leakage code in entire defined input voltage range.With splendid AD transfer linearity, nonlinearity erron as low as
±0.8LSBtyp,±1.5LSBmaxINL.With extremely low offset voltage Offset ± 1MVMAX.Extremely low power dissipation 10MW, in 5V
Power supply, when conversion rate 250KHz.
Figure 16 shows the serial 3 line SPI interface (CS, DCLK, Dout) of standard, 16 AD conversion timing.
Figure 17 and following table are the waveform requirements figure of AD conversion.
TIMING INFORMATION(continued) Timing Characteristics
Figure 18 and following table show that 16 AD conversion input analog voltages are corresponding with output binary system and heuristicimal code and close
System.
Figure 19 is 16 AD conversion schematic diagrams.
It is sampled and conversion rate reaches 200KHz
9. signal isolation circuit
Signal isolation circuit can be kept away by front end analogue conversion circuit and subsequent digital circuit electrically completely isolated
Exempt from string mould and common mode interference.ISO7231 is used in this case.ISO7231 is integrated with three signal isolation circuits.Three signals every
From circuit arrangement in the chip and pin arranging such as Figure 20.
The choosing of INA-OUTA:CS piece, is issued by FPGA.
INB-OUTB:DCLK change over clock, is issued by FPGA.
The output of INC-OUTC AD result, is issued by converter.
FPGA circuitry realizes the control to each channel A/D ALT-CH alternate channel, and it is slow to provide the sufficiently large mirror image of mirror for each channel
It deposits and bus access interface driver.
Figure 20 is ISO7231 pin figure.
ISO7231 has high signal transmission rate, reaches 25Mbps/S. isolation voltage and reaches 560V and have anti-
4000V electrostatic interference (EDS) ability.
10.FPGA circuit
Altera corp CycloneII EPC2C8144I5FPGA is used in the present case.Using the realization pair of FPGA circuit
The control of each channel A/D ALT-CH alternate channel, FPGA receive the order of DAQ host, and cycle synchronisation starts each channel in required time
AD conversion, downtown number required for sending chip selection signal to A/D converter circuit and convert.Receive each channel AD conversion result.It is right
The result of each channel conversion carries out redundancy check, then determines that change data is correctly stored in corresponding data buffer area afterwards.
EPC2C8144I5FPGA has 36KbitM4KRAM, and total RAM number reaches 165,888bit.Using Altera FPGA
165,888bitRAM is divided into two 16bit*4KW data blocks, sufficiently large mirror cache is provided for each channel by nuclear technology,
Guarantee that data are continuous in acquisition and recording and transmission process, breakpoint does not occur.FPGA also provides interface driver for bus access,
The EISA104 bus specification of realization standard.Exactly replace previous MCU technology using FPGA technology.That is hardware skill is used
Art is instead of software technology.Data high-speed acquisition is just able to achieve continuously without breakpoint non-volatile recording.
Continuously recorded without breakpoint synchronous high-speed for a long time to be able to achieve multichannel (48 channel) data, the present invention use with
Lower technology:
1, hardware and software according to the present invention, is realized using field programmable logic battle array controller technology (FPGA).
Previous recorder mostly uses CPU+ software form to work.It works under this form.Recorder work is by software
Operation control.Software control successively carries out each channel analog-to-digital conversion (A/D conversion), reads transformation result, then logarithm
According to being handled, deposit caching is forwarded.CPU can only execute a task at any time, this will generate following problems: 1.1
The same task of n times will be repeated in N number of channel data record CPU under software control, limit the record of recorder
Speed and real-time.1.2 can not accurately determine in software runing time, can not achieve N channel data synchronous recording, limit
The use scope of recorder.It is poor that 1.3 softwares run Electro Magnetic Compatibility, is easy to be disturbed generating routine and runs fast phenomenon, although can be with
Program can be made to work normally again by watchdog technique, but record stops at this moment, breakpoint occur in record data.Using soft
After part Hardware, very effective problem above can be overcome.
FPGA field programmable logic battle array controller is that money can be retouched by the function that VHDL language to realize it
It states.Then by off-line simulation, the technologies such as on-line testing repeatedly modify to it description.Until obtaining satisfied anticipation function
Afterwards, FPGA is programmed by JTAC interface (fpga chip is included), changes fpga logic battle array structure, realizes desired function
Energy.It is no longer under software control in recorder work but is controlled by fpga logic battle array is changed, practiced hardware and software.
2, N number of parallel synchronous trigger mechanism is created
Due to using hardware and software technology, there is parallel processing performance using FPGA, create N number of input channel data
Function blocks, each functional block include that starting analog signal to digital signal converts (AD conversion), reads data information, number
Word filtering, data redundancy processing and data save.N number of input channel data processing function block is in clock touch-control system synchronizing cycle
Under, the synchronous working in period.It walks around through emulation and actual test AD and consumes 5us, reading data 0.02us, digital filtering
0.02us, data redundancy are handled 4 times, and data save 0.02us, and successively N channel data processing consumes 25us altogether.Due to using
FPGA technology, parallel synchronous practice trigger mechanism.It is said in principle, how much unrelated data acquisition writing speed is with port number.It is practical
48 channels have been used, estimated performance and technical requirements are fully achieved.Speed improves compared with traditional CPU+ software mode
48 times (for 48 channels).It can be seen that traditional CPU+ software mode can not practice above-mentioned performance.
3, data pipe Techniques of preserving is created
Data buffer storage is not only greatly improved using data pipe Techniques of preserving (fifo fifo technology) in FPGA to turn
Efficiency is sent out, and the consumption of FPGA logic cell can be reduced, the utilization rate of FPGA is improved, reduces the ` manufacturing cost of equipment.Its
Implementation method is exactly the data pipe caching that a certain length is created in each channel data processing function module
(FIFORAM), it is 128BYTE that length is created in this equipment.The processing of data pipe buffer inlet logical connection data redundancy is defeated
Out, the outlet of data pipe caching is connected to TCP delivery module input port.Two counters of each data pipe cached configuration.One
It pushes on counter for data, the number to push on for recording data is a counter.The other is counter of popping, is used for
Record pop data counts and a up counter.By carrying out algebraic operation to love song counter, to control log-on data
Data are popped and automatically adjust to pop speed.When data push on number reach certain amount when, log-on data is popped, and data push on
Speed is determined that this equipment is 32.25us by the AD conversion period.And data speed of popping is pushed on by data and counter and pops counting
It is automatically adjusted after device.It when the counting that pushes on reaches certain length, and pushes on to count speedup and be greater than and pop when counting speedup, pop
Speed is accelerated automatically.When counting of popping subtract push on counting be less than push on counting step when, stop data popping.It ensure that data pipe
There are certain data in flow at high speed always in road caching, will not both be read sky, and data spilling will not occur.Each data pipe
The address of overabsorption certain length is cached, each data buffer storage address is unique in whole equipment.And it is linear by channel number
Arrangement
4, multithreading
Two threads are created in FPGA, a thread includes in this thread for handling the processing of N channel reading data
The realization of 48 channel (this equipment) parallel synchronous trigger mechanism logic modules synchronizes processing function to 48 channel datas.Another
FPGA nuclear technology is utilized in journey of relocating and is created TCP sending function module due to data forwarding for thread.Work as parallel synchronous
Trigger mechanism logic module record data reach certain length, while starting data in 48 data pipe cachings and popping.At this point,
TCP data forwards thread work, reads data in each data pipe caching by linear array, will be counted by TCP transmission interface
According to sending to local area network or wide area network.
5, functional description language process
It is realized by functional description language process
FPGA is initialized；
It creates 48 length and sets out mechanism module, TCP transmission core and distribution respectively for 128B FIFO, 48 parallel synchronous
A I/O function；
Realize that the starting AD conversion to 48 channels, reading transformation result, digital filtering, data redundancy entangle by thread 1
Wrong, data push on；By realization of thread 2 etc., pending datas are popped, detection data is popped, read each data fifo and send number
According to.
11.DAQ data collecting card technical indicator
Four, DAQ host
DAQ host is a embedded industrial control board using Cortex-A8 chip (TI AM3517) as primary processor, should
CPU is based on Cortex-A8 nuclear design.Can support 24 bit address buses and 16 bit data bus, provide USB2.0, SD Card,
UART, CAN, SPI, IIC and adaptive 10/100M Ethernet.Support 6.0 operating system of winCE.Support hot plug.With it
Cooperation is one piece of Altera company MAXII EPC570T144I3CPLD.EPC570T144I3CPLD effect is by Cortex-
A8 supports 24 bit address buses and 16 bit data bus to be configured to meet the bus interface of EISAPC104 specification, is passed through with realizing
The EISA104 bus of construction, DAQ host can carry out data access with several pieces of data collecting cards.Construct EISA data/address bus
Possess 16 bit data bus, 24 bit address buses, 6 control buss (RD reads control, WR writes control, MEN internal storage access is enabled,
16 data access of BHEN, IRQ access request and the request of DAM block access).EISAPC104 bus access rate reaches 4MW/S.
The task of DAQ host is the data ready request reception signal for receiving the FPGA on capture card, confirmed
It is successively to issue data reception signal to a data collecting card, and quickly read the data of a capture card after effective request.And it will
All received data are packaged, and transfer data to data workstation by 10/100M Ethernet interface.
After insertion CF card or flash disk, when Ethernet failure, data are automatically saved in CF card or excellent by DAQ host
In disk.Since data do not carry out compression processing, so the amount of data stored about 920M/H.Data save length view CF card with
Depending on flash disk capacity.
DAQ host technology index
DAQ host software function
Receive the configuration parameter of the DAQ rack of PC machine sending, far control trigger command
Receive interruption by chassis configuration parameter and control command and DAQ capture card request of data, the data of receiving are with west gate
Sub- TDC ethernet communication protocol format forwards data to PC machine.
The working condition of each DAQ capture card in rack is read, and uses LED indication respectively.
Timing sends out DAQ capture card work state information each to PC machine.
The record length of acquisition data is controlled by chassis configuration parameter and remote control order.
When network communication failure, stored data into CF card or USB flash disk automatically.
Figure 21 is DAQ host panel.
Five, core bus
Figure 22 shows the core bus of DAQ capture card data system.
Core bus includes 16 radicals evidence, 24 address bus of bus, 2 read-write lines, 2 interrupt request lines, 1 memory behaviour
Make line, the ready line of 1 root device and root device engaged line.
DAQ host carries out data exchange by core bus with capture card.One DAQ data collection system rack can receive
9 DAQ data collecting cards.
Core bus 1# slot installs DAQ host.
Core bus 2# slot installs 1#DAQ capture card, this slot cannot be sky.
Core bus 3-10# slot can install DAQ capture card as needed.
Six, PC machine configuration requirement
According to an embodiment of the invention, 1 PC machine can be connect with 4 DAQ data collection systems, 48 can be handled simultaneously
The data volume in a channel.
PC machine technical indicator
PC machine software function
Configuration DAQ system
1, rack number is configured, IP and port numbers that each rack DAQ host is directed toward are set
2, the number of DAQ capture card in each rack is configured.
3, triggering mode, record length are set.The triggering mode and record length of each rack can be respectively set.Triggering
What record length of mode, which is shown in DAQ capture card technical indicator table, describes.
4, the content in above-mentioned 2,3 is sent into the DAQ host in each rack by Ethernet.
Control parameter configuration is carried out to each channel
1, channel input type and range:
0-5V 0-10V±10V±10V 0-20MA 4-20MA ±20MA ±10MA
2, engineering range is set:
0.0000-99999.0000
3, the sampling period sets
250uS---60S is the multiple of 250uS between shelves
It set time by DAQ host of the Ethernet to each rack, issue remote control trigger command.
Each channel data is handled
1, data are extracted by the measurement period of each path setting.
2, quantification treatment is carried out by the project amount of setting to the data of extraction.
3, data compression is carried out by PDA analysis software.
4, hard disk is deposited by PDA format and requirement.Data retention over time 90 days.
Seven, physical record is as the result is shown
Figure 23 is record fault waveform.
Eight, the technical indicator and technical effect reached
An embodiment according to the present invention, has reached following technical indicator:
1, the conversion of 48 Channel Synchronous, change-over period 32us are realized
2, data save format and Iba6.12 is completely compatible
3, it is able to achieve the synchronous forwarding (DAQ conversion board) of 1.8MW/S speed data
4,5.6MW/S data receiver, compression, deposit are able to achieve (PC machine technical indicator is shown in PC machine, configuration).
5, it deposits the holding time 7 days and recycles
6, data are without breakpoint
7, data forwarding compresses the bit error rate less than 1/10-9
8, the DAQ system mean free error time is greater than 20000 hours.
According to the present invention, it realizes and multichannel (48 channel) data is continuously recorded for a long time, without breakpoint, synchronous high-speed.
Although this technology is led finally it is pointed out that the present invention is described with reference to current specific embodiment
Those of ordinary skill in domain it should be appreciated that more than embodiment be intended merely to illustrate the present invention, and be not used as to this
The restriction of invention can also make various equivalent change or replacement without departing from the inventive concept of the premise, therefore, as long as
Claims of the present invention range will all be fallen in the variation of above-described embodiment, modification in spirit of the invention
It is interior.
Claims (11)
1. a kind of high speed data acquisition system for MP-SCALE monitoring running state, it is characterised in that: the DAQ high-speed data
Acquisition system includes host module, one or more data acquisition modules and core bus, in which:
The host module is DAQ host；
The data acquisition module include it is multiple electrically independent multiple A/D ALT-CH alternate channels and to each A/D ALT-CH alternate channel into
The FPGA circuitry of row control, wherein each A/D ALT-CH alternate channel includes impedance inverter circuit, range conversion circuit, active low
Bandpass filter, A/D converter, reference power supply and digital signal light electric isolator,
The DAQ host carries out data exchange by core bus and the multiple DAQ data acquisition module,
The FPGA circuitry receive DAQ host order, stipulated time cycle synchronisation start each channel A/D A/D conversion, to
A/D converter send chip selection signal, the A/D transformation result for receiving each A/D ALT-CH alternate channel, to the result of each channel A/D conversion into
Row redundancy check, change data are deposited into corresponding data buffer area after determining correctly, thus provide foot for each channel A/D
Enough big mirror caches, to guarantee that data are continuous in acquisition and recording and transmission process, breakpoint does not occur.
2. a kind of high speed data acquisition system for MP-SCALE monitoring running state as described in claim 1, feature exist
In: the FPGA circuitry is field programmable logic battle array controller, its function is described by VHDL language, by offline
Emulation, on-line testing technique modify to it, are programmed by JTAC interface to FPGA, change fpga logic battle array structure,
Realize FPGA hardware and software.
3. a kind of high speed data acquisition system for MP-SCALE monitoring running state as described in claim 1, feature exist
In: the number of the DAQ data acquisition module is 1-9, and each DAQ data acquisition module includes 6 channels.
4. a kind of high speed data acquisition system for MP-SCALE monitoring running state as claimed in claim 1 or 2, feature
Be: the number of the DAQ data acquisition module is 4, and DAQ data collection system can 24 channels of synchro measure simultaneously
Data.
5. a kind of high speed data acquisition system for MP-SCALE monitoring running state as described in claim 1, feature exist
In: the impedance inverter circuit of the DAQ data acquisition module is AD8221 amplifier, and input impedance reaches 1012Ω, input electricity
Hold and there was only 2Pf；The range conversion circuit allows a variety of input data voltage ranges: 0-10V, 0-5V, ± 10V, ± 5V, 0-
20MA,4-20MA,±20MA,±10MA；The low-pass filter filter is second-order low-pass filter circuit, and cutoff frequency is
100kHz, quality factor q=0.707；The reference power supply is the base of standard basis power supply REF3225, EF3225 reference power supply
Quasi- supply voltage be 2.5V, temperature drift < 3PPM/0-125 DEG C, benchmark export electric current reach 10MA and low-noise current 10uA；Institute
Stating A/D converter is ADS8317 16BIT high-speed a/d converter, and sampling and conversion rate reach 250KHz；The number letter
Number photoisolator is ISO7231, for making front end analogue conversion circuit and digital circuit is being electrically isolated below, avoids going here and there
Mould and common mode interference.
6. a kind of high speed data acquisition system for MP-SCALE monitoring running state as described in claim 1, feature exist
In: the DAQ host is the embedded industrial control board that TI AM3517 is primary processor, and the DAQ host receives to come from the DAQ
The data ready request of the FPGA circuitry of data acquisition module receives signal, after confirmation request reception signal is effective, successively
Data reception signal is issued to each DAQ data acquisition module, and quickly reads the data of each DAQ data acquisition module, to reception
Total data be packaged, data workstation is transferred data to by 10/100M Ethernet interface.
7. a kind of high speed data acquisition system for MP-SCALE monitoring running state as claimed in claim 6, feature exist
In: the panel of the DAQ host includes CF card slot, USB jack, after insertion CF card or flash disk, when Ethernet breaks down, institute
It states DAQ host data are automatically saved in CF card or flash disk.
8. a kind of high speed data acquisition system for MP-SCALE monitoring running state as described in claim 1, feature exist
In: the core bus includes mounting groove 1-10, and wherein mounting groove 1 is for installing the DAQ host, and mounting groove 2-10 is for pacifying
Fill the DAQ data acquisition module.
9. a kind of DAQ high-speed data acquisition network system based on PC and LAN, characterized by comprising: PC machine and as right is wanted
The high speed data acquisition system that MP-SCALE monitoring running state is used for described in one of 1-8 is sought, the PC machine passes through LAN, HUB
Or Ethernet is coupled with one or more DAQ high-speed data acquistion systems.
10. the DAQ high-speed data acquisition network system based on PC and LAN as claimed in claim 9, it is characterised in that: described
PC machine is coupled with 2 DAQ high-speed data acquistion systems, realizes that 48 channel datas are continuously recorded without breakpoint synchronous high-speed for a long time.
11. the DAQ high-speed data acquisition network system based on PC and LAN as claimed in claim 9, it is characterised in that: described
PC machine carries out parameter configuration and control to each channel of the DAQ high-speed data acquistion system and carries out to the data in each channel
Processing.
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