CN110310893A - A kind of production method of semiconductor devices, semiconductor devices and electronic device - Google Patents
A kind of production method of semiconductor devices, semiconductor devices and electronic device Download PDFInfo
- Publication number
- CN110310893A CN110310893A CN201810229806.6A CN201810229806A CN110310893A CN 110310893 A CN110310893 A CN 110310893A CN 201810229806 A CN201810229806 A CN 201810229806A CN 110310893 A CN110310893 A CN 110310893A
- Authority
- CN
- China
- Prior art keywords
- fin structure
- layer
- dummy gate
- gate
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 71
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 47
- 239000010703 silicon Substances 0.000 claims abstract description 47
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims abstract description 35
- 238000002955 isolation Methods 0.000 claims abstract description 19
- 238000000926 separation method Methods 0.000 claims abstract description 9
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 144
- 239000000463 material Substances 0.000 claims description 46
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- 125000006850 spacer group Chemical group 0.000 claims description 13
- 239000011229 interlayer Substances 0.000 claims description 6
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 10
- 150000004706 metal oxides Chemical class 0.000 description 10
- 230000005669 field effect Effects 0.000 description 9
- 238000005530 etching Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 7
- 239000012212 insulator Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 239000002070 nanowire Substances 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 210000000746 body region Anatomy 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000011777 magnesium Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910010041 TiAlC Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 210000000695 crystalline len Anatomy 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- -1 for example Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The present invention provides production method, semiconductor devices and the electronic device of a kind of semiconductor devices, which is characterized in that the described method comprises the following steps: step a) provides semiconductor substrate；Step b), forms fin structure on the semiconductor substrate；Step c) is developed across the dummy gate of the fin structure in the fin structure；Step d) etches the part positioned at the dummy gate two sides of the fin structure to the top surface of the semiconductor substrate；Step e), the deposited bottom separation layer on the top surface；Step f), epitaxial growth source region and drain region on the bottom isolation layer.The circulating type gate mos (GAA MOS) that the present invention forms plane formula are that 3 end structures, source region and drain region and body silicon substrate are completely isolated.
Description
Technical field
The present invention relates to technical field of semiconductors, partly lead in particular to a kind of circulating type grid complementary metal oxide
The production method of body device.
Background technique
MOS transistor is one of most important element in modern integrated circuits.The basic structure of MOS transistor includes: half
Conductor substrate；Source region and position positioned at the gate structure of semiconductor substrate surface, in the semiconductor substrate of gate structure side
Drain region in the semiconductor substrate of the gate structure other side.MOS transistor adjusts by applying voltage in grid and passes through grid knot
The electric current of structure bottom channel generates switching signal.
With the development of semiconductor technology, the MOS transistor of traditional plane formula dies down to the control ability of channel current,
Cause serious leakage current.Fin formula field effect transistor (Fin FET) is a kind of emerging multi-gate device, it generally comprises protrusion
In the fin of semiconductor substrate surface, the top surface of fin and the gate structure of side wall described in covering part are located at grid knot
Source region in the fin of structure side and the drain region in the fin of the gate structure other side.
By increasing following two processing step in the forming method of fin formula field effect transistor, so that it may be formed and be surround
Formula grid complementary metal oxide semiconductor.Circulating type gate nanowire Metal Oxide Semiconductor Field Effect Transistor as a result,
It (MOSFETs) is a kind of possible extension of fin formula field effect transistor (FinFET).Two above-mentioned processing steps are as follows: step
A), SiGe/Si fin structure is formed on a semiconductor substrate, wherein fin structure may include stacking setting between each other
Multiple germanium-silicon layers and silicon layer, for example, the germanium-silicon layer successively stacked, silicon layer, germanium silicon layer, silicon layer, germanium silicon layer ....Step b),
It replaces in metal gate process step, selective removal germanium-silicon layer, then, in the germanium-silicon layer of removal and the position shape of dummy gate
At high-K metal gate, in this way, high-K metal gate just surround silicon layer, to form circulating type gate mos.
But there are still bottom parasitisms for the circulating type gate mos of current plane formula (GAA MOS)
The problem of metal-oxide semiconductor (MOS).
Therefore, it is necessary to a kind of new production method is provided, it is the problems of current at least to be partially solved.
Summary of the invention
In view of the above-mentioned problems, on the one hand, the present invention provides a kind of production method of semiconductor devices, which is characterized in that packet
Include following steps:
Step a), provides semiconductor substrate；
Step b), forms fin structure on the semiconductor substrate；
Step c) is developed across the dummy gate of the fin structure in the fin structure；
Step d) etches the part positioned at the dummy gate two sides of the fin structure to the semiconductor substrate
Top surface；
Step e), the deposited bottom separation layer on the top surface；
Step f), epitaxial growth source region and drain region on the bottom isolation layer.
It is further comprising the steps of after the step f) in an example of the invention:
Step g), the interlayer dielectric between the dummy gate, and grind the inter-level dielectric；
Step h) removes the part fin structure below the dummy gate and the dummy gate；
Step i), the position of the part fin structure below the dummy gate and the dummy gate of removal
High-K metal gate is formed, the high-K metal gate is around the part of the fin structure not being removed, to form circulating type grid
Structure.
In an example of the invention, the fin structure includes multiple material layers stacked.
In an example of the invention, the multiple material layer stacked includes germanium-silicon layer and/or silicon layer.
In an example of the invention, the germanium-silicon layer and the silicon layer successively stack from bottom to up, in step h),
Removal is the germanium-silicon layer being located at below the silicon layer.
In an example of the invention, after forming the fin structure, before the dummy gate is formed, also wrap
It includes the step of the top surface of the fin structure and side form oxide.
It further include the two of the dummy gate after forming the dummy gate in an example of the invention
Side forms the step of clearance wall.
It further include being formed with spacer material layer on the surface of the semiconductor substrate in an example of the invention
Step.
The semiconductor devices that the method according to one of above-mentioned that the invention also discloses a kind of is prepared.
The invention also discloses a kind of electronic devices, which is characterized in that the electronic device includes above-mentioned semiconductor device
Part.
The invention proposes the process flow for forming circulating type gate mos (GAA MOS), the techniques
Process solves the bottom circulating type gate mos (GAA MOS) parasitic metal oxide semiconductor of plane formula
(MOS) the problem of.By removing the part positioned at dummy gate two sides of fin structure, and the position extension in the part of removal
Before growing source region and drain region, the deposited bottom separation layer on the top surface of grid two sides, so that bottom isolation layer covering device
The extension in the body region of bottom-exposed source region and drain region, source region and drain region from channel region grow, with lower bulk separate from.This hair
The bright circulating type gate mos (GAA MOS) for forming plane formula are that 3 end structures, source region and drain region and body silicon serve as a contrast
Bottom is completely isolated.Method of the invention is also apply to the resulting fin formula field effect transistor (Fin FET), to reduce source region and drain region
To the leakage current in body area.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
The production method that FIG. 1 to FIG. 6 shows an embodiment of the present invention successively implements cuing open for the obtained device of each step
Face schematic diagram；
Fig. 7 shows the schematic diagram of electronic device according to an embodiment of the present invention；And
Fig. 8 shows the flow chart of the production method of semiconductor devices according to an embodiment of the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Example.On the contrary, provide these examples will make it is open thoroughly and completely, and will fully convey the scope of the invention to ability
Field technique personnel.
The purpose of term as used herein is only that description specific example and not as limitation of the invention.It uses herein
When, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates in addition
Mode.Be also to be understood that term " composition " and/or " comprising ", when being used in this specification, determine the feature, integer,
The presence of step, operations, elements, and/or components, but it is not excluded for one or more other features, integer, step, operation, member
The presence or addition of part, component and/or group.Herein in use, term "and/or" includes any and all of related listed item
Combination.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical solution proposed by the present invention.Preferable examples of the invention are described in detail as follows, however other than these detailed descriptions,
The present invention can also have other embodiments.
A kind of process flow for forming circulating type gate mos (GAA MOS) of disclosure of the invention,
The bottom circulating type gate mos (GAA MOS) parasitic metal oxide semiconductor of plane formula is solved with this
(MOS) problem.The circulating type gate mos (GAA MOS) of formation are three end structures, source region and drain region and body
Silicon substrate is completely isolated, does not need conventional injection to form well structure in body silicon substrate, solves bottom parasitic metal oxygen
The problem of compound semiconductor.
Specifically, the present invention in the formation process of existing fin formula field effect transistor (FinFET) by increasing by two
Processing step forms circulating type gate nanowire Metal Oxide Semiconductor Field Effect Transistor of the invention with this
(MOSFETs).In one example, described two processing steps include: step a), form SiGe/Si on a semiconductor substrate
Fin structure, wherein fin structure may include the multiple germanium-silicon layers and silicon layer for stacking setting between each other, for example, from down toward
On the germanium-silicon layer, silicon layer, germanium-silicon layer, silicon layer, the germanium-silicon layer ... that successively stack.Step b), in displacement metal gate process step,
Then the removal germanium-silicon layer of selectivity forms high-K metal gate in the germanium-silicon layer of removal and the position of dummy gate, in this way, high K
Metal gate is just around silicon layer, to form circulating type gate structure.
The work of formation circulating type gate nanowire Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) of the invention
Skill process including the following steps:
Step a) provides semiconductor substrate 100；
Semiconductor substrate 100 can be silicon, silicon-on-insulator (SOI), silicon (SSOI), insulator upper layer be laminated on insulator
At least one in folded SiGe and silicon (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI)
Kind.In one example, semiconductor substrate 100 is silicon substrate.
In one example, semiconductor substrate 100 may include NMOS area and PMOS area.
Conduction type in semiconductor devices mainly includes two kinds, it may be assumed that p-type doping and n-type doping.Wherein, p-type is adulterated
Main doped chemical includes boron (B) and phosphorus (P), and the main doped chemical of n-type doping is arsenic (As).According to the present invention one
In a example.Above-mentioned doping is realized generally by the method for injection.Required doping concentration is higher, then in injection process
Implantation dosage correspondingly also should be higher.
It can not include well structure in semiconductor substrate 100.
Step b) forms fin structure 200 in the semiconductor substrate 100；
As shown in Figure 1, fin structure 200 is the multiple material layers formed on a semiconductor substrate.In one example, institute
Stating multiple material layers includes first material layer 210 and second material layer 220, wherein first material layer 210 and second material layer
220 stack to be formed on a semiconductor substrate.The material of first material layer 210 and second material layer 220 is semiconductor material,
In one example, the material of first material layer 210 and second material layer 220 is SiGe, silicon materials or including SiGe, silicon materials,
In one example, the material of first material layer 210 can be for SiGe or including SiGe, and the material of second material layer 220 is silicon
Or including silicon materials.In one example, the germanium-silicon layer of fin structure 200 is formed on a semiconductor substrate, and silicon layer is formed in silicon
On germanium layer.Skilled person will appreciate that dawn, the number of the fin structure 200 formed on a semiconductor substrate can for one or
It is multiple.The base portion 240 of fin that further includes the steps that etching the semiconductor substrate in step b) and be formed, the multiple heap
Material layer repeatedly is formed on the base portion 240.
Fin structure 200 can be formed by any suitable technique, such as various sedimentations, photodevelopment technology and/or etching work
Skill.In one example, photodevelopment technology includes to form photoresist layer covering substrate, photoresist layer is made to be exposed under a pattern, carry out
One postexposure bake technique and to photoresist development (develop) to form shielding element comprising photoresist layer.Shielding
Element can then be used to fin structure 200 being etched into silicon layer.The etching of fin structure 200 can pass through reactive ion etch
(reactive ion etching；RIE) and/or other suitable etch process is completed.In one example, fin structure 200
It can be formed by one layer of silicon in etching substrate.This layer of silicon (can be covered in insulating layer for a silicon layer on semiconductor on insulator
On).Fin structure 200 also may include a coating being covered on fin.Coating can be a silicon covering layer.In other realities
It applies in example, the fin structure of multilayer parallel can also be formed by above-mentioned mode.
It in one example, further include the shape on the top surface and side wall of fin structure 200 after forming fin structure 200
The step of at oxide skin(coating) 230.
Spacer material layer a is formed on the surface of semiconductor substrate 100, the surface of spacer material layer a is lower than fin structure
200 top surface, the effect of spacer material layer a are the adjacent fin structures 200 of electric isolation, and the material of spacer material layer a can
Think silica, silicon nitride or silicon oxynitride.In one example, the material of spacer material layer a is silica.Spacer material layer
The forming process of a includes: firstly, then the spacer material layer a for forming covering semiconductor substrate 100 and fin structure 200 is adopted
Spacer material layer a is planarized with chemical mechanical milling tech, using the top surface of fin structure 200 as stop-layer, then, eatch-back
Removal part spacer material layer a is carved, spacer material layer a is formed.
It can be with doped p-type foreign ion or N-type impurity ion in fin structure 200.
Step c) is developed across the dummy gate 300 of the fin structure 200 in the fin structure 200；
As depicted in figs. 1 and 2, dummy gate 300 is formed in the top of the fin structure 200 stacked.Dummy gate
300 extending direction is vertical with the extending direction of fin structure 200 stacked.In one example, 300 shape of dummy gate
At on the top surface of oxide skin(coating) 230.Dummy gate 300 includes gate dielectric, workfunction layers and grid layer,
The two sides of dummy gate are provided with clearance wall 310.In one example, by suitable technique, in a manner of conforma layer, successively
Gate dielectric layer, workfunction layers and grid layer are above fin structure 200.
In one example, gate dielectric includes the stratified film of silicon oxide layer, silicon nitride layer or combinations thereof.Grid is situated between
The material of electric layer includes the dielectric material of high dielectric constant (high-k).In one example, the dielectric material of high dielectric constant
With greater than about 7.0 dielectric constant, including metal oxide or hafnium (Hf), aluminium (Al), zirconium (Zr), lanthanum (La), magnesium (Mg), barium
(Ba), titanium (Ti), the silicate of lead (Pb), its composition or the like.
After forming gate dielectric, workfunction layers are formed in the top of gate dielectric.The material of workfunction layers
Material includes TiN, TiAlC, TaSi, its composition or the like.
Then, the metal electrode layer of electric conductivity is formed in the top of workfunction layers by suitable depositing operation.Gold
Belong to electrode layer material include metal material, for example, TiN, TaN, TaC, Co, Ru, Al, or combinations thereof.
It in one example, further include that patterning gate dielectric, workfunction layers and grid layer, removal extend to
Part of grid pole dielectric layer, workfunction layers and grid layer between two adjacent wraparound-gate transistors, carry out shape with this
At the gate structure for surrounding nano wire respectively.
In one example, it is forming dummy gate 300 and after the clearance wall 310 of 300 two sides of dummy gate, is going back
Including expanding the source region of fin structure 200 and the processing step in drain region.
Step d) etches the part positioned at 300 two sides of dummy gate of the fin structure 200 to the semiconductor
The top surface of substrate；
As shown in Fig. 2, top surface of the part positioned at dummy gate two sides of etching fin structure 200 to base portion 240,
That is, the germanium-silicon layer and silicon layer positioned at 300 two sides of dummy gate are etched.In a subsequent step, exposing in base portion 240
Top surface on deposit the bottom isolation layer 400 of nappe silicon (that is, base portion 240 and substrate of the lower section of base portion 240), then
Epitaxial growth source region 500 and drain region 600 on bottom isolation layer 400, source region 500 and drain region 600 are from channel region extension, and and body
Silicon isolation.The a part of the fin structure 200 being etched is for the source region and drain region inside fin structure 200 or including fin
Source region and drain region inside structure 200.
Step e), the deposited bottom separation layer 400 on the top surface；
As shown in figure 3, bottom isolation layer 400 covers base portion 240 and spacer material layer a.In one example, bottom is isolated
Layer 400 is formed by the technique deposited, further includes the step of etch-back bottom isolation layer 400 after deposited bottom separation layer 400
Suddenly.
In one example, the material of bottom isolation layer 400 can be silica, silicon nitride or silicon oxynitride.
Step f), epitaxial growth source region 500 and drain region 600 on the bottom isolation layer 400.
As shown in figure 4, using epitaxial growth technology in 400 upper surface epitaxial growth source region 500 of bottom isolation layer and drain region
600.Source region 500 and drain region 600 are isolated from channel region extension, and with body silicon.Source region 500 and drain region 600 can be n-type doping or
P-type doping, specifically, epitaxy technique include being deposited on substrate crystalline lens covering.
Step g), the interlayer dielectric between the dummy gate, and grind the inter-level dielectric；
Step h) removes the part fin structure 200 of 300 lower section of the dummy gate 300 and the dummy gate；
As shown in figure 5, dummy gate 300 of the removal between clearance wall 310, and remove certain of fin structure 200
A or multiple material layers.In one example, the germanium-silicon layer of fin structure 200 being located at below silicon layer is removed.In an example
In, germanium-silicon layer can be removed by etching.Certainly, skilled person will appreciate that dawn, also can remove its of fin structure 200
Its layer or multiple layers.It in this step, further include this operation for the oxide skin(coating) that removal is located on the top surface of silicon layer.
Silicon layer is in hanging after etching, and hanging silicon layer is as nanowire structure.
It further include depositing on a semiconductor substrate before removal dummy gate 300 and the germanium-silicon layer of removal fin structure 200
The step of inter-level dielectric 700.In one example, one layer of erosion is formed in bottom isolation layer 400, source region and the top in drain region before this
Carve stop-layer 800, then the interlayer dielectric 700 on etching stopping layer 800.Inter-level dielectric 700 is between dummy gate 300
Between gap wall 310, and cover bottom isolation layer 400, source region 500 and drain region 600.The technique of interlayer dielectric 700 can be used
Current Conventional process steps, which is not described herein again.It further include etch-back inter-level dielectric 700 after interlayer dielectric 700
The step of.Current common process can be used in etch-back, is not repeating here.
Step i), the part fin structure below the dummy gate 300 and the dummy gate 300 of removal
200 position forms high-K metal gate 900, and the high-K metal gate 900 is around the portion of the fin structure 200 not being removed
Point, to form circulating type gate structure.
As shown in fig. 6, high-K metal gate 900 is formed between the clearance wall 310 of silicon layer and the lower section of silicon layer, high K
Silicon layer is surround by metal gate 900.
In one example, it is additionally provided with insulating layer 910 around high-K metal gate 900, the insulating layer 910 is by high-K metal gate
900 are isolated with the part below the germanium-silicon layer of surrounding clearance wall 310, source region 500, drain region 600 and fin structure 200.
Certainly, since fin structure 200 may include multiple material layers, and the property of can choose when removal fin structure 200
Removal some or multiple material layers therein, therefore, high-K metal gate 900 can be around other one or more material layers.
In one example, high-K metal gate 900 includes multi-functional function gate stack.
It after the above step further include chemical mechanical grinding step, contact hole forming step and the formation for replacing metal gate
Layers of copper and etc..
The present invention is by deposited bottom separation layer 400 with the silicon body region of covering device bottom-exposed source region 500 and drain region 600
Domain (that is, bulk silicon region of 600 lower section of source region 500 and drain region), to make source region 500 and the extension in drain region 600 from channel region
Domain growth, and be isolated with lower bulk silicon.Reduce source region 500 and the leakage current in body area is arrived in drain region 600.
The invention proposes the process flow for forming circulating type gate mos (GAA MOS), the techniques
Process solves the bottom circulating type gate mos (GAA MOS) parasitic metal oxide semiconductor of plane formula
(MOS) the problem of.The part for being located at dummy gate two sides by removing fin structure, and it is raw in the position extension of the part of removal
Before long source region and drain region, the deposited bottom separation layer on the top surface of grid two sides, so that bottom isolation layer covering device bottom
The body region of portion's exposure source region and drain region, the extension in source region and drain region are grown from channel region, with lower bulk separate from.The present invention
The circulating type gate mos (GAA MOS) for forming plane formula are 3 end structures, source region and drain region and body silicon substrate
It is completely isolated.Method of the invention is also apply to the resulting fin formula field effect transistor (Fin FET), is arrived with reducing source region and drain region
The leakage current in body area.
Wherein, Fig. 8 illustrates the process for being used to make semiconductor devices of the present embodiment, comprising the following steps:
Step a), provides semiconductor substrate；
Step b), forms fin structure on the semiconductor substrate；
Step c) is developed across the dummy gate of the fin structure in the fin structure；
Step d) etches the part positioned at the dummy gate two sides of the fin structure to the semiconductor substrate
Top surface；
Step e), the deposited bottom separation layer on the top surface；
Step f), epitaxial growth source region and drain region on the bottom isolation layer.
Embodiment two
The present invention also provides a kind of semiconductor devices made of method described in embodiment one, as shown in fig. 6, should
Semiconductor devices includes semiconductor substrate 100, the fin structure in formation semiconductor substrate 100, in fin structure 200
Grid and positioned at the bottom isolation layer of grid two sides and the source region on bottom isolation layer and drain region.The semiconductor devices
It is formed using the above method of the present invention.
Embodiment three
The present invention also provides a kind of electronic devices, including the semiconductor devices.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, Digital Frame, camera, video camera, recording pen, MP3, MP4, PSP is set
It is standby, it can also be any intermediate products including circuit.The electronic device of the embodiment of the present invention, due to having used above-mentioned circuit,
Thus there is better performance.
Wherein, Fig. 7 shows the example of mobile phone handsets.Mobile phone handsets 400, which are equipped with, to be included in shell 401
Display portion 402, operation button 403, external connection port 404, loudspeaker 405, microphone 406 etc..
Wherein the mobile phone handsets include the semiconductor devices, and the semiconductor devices is above-mentioned using the present invention
Method is formed.
The present invention is illustrated by above-mentioned example, but it is to be understood that, above-mentioned example is only intended to illustrate
With the purpose of explanation, and it is not intended to limit the invention in described example ranges.Furthermore those skilled in the art can be with
Understand, the invention is not limited to above-mentioned example, introduction according to the present invention can also make more kinds of modifications and repair
Change, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention is by attached power
Sharp claim and its equivalent scope are defined.
Claims (10)
1. a kind of production method of semiconductor devices, which comprises the following steps:
Step a), provides semiconductor substrate；
Step b), forms fin structure on the semiconductor substrate；
Step c) is developed across the dummy gate of the fin structure in the fin structure；
Step d) etches the part positioned at the dummy gate two sides of the fin structure to the top table of the semiconductor substrate
Face；
Step e), the deposited bottom separation layer on the top surface；
Step f), epitaxial growth source region and drain region on the bottom isolation layer.
2. manufacturing method according to claim 1, which is characterized in that further comprising the steps of after the step f):
Step g), the interlayer dielectric between the dummy gate, and grind the inter-level dielectric；
Step h) removes the part fin structure below the dummy gate and the dummy gate；
The position of step i), the part fin structure below the dummy gate and the dummy gate of removal are formed
High-K metal gate, the high-K metal gate is around the part of the fin structure not being removed, to form circulating type gate structure.
3. production method according to claim 2, which is characterized in that the fin structure includes multiple materials stacked
Layer.
4. production method according to claim 3, which is characterized in that the multiple material layer stacked includes germanium-silicon layer
And/or silicon layer.
5. production method according to claim 4, which is characterized in that the germanium-silicon layer and the silicon layer are from bottom to up successively
It stacks, in step h), removal is the germanium-silicon layer being located at below the silicon layer.
6. manufacturing method according to claim 1, which is characterized in that described virtual after forming the fin structure
Before grid is formed, further include the steps that forming oxide in the top surface of the fin structure and side.
7. manufacturing method according to claim 1, which is characterized in that after forming the dummy gate, further include
The two sides of the dummy gate form the step of clearance wall.
8. manufacturing method according to claim 1, which is characterized in that further include the shape on the surface of the semiconductor substrate
At there is the step of spacer material layer.
9. a kind of semiconductor devices that method according to claim 1 to 8 is prepared.
10. a kind of electronic device, which is characterized in that the electronic device includes semiconductor devices as claimed in claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810229806.6A CN110310893A (en) | 2018-03-20 | 2018-03-20 | A kind of production method of semiconductor devices, semiconductor devices and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810229806.6A CN110310893A (en) | 2018-03-20 | 2018-03-20 | A kind of production method of semiconductor devices, semiconductor devices and electronic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110310893A true CN110310893A (en) | 2019-10-08 |
Family
ID=68073495
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810229806.6A Pending CN110310893A (en) | 2018-03-20 | 2018-03-20 | A kind of production method of semiconductor devices, semiconductor devices and electronic device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110310893A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140084342A1 (en) * | 2012-09-27 | 2014-03-27 | Annalisa Cappellani | Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates |
| CN105552126A (en) * | 2015-12-15 | 2016-05-04 | 上海集成电路研发中心有限公司 | Finned-type field effect transistor and fabrication method thereof |
| US20160190243A1 (en) * | 2014-12-24 | 2016-06-30 | Taiwan Semiconductor Manufacturing Co., Ltd | Structure and formation method of finfet device |
| US20170141207A1 (en) * | 2015-11-13 | 2017-05-18 | International Business Machines Corporation | Nanosheet mosfet with full-height air-gap spacer |
| US9755017B1 (en) * | 2016-03-01 | 2017-09-05 | International Business Machines Corporation | Co-integration of silicon and silicon-germanium channels for nanosheet devices |
-
2018
- 2018-03-20 CN CN201810229806.6A patent/CN110310893A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140084342A1 (en) * | 2012-09-27 | 2014-03-27 | Annalisa Cappellani | Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates |
| US20160190243A1 (en) * | 2014-12-24 | 2016-06-30 | Taiwan Semiconductor Manufacturing Co., Ltd | Structure and formation method of finfet device |
| US20170141207A1 (en) * | 2015-11-13 | 2017-05-18 | International Business Machines Corporation | Nanosheet mosfet with full-height air-gap spacer |
| CN105552126A (en) * | 2015-12-15 | 2016-05-04 | 上海集成电路研发中心有限公司 | Finned-type field effect transistor and fabrication method thereof |
| US9755017B1 (en) * | 2016-03-01 | 2017-09-05 | International Business Machines Corporation | Co-integration of silicon and silicon-germanium channels for nanosheet devices |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20220328356A1 (en) | Mechanisms for Forming FinFET Device | |
| TWI673871B (en) | Techniques for integration of ge-rich p-mos source/drain contacts | |
| KR102178827B1 (en) | MOSFET(Metal-Oxide Semiconductor Field Effect Transistor), method for fabricating the same and semiconductor apparatus comprising the same | |
| US9865510B2 (en) | Device and methods for high-K and metal gate slacks | |
| TWI556322B (en) | Semiconductor devices and fabricating methods thereof using selectively regrown top contact | |
| TWI590337B (en) | Techniques for improving gate control over transistor channel by increasing effective gate length | |
| TW201905974A (en) | Semiconductor component and manufacturing method thereof | |
| US20140054717A1 (en) | Integration of multiple threshold voltage devices for complementary metal oxide semiconductor using full metal gate | |
| US8691651B2 (en) | Method of forming non-planar FET | |
| TW201342580A (en) | CMOS nanowire structure | |
| TW201736249A (en) | Nanowire transistor and method for fabricating the same | |
| CN103474397A (en) | Method of making a FINFET device | |
| TW201611289A (en) | Semiconductor device having germanium active layer with underlying diffusion barrier layer | |
| TWI787553B (en) | Semiconductor device and manufacturing method thereof | |
| US20200118888A1 (en) | Gate formation scheme for n-type and p-type transistors having separately tuned threshold voltages | |
| TW201911386A (en) | Semiconductor component and manufacturing method thereof | |
| CN106062963A (en) | Strain compensation in transistors | |
| CN109863606A (en) | Cause the semiconductor equipment of feature with fin end stress | |
| CN108288647A (en) | Ring gate nano line field-effect transistor and preparation method thereof | |
| CN106601741B (en) | A kind of semiconductor devices and preparation method thereof, electronic device | |
| CN110310893A (en) | A kind of production method of semiconductor devices, semiconductor devices and electronic device | |
| CN107978565B (en) | Semiconductor device, manufacturing method thereof and electronic device | |
| CN106601684B (en) | Semiconductor device, preparation method thereof and electronic device | |
| TWI527227B (en) | Semiconductor structure and process thereof | |
| TWI726338B (en) | Method for manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20191008 |