CN110309549B - Method for placing Fuse graph through Boolean operation - Google Patents
Method for placing Fuse graph through Boolean operation Download PDFInfo
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- CN110309549B CN110309549B CN201910484984.8A CN201910484984A CN110309549B CN 110309549 B CN110309549 B CN 110309549B CN 201910484984 A CN201910484984 A CN 201910484984A CN 110309549 B CN110309549 B CN 110309549B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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Abstract
The invention discloses a method for placing Fuse graphs through Boolean operation, which comprises the following steps: step one, defining a scribing groove graph; secondly, defining the layout of Fuse graphic units; step three, defining the distance between the scribing groove graph and the Fuse graph unit, and eliminating the island pattern through Boolean operation; and step four, combining the graphics after the Boolean operation with the chip main data. According to the invention, through Boolean operation, the scribing groove graph and the Fuse graph unit are automatically merged, the part which cannot be overlapped is removed, and manual cutting is not needed and whether the Fuse graph unit is correctly placed is confirmed.
Description
Technical Field
The invention relates to the field of semiconductor device manufacturing, in particular to a method for placing Fuse patterns through Boolean operation.
Background
The Fuse structure (Fuse) is a widely used circuit structure in a chip, and has many applications, for example, the circuit structure is protected from overcurrent or overload, and the Fuse structure is also used in some occasions sensitive to data protection, for example, after some data are written in some chips, the data in the chip are not expected to be read or damaged, the Fuse structure is adopted, after the data are written in the Fuse structure, the Fuse is blown by a certain method, for example, the Fuse is blown by a certain current and the time for controlling the current to pass, and the data channel between the internal data of the chip and the outside is cut off, so that the purpose of protecting the internal data of the chip can be achieved. The common application fields are some confidential data requirements, or are copyright type, or are prohibited from being modified by others, and the like.
A Fuse structure is often used in chip design, which maintains some signal connectivity during wafer testing and cuts off the path during packaging.
In many past products, fuse patterns are mainly placed manually, and scribing is performed through scribing grooves in the later period. As shown in fig. 1, the figure includes a scribe line and a Fuse pattern located at the center of the scribe line. The Fuse graph is placed at the center of the scribing groove and is removed in the later scribing process. Problems easily occur by manually placing the Fuse graphic, and since the Fuse graphic is small, omission easily occurs by visual inspection. At present, many defects of manually placing a Fuse pattern exist, and problems which are difficult to solve exist in the aspects of the whole production environment, materials, equipment, manpower, methods, measurement and the like, for example, the whole production environment has no internal data inspection flow of non-high-melting-point products, a detection tool cannot detect layers outside a damaged window of a wafer, manual inspection does not strictly detect a Fuse structure, and the like.
Disclosure of Invention
The invention aims to provide a method for placing Fuse graphs through Boolean operation.
In order to solve the above problem, the method for placing Fuse graphics through boolean operations according to the present invention includes:
step one, defining a scribing groove graph;
secondly, defining the layout of Fuse graphic units;
step three, defining the distance between the scribing groove graph and the Fuse graph unit, and eliminating the island pattern through Boolean operation;
and step four, combining the graphics after the Boolean operation with the chip main data.
Further, in the first step, a scribing groove pattern is placed in a scribing groove of the wafer.
Further, in the second step, the layout of the Fuse graphic unit is defined, and the placement area of the Fuse graphic is preliminarily determined in the scribing slot.
Further, in the third step, after the space between the scribing groove pattern and the Fuse pattern unit is defined, the size from the Fuse pattern unit area to the space is enlarged.
Furthermore, after the Fuse pattern unit area is enlarged to the defined space, an area which is not overlapped with other Fuse patterns is formed in the original Fuse pattern unit, and an island pattern is formed.
Further, in the third step, the boolean operation is a subtraction operation.
Furthermore, island patterns that do not overlap with other Fuse graphics units are eliminated by boolean operations.
Furthermore, the scribing groove graph and the Fuse graph unit belong to different layers.
Further, in the fourth step, the spacing between the scribe line pattern and the Fuse pattern unit is defined according to the width of the minimum island pattern.
According to the method for placing the Fuse graph through the Boolean operation, the scribing groove graph and the Fuse graph unit are automatically combined through the Boolean operation, the part which cannot be overlapped is removed, and the situation that whether the Fuse graph unit is placed correctly or not is determined without manually cutting is avoided.
Drawings
FIG. 1 is a schematic diagram of a scribe line and Fuse pattern.
FIG. 2 is a schematic diagram of the present invention defining a pattern of scribe lines.
FIG. 3 is a diagram illustrating the definition of Fuse graphic elements according to the present invention.
FIG. 4 is a schematic diagram of defining the spacing between the scribe line pattern and Fuse pattern unit and eliminating the island pattern by Boolean operation.
FIG. 5 is a schematic diagram of the combination of a Boolean operated Fuse graphic element with chip master data.
FIG. 6 is a schematic diagram of the Fuse pattern placed in different positions.
FIG. 7 is a flow chart of the method for placing Fuse graphics through Boolean operation according to the present invention.
Description of the preferred embodiment
Boolean operations are logical deductions of digital symbologies including union, intersection, subtraction. The logical operation method is introduced in the graphic processing operation, so that a simple basic graphic combination generates a new body, and the Boolean operation of a three-dimensional graphic is developed from a two-dimensional Boolean operation.
Because of the special contribution of boolean in symbolic logic operations, logic operations are referred to in many computer languages as boolean operations, the result of which is referred to as a boolean value.
Boolean operations have successfully established logical operations by studying logical problems mathematically. The judgment is expressed by an equation, and the inference is regarded as the transformation of the equation. The effectiveness of the transformation does not depend on the interpretation of the symbols and only on the combination rule of the symbols. This logic theory is often referred to as boolean algebra. In the 30's of the 20 th century, logic algebra was used in circuitry, and subsequently, due to the development of electronics and computers, a variety of complex and large systems appeared, and their transformation rules also followed those disclosed by boolean.
The method for placing the Fuse graph through Boolean operation is mainly used for solving the problem that the existing method for placing the Fuse graph in the scribing groove needs a large amount of manual operation, the large amount of Fuse graph needs to be placed manually, great inconvenience is brought to the manufacturing of the existing deep submicron and large-size wafer, and the accuracy is difficult to guarantee during error inspection, particularly visual inspection, because the size of the Fuse graph is generally extremely small.
The invention discloses a method for placing Fuse graphs through Boolean operation, which comprises the following steps:
step one, defining a scribing groove graph;
step two, defining the layout of Fuse graphic units;
step three, defining the distance between the scribing groove graph and the Fuse graph unit, and eliminating the island pattern through Boolean operation;
and step four, combining the graphics after Boolean operation with the chip main data.
Specifically, as shown in fig. 2, a scribe line pattern is first defined in a scribe line region on a wafer, and necessary scribe line patterns are placed in scribe lines. Since the scribing groove is relatively fine, only the scribing groove is shown in the figure, and the central line of the scribing groove becomes a routing line for subsequent scribing.
Then, as shown in fig. 3, the layout of the Fuse graphic element is defined, the placement area of the Fuse graphic element is preliminarily determined in the scribe line, and the preliminary placement of the Fuse graphic element is performed. The scribing groove pattern and the Fuse pattern belong to different layers.
After the distance D1 between the scribe line pattern and the Fuse pattern unit is preliminarily defined, as shown in fig. 4, the size of the distance D1 between the Fuse pattern unit area and the Fuse pattern unit area is enlarged.
After the Fuse graphic unit area is enlarged to the size of the defined distance D1, an area which is not overlapped with other Fuse graphics can be formed in the original Fuse graphic unit to form an island-type pattern, as shown in the middle diagram in FIG. 4, the scribing groove graphics and the Fuse graphics belong to different layers, when the Fuse graphic unit area is enlarged, the Fuse graphics are overlapped with other graphics step by step, and the remaining non-overlapped graphics become an isolated island-type pattern. Then, boolean operations of subtraction including union, intersection and subtraction are performed to combine simple basic graphics to generate new shapes. Island patterns that do not overlap with other Fuse graphics units are eliminated. The spacing between the scribe line pattern and Fuse pattern elements is defined according to the minimum width of the island pattern.
Through Boolean operation, the scribing groove graph and the Fuse graph unit are automatically merged, the part which cannot be overlapped is removed, and manual cutting is not needed to confirm whether the Fuse graph unit is placed correctly or not.
The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. A method for placing Fuse graphics through Boolean operation is characterized in that:
step one, defining a scribing groove graph;
secondly, defining the layout of Fuse graphic units;
step three, defining the space between the scribing groove graph and the Fuse graph unit, expanding the area of the Fuse graph unit to the size of the space, and eliminating the island pattern through the Boolean operation of subtraction operation;
after the area of the Fuse graphic unit is enlarged to the defined space, an area which is not overlapped with other Fuse graphics is formed in the original Fuse graphic unit to form an island-type pattern;
and step four, combining the graphics after Boolean operation with the chip main data.
2. The method of placing Fuse graphics by boolean operations as claimed in claim 1, characterized in that: in the first step, scribing groove graphs are placed in scribing grooves of the wafer, and layout of the scribing groove graphs is carried out.
3. The method of placing Fuse graphics via boolean operations as recited in claim 1, wherein: in the second step, the layout of the Fuse graphic unit is defined, and the placement area of the Fuse graphic is preliminarily determined in the scribing groove.
4. The method of placing Fuse graphics by boolean operations as claimed in claim 3, characterized in that: island patterns that do not overlap with other Fuse graphic units are eliminated by boolean operations.
5. The method of placing Fuse graphics by boolean operations as claimed in claim 1, characterized in that: the scribing groove graph and the Fuse graph unit belong to different layers.
6. The method of placing Fuse graphics by boolean operations as claimed in claim 1, characterized in that: in the fourth step, the space between the scribe line pattern and the Fuse pattern unit is defined according to the width of the minimum island pattern.
7. The method of placing Fuse graphics by boolean operations as claimed in claim 1, characterized in that: and through Boolean operation, automatically merging the scribing groove graph and the Fuse graph unit, and removing the part which cannot be overlapped without manually cutting off and confirming whether the Fuse graph unit is correctly placed.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101165888A (en) * | 2006-10-19 | 2008-04-23 | 国际商业机器公司 | Electrically programmable fuse sense circuit and method for sensing electrically programmable fuse state |
| CN101561796A (en) * | 2008-05-27 | 2009-10-21 | 威盛电子股份有限公司 | A micro processor and a method for writing a new value of a duplicable non volatile state of the micro processor thereof |
| CN108681623A (en) * | 2018-04-11 | 2018-10-19 | 上海华虹宏力半导体制造有限公司 | The method for placing scribe line figure |
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2019
- 2019-06-05 CN CN201910484984.8A patent/CN110309549B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101165888A (en) * | 2006-10-19 | 2008-04-23 | 国际商业机器公司 | Electrically programmable fuse sense circuit and method for sensing electrically programmable fuse state |
| CN101561796A (en) * | 2008-05-27 | 2009-10-21 | 威盛电子股份有限公司 | A micro processor and a method for writing a new value of a duplicable non volatile state of the micro processor thereof |
| CN108681623A (en) * | 2018-04-11 | 2018-10-19 | 上海华虹宏力半导体制造有限公司 | The method for placing scribe line figure |
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| FDM工艺中支撑添加技术的研究;彭安华等;《机床与液压》;20071231;第35卷(第12期) * |
| 分级式IC版图设计规则检查;李刚等;《上海交通大学学报》;19990131(第01期);全文 * |
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