CN110299914B

CN110299914B - Phase-locked loop circuit correction method, memory storage device and connection interface circuit

Info

Publication number: CN110299914B
Application number: CN201810232935.0A
Authority: CN
Inventors: 余家辉; 陈维咏
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2018-03-21
Filing date: 2018-03-21
Publication date: 2022-11-22
Anticipated expiration: 2038-03-21
Also published as: CN110299914A

Abstract

The invention provides a phase-locked loop circuit correction method, a memory storage device and a connection interface circuit, which are used for the memory storage device comprising a rewritable nonvolatile memory module. The method comprises the following steps: receiving a first signal from a host system; generating a dither signal by the memory storage device; generating a second signal according to the first signal and the jitter signal; performing, by a phase-locked loop circuit, a phase-locking operation on the second signal to generate a third signal; and detecting the third signal to correct an electrical parameter of the phase-locked loop circuit.

Description

Phase-locked loop circuit correction method, memory storage device and connection interface circuit

Technical Field

The present invention relates to a calibration mechanism of a Phase-locked loop (PLL) circuit, and more particularly, to a calibration method of a PLL circuit, a memory storage device and a connection interface circuit.

Background

The phase locked loop is widely applied in the communication field. In the phase-locked loop, the reference signal and the output signal can be locked at the same frequency and phase according to the feedback signal, so that the signal error generated by a receiving end circuit due to frequency offset generated in the signal transmission process is reduced. In some applications, the loop bandwidth (loop bandwidth) of the pll must be controlled within a specific range. However, the loop bandwidth of the pll is easily changed due to external environment (e.g., temperature), process error or voltage variation, so that the loop bandwidth of the pll is not easy to correct.

Disclosure of Invention

The invention provides a phase-locked loop circuit correction method, a memory storage device and a connection interface circuit, which can effectively correct the electrical parameters of a phase-locked loop.

An exemplary embodiment of the present invention provides a method for calibrating a phase-locked loop circuit, which is used in a memory storage device including a rewritable nonvolatile memory module, the method comprising: receiving a first signal from a host system; generating a dither signal by the memory storage device; generating a second signal according to the first signal and the jitter signal; performing, by a phase-locked loop circuit, a phase-locking operation on the second signal to generate a third signal; and detecting the third signal to correct an electrical parameter of the phase locked loop circuit.

In an exemplary embodiment of the invention, the step of detecting the third signal to correct the electrical parameter of the phase-locked loop circuit includes: and adjusting at least one circuit parameter of the phase-locked loop circuit to correct the loop bandwidth or the loop jitter peak value of the phase-locked loop circuit.

In an exemplary embodiment of the present invention, the step of adjusting the circuit parameters of the phase-locked loop circuit comprises: at least one of a current, an impedance, and a gain on a closed loop path of the phase locked loop circuit is adjusted.

In an exemplary embodiment of the present invention, the step of detecting the third signal to correct the electrical parameter of the phase-locked loop circuit comprises: detecting signal quality assessment information of the third signal; and correcting the electrical parameter of the phase locked loop circuit according to the signal quality evaluation information.

In an exemplary embodiment of the invention, the step of detecting the signal quality estimation information of the third signal comprises: obtaining a measurement value of the third signal, wherein the measurement value reflects one of an eye width of the third signal, an eye height of the third signal, and a jitter value of the third signal.

In an exemplary embodiment of the present invention, the step of detecting the third signal to correct the electrical parameter of the phase-locked loop circuit comprises: setting a frequency of the dither signal to a first frequency; obtaining a first measurement value of the third signal after performing the phase locking operation on the second signal generated according to the first signal and the jitter signal with the first frequency; determining a target value according to the first measurement value; setting the frequency of the dither signal to a second frequency, wherein the second frequency is different from the first frequency; obtaining a second measurement value of the third signal after performing the phase locking operation on a second signal generated according to the first signal and the jitter signal with the second frequency; and correcting the electrical parameter of the phase-locked loop circuit according to the target value and the second measurement value.

An exemplary embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The connection interface unit includes a phase locked loop circuit. The connection interface unit is used for receiving a first signal from the host computer system. The connection interface unit is further used for generating a jitter signal. The connection interface unit is further used for generating a second signal according to the first signal and the jitter signal. The phase-locked loop circuit is used for performing phase-locking operation on the second signal to generate a third signal. The connection interface unit is further configured to detect the third signal to correct an electrical parameter of the phase-locked loop circuit.

In an exemplary embodiment of the invention, the operation of the connection interface unit detecting the third signal to correct the electrical parameter of the phase-locked loop circuit includes: and adjusting at least one circuit parameter of the phase-locked loop circuit to correct the loop bandwidth or the loop jitter peak value of the phase-locked loop circuit.

In an exemplary embodiment of the present invention, the operation of the connection interface unit adjusting the circuit parameters of the phase-locked loop circuit includes: at least one of a current, an impedance, and a gain on a closed loop path of the phase locked loop circuit is adjusted.

In an exemplary embodiment of the invention, the operation of the connection interface unit detecting the third signal to correct the electrical parameter of the phase-locked loop circuit includes: detecting signal quality assessment information of the third signal; and correcting the electrical parameter of the phase-locked loop circuit according to the signal quality evaluation information.

In an exemplary embodiment of the present invention, the operation of the connection interface unit detecting the signal quality evaluation information of the third signal includes: obtaining a measurement value of the third signal, wherein the measurement value reflects one of an eye width of the third signal, an eye height of the third signal, and a jitter value of the third signal.

In an exemplary embodiment of the present invention, the operation of the connection interface unit detecting the third signal to correct the electrical parameter of the phase-locked loop circuit includes: setting a frequency of the dither signal to a first frequency; obtaining a first measurement value of the third signal after performing the phase locking operation on the second signal generated according to the first signal and the jitter signal with the first frequency; determining a target value according to the first measurement value; setting the frequency of the dither signal to a second frequency, wherein the second frequency is different from the first frequency; obtaining a second measurement value of the third signal after performing the phase locking operation on a second signal generated according to the first signal and the jitter signal with the second frequency; and correcting the electrical parameter of the phase-locked loop circuit according to the target value and the second measurement value.

An exemplary embodiment of the present invention provides a connection interface circuit for connecting a memory storage device to a host system, the connection interface circuit including a jitter control circuit, a jitter generation circuit, a phase-locked loop circuit, and a control circuit. The jitter control circuit is used for generating a jitter signal. The jitter generating circuit is connected with the jitter control circuit and is used for receiving a first signal from the host system and generating a second signal according to the first signal and the jitter signal. The phase-locked loop circuit is connected to the jitter generating circuit and is used for performing a phase-locking operation on the second signal to generate a third signal. The control circuit is connected to the phase-locked loop circuit and the jitter control circuit and is used for detecting the third signal to correct the electrical parameter of the phase-locked loop circuit.

In an exemplary embodiment of the present invention, a frequency of the dither signal is not higher than a frequency of the first signal.

In an exemplary embodiment of the present invention, the operation of the control circuit detecting the third signal to correct the electrical parameter of the phase-locked loop circuit includes: and adjusting at least one circuit parameter of the phase-locked loop circuit to correct the loop bandwidth or the loop jitter peak value of the phase-locked loop circuit.

In an exemplary embodiment of the present invention, the operation of the control circuit adjusting the circuit parameter of the phase-locked loop circuit includes: at least one of a current, an impedance, and a gain on a closed loop path of the phase locked loop circuit is adjusted.

In an exemplary embodiment of the present invention, the operation of the control circuit detecting the third signal to correct the electrical parameter of the phase-locked loop circuit includes: detecting signal quality assessment information of the third signal; and correcting the electrical parameter of the phase locked loop circuit according to the signal quality evaluation information.

In an exemplary embodiment of the present invention, the operation of the control circuit detecting the signal quality evaluation information of the third signal includes: obtaining a measurement value of the third signal, wherein the measurement value reflects one of an eye width of the third signal, an eye height of the third signal, and a jitter value of the third signal.

In an exemplary embodiment of the present invention, the operation of the control circuit detecting the third signal to correct the electrical parameter of the phase-locked loop circuit includes: setting a frequency of the dither signal to a first frequency; obtaining a first measurement value of the third signal after performing the phase locking operation on the second signal generated according to the first signal and the jitter signal with the first frequency; determining a target value according to the first measurement value; setting the frequency of the dither signal to a second frequency, wherein the second frequency is different from the first frequency; obtaining a second measurement value of the third signal after performing the phase locking operation on a second signal generated according to the first signal and the jitter signal with the second frequency; and correcting the electrical parameter of the phase-locked loop circuit according to the target value and the second measurement value.

In an exemplary embodiment of the invention, the first signal is an initial signal used to establish a connection between the host system and the memory storage device in a handshake phase.

In an exemplary embodiment of the invention, the first signal is a test signal for calibrating the phase-locked loop circuit in a test phase.

In an exemplary embodiment of the invention, the wobble signal is used to adjust the first signal such that at least one rising edge or at least one falling edge of the bitstream of the second signal is shifted in time by different amounts.

Based on the above, after receiving the first signal from the host system, the second signal may be generated according to the first signal and the jitter signal generated by the memory storage device itself. After performing a phase-locking operation on the second signal to generate a third signal, the third signal can be detected to correct an electrical parameter of the phase-locked loop circuit. Therefore, the correction efficiency of the electrical parameters of the phase-locked loop circuit can be improved.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a schematic diagram of a connection interface circuit according to an exemplary embodiment of the present invention.

Fig. 2 is a schematic diagram of a connection interface circuit according to another exemplary embodiment of the present invention.

Fig. 3A is a schematic diagram of a control circuit according to an exemplary embodiment of the present invention.

Fig. 3B is a diagram illustrating a third signal according to an exemplary embodiment of the invention.

Fig. 3C is a graph illustrating frequency versus measurement values according to an exemplary embodiment of the present invention.

Fig. 4 and 5 are schematic diagrams illustrating timing for performing calibration of the pll circuit according to an exemplary embodiment of the present invention.

Fig. 6 is a flowchart illustrating a calibration method of a pll circuit according to an exemplary embodiment of the invention.

FIG. 7 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the present invention.

FIG. 8 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the present invention.

FIG. 9 is a diagram illustrating a host system and a memory storage device according to another exemplary embodiment of the invention.

Fig. 10 is a schematic structural diagram of a memory storage device according to an exemplary embodiment of the invention.

Description of the reference numerals

10. 20: connection interface circuit

11. 22: jitter generation circuit

12. 23: phase-locked loop circuit

13. 24, 34: control circuit

14. 21: jitter control circuit

231: phase detector circuit

232: charge pump circuit

233: voltage controlled oscillator circuit

234: loop filter circuit

341: signal quality detection circuit

342: buffer device

343: decision circuit

S601: step (receiving a first signal from a host system)

S602: step (generating dither signal from memory storage device)

S603: step (generating a second signal based on the first signal and the dither signal)

S604: step (phase-locked operation is performed on the second signal by the phase-locked loop circuit to generate a third signal)

S605: step (detecting the third signal to correct the electrical parameters of the PLL circuit)

71. 91: host system

710: system bus

711: processor with a memory having a plurality of memory cells

712: random access memory

713: read-only memory

714: data transmission interface

72: input/output (I/O) device

80: motherboard with a memory card

801: u disk

802: memory card

803: solid state disk

804: wireless memory storage device

805: global positioning system module

806: network interface card

807: wireless transmission device

808: keyboard with a keyboard body

809: screen

810: horn (loudspeaker)

92: SD card

93: CF card

94: embedded storage device

941: embedded multimedia card

942: embedded multi-chip packaging storage device

1002: connection interface unit

1004: memory control circuit unit

1006: rewritable nonvolatile memory module

Detailed Description

In the following, a number of embodiments are presented to illustrate the invention, however, the invention is not limited to the illustrated embodiments. Appropriate combinations are also permitted between the embodiments. The term "coupled" as used throughout this specification, including the claims, may refer to any direct or indirect connection. For example, if a first device couples to a second device, that connection should be interpreted as either being a direct connection, or a indirect connection via other devices and some means of connection. Furthermore, the term "signal" may refer to at least one current, voltage, charge, temperature, data, or any other signal or signals.

Fig. 1 is a schematic diagram of a connection interface circuit according to an exemplary embodiment of the present invention. Referring to fig. 1, the connection interface circuit 10 includes a jitter generating circuit 11, a phase-locked loop circuit 12, a control circuit 13, and a jitter control circuit 14. The jitter generating circuit 11 is connected to the phase locked loop circuit 12 and the jitter control circuit 14. The control circuit 13 is connected to the phase-locked loop circuit 12 and the jitter control circuit 14.

The jitter control circuit 14 is configured to generate a signal (also referred to as a jitter signal) SJ and supply the signal SJ to the jitter generation circuit 11. The jitter generation circuit 11 may receive a signal (also referred to as a first signal) S1 and a signal SJ from the host system. In an exemplary embodiment, the signal S1 may be a differential (or non-differential) signal. For example, signal S1 may include two signals of the same amplitude but opposite phases. In an example embodiment, the signal SJ may be considered as artificially and/or intentionally generated noise. For example, the signal SJ may be a sine wave, a square wave, a triangular wave, or a signal having a fixed period combined from the above-described fundamental waves. In an exemplary embodiment, the frequency of signal SJ (also referred to as the clock frequency) is not higher than the frequency of signal S1. For example, the frequency of signal SJ may be 3.5MHz, and the frequency of signal S1 may be 100MHz. However, in another exemplary embodiment, the frequencies of the SJ and S1 signals can be adjusted according to actual requirements.

The jitter generation circuit 11 may generate a signal (also referred to as a second signal) S2 according to the signal S1 and the signal SJ. The jitter generating circuit 11 may adjust the signal S1 according to the signal SJ such that at least one rising edge or/and at least one falling edge of the bitstream of the signal S2 have different amounts of time shift. For example, the jitter generation circuit 11 may reflect the signal SJ to the signal S1 through a logic circuit element such as an adder (adder), an interpolator (interpolator), or a voltage controlled delay circuit to generate the signal S2. In other words, by reflecting signal SJ to signal S1, the frequency, amplitude, period, or other electrical parameter of signal S1 can be randomly changed.

The phase-locked loop circuit 12 may receive the signal S2 from the jitter generating circuit 11. The phase-locked loop circuit 12 may perform a phase-locking operation on the signal S2 to generate a signal (also referred to as a third signal) S3. For example, the pll circuit 12 is a feedback circuit, and the pll circuit 12 can lock the frequency and phase of the signals S2 and S3. For example, the frequency and phase of the signal S3 can be approximated to the frequency and phase of the signal S2 by the pll circuit 12.

The control circuit 13 can detect the signal S3 to correct electrical parameters such as loop bandwidth and/or loop jitter peak (loop jitter peaking) of the phase-locked loop circuit 12. For example, the control circuit 13 may output a signal (also referred to as a control signal) SC to the phase-locked loop circuit 12 in accordance with the detected signal S3. The signal SC is used to indicate the phase-locked loop circuit 12 to use or adjust a specific circuit parameter. Based on the signal SC, the phase-locked loop circuit 12 may automatically use or adjust certain circuit parameters to correct the electrical parameters of the phase-locked loop circuit 12. In addition, control circuit 13 may also control dither control circuit 14 to adjust the frequency, amplitude, period, or other electrical parameters of signal SJ.

Conventionally, electrical parameters such as loop bandwidth of the pll circuit 12 are easily changed by external environment (e.g. temperature), process error or voltage variation, so that loop bandwidth calibration of the pll is not easy. However, in the exemplary embodiment of fig. 1, after the signal SJ is reflected to the signal S1, the electrical parameters of the phase-locked loop circuit 12, such as the loop bandwidth and/or the loop jitter peak, can be effectively corrected by detecting the signal S3 and adjusting the circuit parameters of the phase-locked loop circuit 12 according to the detection result.

Fig. 2 is a schematic diagram of a connection interface circuit according to another exemplary embodiment of the present invention. Referring to fig. 2, the connection interface circuit 20 includes a jitter control circuit 21, a jitter generating circuit 22, a phase-locked loop circuit 23 and a control circuit 24. Dither control circuitry 21 is configured to provide signal SJ. For example, dither control circuitry 21 may be the same or similar to dither control circuitry 14 in the example embodiment of FIG. 1.

The jitter generation circuit 22 receives the signals S1 and SJ and generates a signal S2 according to the signals S1 and SJ. For example, jitter generation circuit 22 may reflect signal SJ to signal S1, thereby affecting the frequency, amplitude, period, or other electrical parameters of signal S2. In an exemplary embodiment, the jitter generating circuit 22 may include a voltage controlled delay circuit. The voltage controlled delay circuit may be a delay line (delay line) circuit and include a plurality of delay elements. The voltage control delay circuit may receive the signal S1 and delay the signal S1 according to the signal SJ to output a delayed signal S1 (i.e., the signal S2). Thus, signal SJ may be used to control the frequency, amplitude, period, or other electrical parameters of signal S1 (or signal S2).

The phase-locked loop circuit 23 includes a Phase Detector (PD) circuit 231, a Charge Pump (CP) circuit 232, a Voltage Controlled Oscillator (VCO) circuit 233, and a loop filter (LP) circuit 234. The charge pump circuit 232 is connected to the phase detector circuit 231, the voltage controlled oscillator circuit 233, and the loop filter circuit 234. The phase detector circuit 231 is used for comparing the phases of the signals S2 and S3. The charge pump circuit 232 is configured to output a signal Vout representing a boost (boost) or buck (buck) according to the comparison result of the phase detector circuit 231.

The loop filter circuit 234 is a Low Pass Filter (LPF) and is used to filter high frequency noise (high frequency noise) of the signal Vout. For example, the loop filter circuit 234 may include a resistor Rf and a capacitor Cf. A first terminal of the resistor Rf receives the signal Vout. A second terminal of the resistor Rf is connected to a first terminal of the capacitor Cf, and a second terminal of the capacitor Cf is connected to a reference potential (e.g., ground). It should be noted that, in another exemplary embodiment, the circuit structure of the loop filter circuit 234 may be adjusted according to actual requirements.

The vco circuit 233 is used for outputting a signal S3 according to the signal Vout, and a frequency of the signal S3 is controlled by the signal Vout. For example, when the voltage of the signal Vout increases, the frequency of the signal S3 may increase. When the voltage of the signal Vout decreases, the frequency of the signal S3 may decrease. In addition, the voltage controlled oscillator circuit 233 may feed back the signal S3 to the phase detector circuit 231.

The control circuit 24 is used for detecting the signal S3. In an exemplary embodiment, the control circuit 13 may detect the signal quality evaluation information of the signal S3. For example, the control circuit 13 may detect the signal S3 and obtain a measurement value of the signal S3 as signal quality evaluation information of the signal S3. The measurement value may reflect at least one of an eye width (eye width) of the signal S3, an eye height (eye high) of the signal S3, and a jitter value (or jitter magnitude) of the signal S3.

In general, the wider the eye width and/or the wider the eye height of the signal S3, the easier and more accurate the sampling of the signal S3. Conversely, the narrower the eye width and/or the narrower the eye height of the signal S3, the more difficult and inaccurate the sampling of the signal S3. For example, the eye width and/or eye height of the signal S3 may be obtained by tracing an eye diagram of the signal S3 or performing other signal analysis means on the signal S3.

Based on the signal quality evaluation information of the signal S3, the control circuit 24 may output a signal SC. Based on the signal SC, specific circuit parameters of the pll circuit 23 can be adjusted. For example, at least one of a current, an impedance, and a gain on a closed loop (close loop) path of the phase locked loop circuit 23 may be adjusted according to the signal SC. Taking fig. 2 as an example, the phase detector circuit 231, the charge pump circuit 232, the vco circuit 233 and the loop filter circuit 234 are all located on the closed loop path of the pll circuit 23. Therefore, according to the signal SC, the gain (Kpd) of the phase detector circuit 231, the current (Icp) flowing through the charge pump circuit 232, the impedance of the loop filter circuit 234 and/or the gain (Kvco) of the tuning vco circuit 233 can be adjusted to correct the electrical parameters of the phase-locked loop circuit 23, such as the loop bandwidth and/or the loop jitter peak.

Fig. 3A is a schematic diagram of a control circuit according to an exemplary embodiment of the present invention. Referring to fig. 2 and fig. 3A, the control circuit 34 includes a signal quality detection circuit 341, a buffer 342, and a decision circuit 343. The signal quality detecting circuit 341 is connected to the buffer 342 and the decision circuit 343. The signal quality detecting circuit 341 is configured to receive the signal S3 and analyze the signal S3 to obtain a measurement value (i.e., signal quality estimation information) of the signal S3.

In calibrating the phase-locked loop circuit 23, the decision circuit 343 may generate a signal SC indicating that different circuit parameters are used. In addition, the decision circuit 343 may also adjust the frequency of the signal SJ when the pll circuit 23 is calibrated. At least one of the eye width, eye height, and jitter values of signal S3 may be changed correspondingly, corresponding to the particular circuit parameters of phase-locked loop circuit 23 being changed and/or the frequency of signal SJ being adjusted. The signal quality detecting circuit 341 may continuously detect and analyze the signal S3 and obtain a corresponding measurement value. The signal quality detection circuit 341 may pair the measured measurement values with the parameter settings (e.g., circuit parameters and/or frequency of the signal SJ) used at that time and store the paired measurement values in the buffer 342. The decision circuit 343 may read and compare the stored measurement values from the buffer 342. After continuously adjusting the specific circuit parameters of the pll circuit 23 and/or the frequency of the signal SJ, the decision circuit 343 may generate the signal SC according to the measurement value stored in the buffer 342. For example, according to the signal SC generated by a certain measurement value (e.g., a maximum eye width value, a maximum eye height value, or a minimum jitter value) stored in the buffer 342, the decision circuit 343 may instruct the pll circuit 23 to use a specific circuit parameter (e.g., adjust the gain of the vco circuit 233 to a specific value) to stabilize the loop bandwidth of the pll circuit 23 and/or control the loop bandwidth of the pll circuit 23 within a specific range.

In the example embodiments of fig. 2 and 3, the decision circuit 343 may instruct the jitter control circuit 21 to set the frequency of the signal SJ to a certain frequency (also referred to as a first frequency). Based on the signal S1 and the signal SJ having the first frequency, the jitter generation circuit 22 may generate a signal S2. The phase-locked loop circuit 23 may perform a phase-locking operation on the signal S2 to generate the signal S3. The signal quality detection circuit 341 may analyze the signal S3 to obtain a measurement value (also referred to as a first measurement value) of the signal S3 and record the first measurement value in the buffer 342. This first measurement value may reflect an eye width, eye height, or jitter value of a third signal (or a second signal) generated based on using the signal SJ having the first frequency.

After obtaining the first measurement value, the decision circuit 343 may determine a target value according to the first measurement value and record the target value in the buffer 342. Then, the decision circuit 343 may instruct the jitter control circuit 21 to set the frequency of the signal SJ to another frequency (also referred to as a second frequency). Based on the signal S1 and the signal SJ having the second frequency, the jitter generation circuit 22 may generate the signal S2. The phase-locked loop circuit 23 may perform a phase-locking operation on the signal S2 to generate the signal S3. The signal quality detection circuit 341 may analyze the signal S3 to obtain another measurement value (also referred to as a second measurement value) of the signal S3 and record the second measurement value in the buffer 342. This second measurement value may reflect an eye width, eye height, or jitter value of a third signal (or a second signal) generated based on using the signal SJ having the second frequency. The decision circuit 343 can correct the electrical parameter of the pll circuit 23 according to the target value and the second measurement value.

Fig. 3B is a diagram illustrating a third signal according to an exemplary embodiment of the invention. Fig. 3C is a graph illustrating frequency versus measurement values according to an exemplary embodiment of the present invention.

Referring to fig. 3B and 3C, for one eye of the signal S3, the pulse width UI is equal to the sum of the eye width EW and the jitter value (G1 + G2). The hatched (or jittered) portion in fig. 3B represents the jitter of the signal S3. The first frequency (e.g., 1 MHz) corresponds to a power of 0db (low frequency). The second frequency (e.g., 3.5 MHz) corresponds to a power of-3 db (target bandwidth). The first measurement value reflects a jitter value of a third signal generated based on using the signal SJ having the first frequency. The second measurement value reflects a jitter value of a third signal generated based on using the signal SJ having the second frequency. Assuming that the first measurement value measured when the frequency of the signal SJ is the first frequency is 100 picoseconds (picosecond), the first measurement value may be multiplied by 0.707 (-3 db) to obtain a target value of 70 picoseconds.

After adjusting the frequency of the SJ signal to the second frequency and measuring the second measurement value, one or more circuit parameters of the phase-locked loop circuit 23 may be continuously adjusted if the second measurement value is not equal to (or close to) the target value. After adjusting one or more circuit parameters of the pll circuit 23, if the measured second measurement value is equal to (or close to) the target value, it indicates that the correction of the electrical parameters of the pll circuit 23, such as the loop bandwidth and/or the loop jitter peak, is completed.

In the example embodiment of fig. 3A, the signal quality detection circuit 341 may include an eye width detector and/or an eye height detector. Further, the

control circuit

13, 24 or 34 may include logic circuit elements such as sampling circuits, flip-flops, comparators, microprocessors, microcontrollers and/or embedded controllers to implement the aforementioned functions.

It should be noted that, although the exemplary embodiments of fig. 3B and 3C use the jitter value of the third signal as the example of the signal quality estimation information, the invention is not limited to the type of the signal quality estimation information. In another exemplary embodiment, the remaining information related to the signal quality of the third signal (the eye width or the eye height of the third signal) can be used as the signal quality estimation information. As the type of signal quality assessment information changes, the internal circuitry of the control circuit and its function may also change accordingly. In addition, the connection relationship of the circuit elements in the foregoing exemplary embodiments is only exemplary and is not intended to limit the present invention. In another exemplary embodiment, more circuit elements may be added to the connection interface circuit to provide additional functionality, depending on the actual requirements.

In the foregoing exemplary embodiments, the connection interface circuits 10 and/or 20 may be disposed in the memory storage device to receive the signal S1 from the host system. Fig. 4 and 5 are schematic diagrams illustrating timing for performing calibration of the pll circuit according to an exemplary embodiment of the present invention. In an exemplary embodiment, the calibration operation of the pll circuits 12 and/or 23 may be performed during a test phase of the memory storage device itself, as shown in fig. 4. For example, the testing stage may be before the memory storage device is shipped or maintained. In the exemplary embodiment of fig. 4, the host system is, for example, a test host, and the signal S1 is, for example, a test signal for calibrating the pll circuit 12 and/or 23 during this test phase.

In an exemplary embodiment, the calibration operation of the pll circuit 12 and/or 23 may be performed during a handshake phase between the memory storage device and the host system (i.e., between time points T0 and T1), as shown in fig. 5. During the handshake phase, the memory storage device and the host system transmit an initial signal (also referred to as a handshake signal) to establish a connection therebetween. In other words, in the exemplary embodiment of fig. 5, the transmitted signal S1 is an initial signal for establishing a connection between the host system and the memory storage device in the handshake phase. After the handshake phase is completed (i.e., after time point T1), the transmit phase (i.e., between time points T1-T2) may be entered. In the transmission phase, the memory storage device may utilize the calibrated PLL circuit 12 and/or 23 to resolve data signals from the host system.

Fig. 6 is a flowchart illustrating a phase-locked loop circuit calibration method according to an exemplary embodiment of the invention. Referring to fig. 6, in step S601, a first signal is received from a host system. In step S602, a dither signal is generated from a memory storage device. In step S603, a second signal is generated according to the first signal and the wobble signal. In step S604, a phase-locked operation is performed on the second signal by the phase-locked loop circuit to generate a third signal. In step S605, the third signal is detected to correct an electrical parameter of the phase-locked loop circuit.

However, the steps in fig. 6 have been described in detail above, and are not described again here. It is to be noted that, the steps in fig. 6 can be actually manufactured as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the method of fig. 6 may be used with the above exemplary embodiments, or may be used alone, and the invention is not limited thereto.

Generally, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also called a control circuit). Memory storage devices are typically used with a host system so that the host system can write data to or read data from the memory storage device.

FIG. 7 is a diagram illustrating a host system memory storage device and an input/output (I/O) device according to an exemplary embodiment of the invention. FIG. 8 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the present invention.

Referring to fig. 7 and 8, the host system 71 generally includes a processor 711, a Random Access Memory (RAM) 712, a Read Only Memory (ROM) 713, and a data transmission interface 714. The processor 711, the random access memory 712, the read only memory 713, and the data transfer interface 714 are all coupled to a system bus 710.

In the exemplary embodiment, the host system 71 is connected to the memory storage device 70 through the data transmission interface 714. For example, the host system 71 can store data to the memory storage device 70 or read data from the memory storage device 70 via the data transmission interface 714. The host system 71 is connected to the I/O device 72 via a system bus 710. For example, the host system 71 may transmit output signals to the I/O device 72 or receive input signals from the I/O device 72 via the system bus 710.

In the present exemplary embodiment, the processor 711, the ram 712, the rom 713 and the data transmission interface 714 may be disposed on the motherboard 80 of the host system 71. The number of data transfer interfaces 714 may be one or more. The motherboard 80 can be connected to the memory storage device 70 via a wired or wireless connection via the data transmission interface 714. The memory storage device 70 can be, for example, a usb disk 801, a memory card 802, a Solid State Drive (SSD) 803, or a wireless memory storage device 804. The wireless memory storage device 804 can be, for example, a Near Field Communication (NFC) memory storage device, a wireless facsimile (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a low power Bluetooth memory storage device (e.g., iBeacon) based memory storage device based on various wireless Communication technologies. In addition, the motherboard 80 may also be connected to various I/O devices such as a Global Positioning System (GPS) module 805, a network interface card 806, a wireless transmission device 807, a keyboard 808, a screen 809, and a speaker 810 via a System bus 710. For example, in one exemplary embodiment, the motherboard 80 can access the wireless memory storage device 804 via the wireless transmission device 807.

In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 9 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 9, in another exemplary embodiment, the host system 91 may be a Digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 90 may be various non-volatile memory storage devices such as a Secure Digital (SD) card 92, a Compact Flash (CF) card 93, or an embedded storage device 94. The embedded storage device 94 includes embedded Multi Media Card (eMMC) 941 and/or embedded Multi Chip Package (eMCP) 942, which connect the memory module directly to the embedded storage device on the substrate of the host system.

FIG. 10 is a block diagram of a memory storage device according to an exemplary embodiment of the invention.

Referring to fig. 10, the memory storage device 1000 includes a connection interface unit 1002, a memory control circuit unit 1004, and a rewritable nonvolatile memory module 1006. It is noted that the connection interface unit 1002 may include the connection interface circuit 10 in the example embodiment of FIG. 1 or the connection interface circuit 20 in the example embodiment of FIG. 2.

The connection interface unit 1002 is used to connect the memory storage device 70 to the host system 71. In the exemplary embodiment, connection interface unit 1002 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 1002 may also be compliant with Parallel Advanced Technology Attachment (PATA) standard, institute of Electrical and Electronic Engineers (IEEE) 1394 standard, high-Speed Peripheral Component connection interface (PCI Express) standard, universal Serial Bus (USB) standard, SD interface standard, ultra High Speed-I (UHS-I) interface standard, ultra High Speed-II (UHS-II) interface standard, memory Stick (Memory Stick, MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, universal Flash Storage (Flash) interface standard, CF interface standard, cp standard, device interface (Integrated drive Electronics) standard, or other suitable integration standard. The connection interface unit 1002 may be packaged with the memory control circuit unit 1004 in one chip, or the connection interface unit 1002 may be disposed outside of a chip including the memory control circuit unit 1004.

The memory control circuit unit 1004 is used for executing a plurality of logic gates or control commands actually manufactured in a hardware type or a firmware type and performing operations such as writing, reading and erasing of data in the rewritable nonvolatile memory module 1006 according to commands of the host system 71.

The rewritable nonvolatile memory module 1006 is connected to the memory control circuit unit 1004 and is used for storing data written by the host system 71. The rewritable non-volatile memory module 1006 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module capable of storing 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 bits in one memory Cell), a multiple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits in one memory Cell), other flash memory modules, or other memory modules with the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 1006 stores one or more bits with a change in voltage (hereinafter also referred to as threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 1006 has a plurality of storage states. The read voltage is applied to determine which storage state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.

In the present exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 1006 form a plurality of physical programming units, and the physical programming units form a plurality of physical erasing units. Specifically, the memory cells on the same word line constitute one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be classified into at least a lower physical programming unit and an upper physical programming unit. For example, the Least Significant Bit (LSB) of a memory cell belongs to the lower physical program unit, and the Most Significant Bit (MSB) of a memory cell belongs to the upper physical program unit. Generally, in the MLC NAND flash memory, the writing speed of the bottom-side physical programming cell is faster than that of the top-side physical programming cell, and/or the reliability of the bottom-side physical programming cell is higher than that of the top-side physical programming cell.

In the present exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit is a physical page (page) or a physical fan (sector). If the physical program cells are physical pages, the physical program cells usually include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundancy bit region stores system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit area includes 32 physical fans, and the size of one physical fan is 512 bytes (B). However, in other example embodiments, the data bit region may also include 8, 16, or a greater or lesser number of physical fans, and the size of each physical fan may also be greater or lesser. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. For example, the physical erase unit is a physical block (block).

In summary, after receiving the first signal from the host system, the second signal can be generated according to the first signal and the jitter signal generated by the memory storage device itself. After performing a phase-locking operation on the second signal to generate a third signal, the third signal can be detected to correct an electrical parameter of the phase-locked loop circuit. Therefore, the correction efficiency of the electrical parameters of the phase-locked loop circuit can be improved.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A phase-locked loop circuit calibration method is used for a memory storage device comprising a rewritable nonvolatile memory module, and comprises the following steps:

receiving a first signal from a host system;

generating, by the memory storage device, a dither signal;

generating a second signal according to the first signal and the jitter signal;

performing, by a phase-locked loop circuit, a phase-locking operation on the second signal to generate a third signal; and

detecting the third signal to correct an electrical parameter of the phase locked loop circuit,

the first signal is an initial signal used for establishing a connection between the host system and the memory storage device in a handshake phase.

2. The phase-locked loop circuit correction method as recited in claim 1, wherein a frequency of the dither signal is not higher than a frequency of the first signal.

3. The phase-locked loop circuit calibration method of claim 1, wherein the step of detecting the third signal to calibrate the electrical parameter of the phase-locked loop circuit comprises:

and adjusting at least one circuit parameter of the phase-locked loop circuit to correct the loop bandwidth or the loop jitter peak value of the phase-locked loop circuit.

4. The method according to claim 3, wherein the step of adjusting the at least one circuit parameter of the phase-locked loop circuit comprises:

at least one of a current, an impedance, and a gain on a closed loop path of the phase locked loop circuit is adjusted.

5. The phase-locked loop circuit calibration method of claim 1, wherein the step of detecting the third signal to calibrate the electrical parameter of the phase-locked loop circuit comprises:

detecting signal quality assessment information of the third signal; and

correcting the electrical parameter of the phase-locked loop circuit according to the signal quality evaluation information.

6. The phase-locked loop circuit calibration method of claim 5, wherein the step of detecting the signal quality assessment information of the third signal comprises:

obtaining a measurement value of the third signal, wherein the measurement value reflects one of an eye width of the third signal, an eye height of the third signal, and a jitter value of the third signal.

7. The phase-locked loop circuit correction method as recited in claim 1, wherein the step of detecting the third signal to correct the electrical parameter of the phase-locked loop circuit comprises:

setting a frequency of the dither signal to a first frequency;

obtaining a first measurement value of the third signal after performing the phase locking operation on the second signal generated according to the first signal and the jitter signal with the first frequency;

determining a target value according to the first measurement value;

setting the frequency of the dither signal to a second frequency, wherein the second frequency is different from the first frequency;

obtaining a second measurement value of the third signal after performing the phase locking operation on a second signal generated according to the first signal and the jitter signal with the second frequency; and

and correcting the electrical parameter of the phase-locked loop circuit according to the target value and the second measurement value.

8. The method according to claim 1, wherein the first signal further comprises a test signal used to calibrate the phase-locked loop circuit during a test phase.

9. The method according to claim 1, wherein the dither signal is used to adjust the first signal such that at least a rising edge or at least a falling edge of a bit stream of the second signal is time-shifted by a different amount.

10. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

a rewritable non-volatile memory module; and

a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the connection interface unit includes a phase locked loop circuit,

wherein the connection interface unit is configured to receive a first signal from the host system,

wherein the connection interface unit is further configured to generate a dithering signal,

wherein the connection interface unit is further configured to generate a second signal according to the first signal and the jitter signal,

wherein the phase-locked loop circuit is configured to perform a phase-locking operation on the second signal to generate a third signal,

wherein the connection interface unit is further configured to detect the third signal to correct an electrical parameter of the phase-locked loop circuit,

11. The memory storage device of claim 10, wherein a frequency of the dither signal is not higher than a frequency of the first signal.

12. The memory storage device of claim 10, wherein the operation of the connection interface unit detecting the third signal to correct the electrical parameter of the phase-locked loop circuit comprises:

13. The memory storage device of claim 12, wherein the operation of the connection interface unit adjusting the at least one circuit parameter of the phase-locked loop circuit comprises:

14. The memory storage device of claim 10, wherein the operation of the connection interface unit detecting the third signal to correct the electrical parameter of the phase-locked loop circuit comprises:

detecting signal quality assessment information of the third signal; and

correcting the electrical parameter of the phase locked loop circuit according to the signal quality assessment information.

15. The memory storage device of claim 14, wherein the operation of the connection interface unit detecting the signal quality assessment information of the third signal comprises:

16. The memory storage device of claim 10, wherein the operation of the connection interface unit detecting the third signal to correct the electrical parameter of the phase-locked loop circuit comprises:

setting a frequency of the dither signal to a first frequency;

determining a target value according to the first measurement value;

17. The memory storage device of claim 10, wherein the first signal further comprises a test signal used to calibrate the phase locked loop circuit during a test phase.

18. The memory storage device of claim 10, wherein the dither signal is used to adjust the first signal such that at least a rising edge or at least a falling edge of a bitstream of the second signal is displaced in time by a different amount.

19. A connection interface circuit for connecting a memory storage device to a host system, the connection interface circuit comprising:

a jitter control circuit for generating a jitter signal;

a jitter generating circuit connected to the jitter control circuit and configured to receive a first signal from the host system and generate a second signal according to the first signal and the jitter signal;

a phase-locked loop circuit connected to the jitter generating circuit and configured to perform a phase-locked operation on the second signal to generate a third signal; and

a control circuit connected to the phase-locked loop circuit and the jitter control circuit and configured to detect the third signal to correct an electrical parameter of the phase-locked loop circuit,

20. The connection interface circuit of claim 19, wherein the frequency of the dither signal is no higher than the frequency of the first signal.

21. The connection interface circuit of claim 19, wherein the operation of the control circuit to detect the third signal to correct the electrical parameter of the phase-locked loop circuit comprises:

22. The connection interface circuit of claim 21, wherein the operation of the control circuit to adjust the at least one circuit parameter of the phase-locked loop circuit comprises:

23. The connection interface circuit of claim 19, wherein the operation of the control circuit to detect the third signal to correct the electrical parameter of the phase-locked loop circuit comprises:

detecting signal quality assessment information of the third signal; and

24. The connection interface circuit of claim 23, wherein the operation of the control circuit to detect the signal quality assessment information for the third signal comprises:

25. The connection interface circuit of claim 19, wherein the operation of the control circuit to detect the third signal to correct the electrical parameter of the phase-locked loop circuit comprises:

setting a frequency of the dither signal to a first frequency;

determining a target value according to the first measurement value;

and correcting the electrical parameter of the phase-locked loop circuit according to the target value and the second measuring value.

26. The connection interface circuit of claim 19, wherein the first signal further comprises a test signal used to calibrate the phase-locked loop circuit during a test phase.

27. The connection interface circuit of claim 19, wherein the dither signal is used to adjust the first signal such that at least a rising edge or at least a falling edge of a bitstream of the second signal is time-shifted by different amounts.