CN102195640A - Phase lock loop (PLL) device and control method thereof - Google Patents
Phase lock loop (PLL) device and control method thereof Download PDFInfo
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- CN102195640A CN102195640A CN2010101342718A CN201010134271A CN102195640A CN 102195640 A CN102195640 A CN 102195640A CN 2010101342718 A CN2010101342718 A CN 2010101342718A CN 201010134271 A CN201010134271 A CN 201010134271A CN 102195640 A CN102195640 A CN 102195640A
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Abstract
The invention discloses a phase lock loop (PLL) device and a control method thereof. The PLL device comprises a PLL circuit and a storage unit, wherein, the PLL circuit generates a phase lock clock signal according to a control voltage; and the storage unit is coupled with the PLL circuit and provides an initial signal to the PLL circuit according to a digital value when the PLL circuit is started so as to restore the control voltage to a preset value.
Description
Technical field
The invention relates to a kind of PLL device, particularly about a kind of locking time of short PLL device.
Background technology
Figure 1A is known phase-locked loop (Phase lock loop; PLL) schematic representation of apparatus.PLL device 10 includes phase detectors (Phase detector) 11, charge pump (Charge pump) 12, loop filter (Loop filter) 13, voltage controlled oscillator (Voltage control oscillator; VCO) 14 and frequency eliminator (Divider) 15.The phase-locked clock signal that frequency eliminator 15 produces voltage controlled oscillator 14 in addition feeds back to phase detectors 11 behind the frequency elimination, phase detectors 11 according to phase detection result provide control signal to electric charge mercury 12 to produce Control current, this Control current discharges and recharges via 13 pairs of capacitor C 1 of loop filter and C2, on node 132, produce voltage Vc, offer voltage controlled oscillator 14.PLL device 10 can need one period locking time from the frequency lock that starts to its signal at every turn, voltage charging on the node 132 is reached desired value, generally begin charging by 0V or VDD, please consult Figure 1B simultaneously, this sentences from 0V and begins to be charged as the example explanation, voltage on the node 132 is when charging arrives default target voltage Vc at leisure by zero beginning, the phase-locked clock signal of PLL device 10 outputs just reaches desired value Fvco and locking frequency, needing through length before reaching frequency lock is the locking time of t1, therefore known PLL device 10 is when each the startup, all need just can reach frequency lock, drag the speed of slow whole system through tediously long locking time.
Summary of the invention
One of purpose of the present invention is to provide a kind of PLL device, and it can restart behind power-off fast.
One of purpose of the present invention is to provide a kind of PLL device with quick turnaround time.
One embodiment of the invention provide a kind of PLL device.This PLL device includes a phase-locked loop circuit and a memory cell.Phase-locked loop circuit produces a phase-locked clock signal according to a control voltage.Memory cell couples this lock loop circuit, when phase-locked loop circuit starts, provides an initialize signal to phase-locked loop circuit according to a digital value, makes control voltage return to a preset value.
Another embodiment of the present invention provides a kind of circuit of storing control voltage and locking frequency signal.This circuit includes a VCO and swings device, a memory cell and a control circuit.Voltage controlled oscillator produces a frequency signal according to a control voltage.One control circuit produces control voltage according to an initialize signal, and when the frequency of frequency signal changes, adjusts control voltage accordingly, frequency signal is locked to a preset value.Memory cell is in order to storing the digital value of control voltage after conversion, and provides one in fact to equal control the initialize signal of voltage to control circuit according to this place value in one during default.
Another embodiment of the present invention provides a kind of PLL device.This PLL device includes phase detectors, a charge pump, a loop filter, a voltage controlled oscillator and a memory cell.These phase detectors detect the phase difference value of a reference signal and a phase-locked clock signal, produce a control signal according to the phase difference value.Charge pump produces a Control current according to control signal.
Loop filter produces one first control voltage according to Control current.Memory cell couples a node, the first control voltage is saved as a digital value during default in one first, and produces an initialize signal according to digital value in one second during default.Voltage controlled oscillator couples this node, produces this phase-locked clock signal according to the first control voltage during default in first, and produces this phase-locked clock signal according to this initialize signal in second during default.
Another embodiment of the present invention provides a kind of control method of PLL device.This method includes the following step: at first, provide a control voltage to a phase-locked loop.Produce a phase-locked clock signal according to control voltage, and produce a digital value according to control voltage.Then, store this digital value.And when starting, digital value is converted to an initialize signal gives PLL device, so that control voltage to be provided in the phase-locked loop.
Another embodiment of the present invention provides a kind of control method of PLL device.This method includes the following step: at first, produce an initialize signal according to a preset number value.Then, make a control voltage return to a preset value according to initialize signal, and will control voltage and offer a phase-locked loop.Afterwards, produce a phase-locked clock signal according to control voltage.
The PLL device of the embodiment of the invention and its control method, utilize the digital value after cell stores is controlled voltage transitions, and PLL device through close to restart before or simultaneously, produce control voltage according to digital value and carry out frequency lock fast, produce the phase-locked clock signal.Not must as the known technology when PLL device the restarting after for the second time, spended time repeats charge/discharge.Therefore, PLL device of the present invention and its control method can solve the problem of known technology, reach the effect of accelerating PLL device locking frequency speed speed.
Description of drawings
Figure 1A shows the schematic diagram of the PLL device of known technology.
Figure 1B shows a running oscillogram of the PLL device of known technology.
Fig. 2 A shows the schematic diagram of the PLL device of one embodiment of the invention.
One running oscillogram of Fig. 2 B displayed map 2A PLL device.
Fig. 2 C shows the schematic diagram of the PLL device of one embodiment of the invention.
Fig. 3 shows the schematic diagram of the PLL device of one embodiment of the invention.
Fig. 4 shows the schematic diagram of the PLL device of one embodiment of the invention.
Fig. 5 shows the flow chart of control method of the PLL device of one embodiment of the invention.
Fig. 6 A shows the schematic diagram of the PLL device of one embodiment of the invention.
One running oscillogram of Fig. 6 B displayed map 6A PLL device.
Fig. 7 A shows the memory cell of one embodiment of the invention and the schematic diagram of loop filter configuration.
Fig. 7 B shows the memory cell of one embodiment of the invention and the schematic diagram of loop filter configuration.
Fig. 8 shows the flow chart of control method of the PLL device of one embodiment of the invention.
[main element label declaration]
10,20,30,40,60 PLL devices
11,31 phase detectors
12,32 charge pumps
13,33,42,44 loop filters
14,34 voltage controlled oscillators
15,35 frequency eliminators
The P1 phase-locked loop circuit
Mu, 36,37,38 memory cell
371 memories
381 analog/digital converters
372,382 digital/analog converters
Embodiment
Fig. 2 A is the schematic diagram according to PLL device one embodiment of the present invention.PLL device 20 can be a frequency generating device or is a kind of storage control signal (voltage or electric current ... Deng) and lock the circuit of clock signal frequency.PLL device 20 includes a phase-locked loop circuit P1 and a memory cell Mu, phase-locked loop circuit P1 produces phase-locked clock signal Fvco according to control voltage Vc, when phase-locked loop circuit P1 starts, memory cell Mu provides an initialize signal to this phase-locked loop circuit according to a digital value, make control voltage Vc rise to a preset value rapidly, the detailed operation mode of present embodiment is described as follows:
Phase-locked loop circuit P1 comprises a voltage controlled oscillator 24, according to the control voltage Vc output one phase-locked clock signal Fvco with stabilized frequency.Must notice that the phase-locked loop circuit P1 of present embodiment can be the circuit that close function is provided in existing known phase-locked loop at present or future development, those skilled in the art should be able to understand the framework and the function mode of those devices.Therefore do not given unnecessary details.Memory cell Mu couples node N1, in phase-locked loop circuit P1 normal operation and close during (Turn off), control voltage Vc is stored with the form of a digital value, and when after phase-locked loop circuit P1 closes, restarting (Turn on) again, provide an initialize signal (for example initial voltage) to node N1 according to this digital value, because this initial voltage is to produce according to this digital value, its level will be close with control voltage Vc, therefore memory cell Mu provides this initial voltage to node N1 when starting, can make the voltage on the node N1 return to speeding up of original level, in other words, shortened required locking time of phase-locked loop circuit P1.Must note, memory cell Mu also can and/or close in startup, running and store control voltage Vc is a digital value and the action of changing this digital value generation initial voltage, this initial voltage promptly just was prepared in advance before not restarting, in other words, memory cell Mu can provide this initial voltage before phase-locked loop circuit P1 restarts or when starting.
In the present embodiment, the initialize signal that memory cell Mu provides according to this digital value is a voltage signal, and in other embodiments, memory cell Mu can also provide an initial current according to this digital value, reaches the effect that shortens locking time equally.
This digital value can be after starting for the first time, determine by the voltage on the detection node N1, can also be after each phase-locked loop circuit P1 locking, voltage on the detection node N1 and upgrading again, perhaps detection node N1 not, in default mode the preset number value is stored among the memory cell Mu, when each the startup, memory cell Mu provides initialize signal according to this preset number value.Must note, adopt the mode of detection node N1 or preset number value, also can be combined and be applied in the embodiment of the invention.For example, can detection node N1 or the preset number value one of them be the major control mode, another way then is to adopt under the default situation of foundation designer design, for example environment changes or controls voltage Vc when unstable.Perhaps when starting for the first time, move, upgrade this preset number value according to the control voltage level after the locking more thereafter according to the preset number value.
The PLL device that the present invention proposes effectively shortens the locking time of required cost when starting, and solves the problem of known technology, reaches and accelerates the effect that PLL device is replied speed.
In one embodiment, shown in Fig. 2 C, memory cell Mu is made up of analog/digital converter Mu1 and digital/analog converter Mu2, analog/digital converter Mu1 will control voltage Vc conversion at phase-locked loop circuit P1 duration of work and produce corresponding digital value, and be stored in the memory, and when phase-locked loop circuit P1 started, digital/analog converter Mu2 produced the initialize signal of voltage or current forms again according to this digital value conversion.Do not disappear owing to not closing because of circuit with the digital value of digital form storage, during therefore each the startup, digital/analog converter Mu2 can promptly provide initial voltage or electric current to phase-locked loop circuit P1 according to this digital value.
Fig. 3 is the schematic diagram according to another embodiment of phase-locked loop of the present invention.PLL device 30 includes phase detectors 31, charge pump 32, loop filter 33, voltage controlled oscillator 34, frequency eliminator 35 and memory cell 36.Phase detectors 31 compare feedback signal Fdiv and the reference signal Fref that frequency eliminator provides, produce control signal C according to this and make charge pump 32 output Control current Icp, Control current Icp is to the capacitor C in the loop filter 33 1 and C2 discharges and recharges and provide control voltage Vc1 to voltage controlled oscillator 34 at node N1, in the present embodiment, phase detectors 31, charge pump 32 and the loop filter 33 common control circuits of forming PLL device 30 are used to provide control voltage and give voltage controlled oscillator 34 with output phase-locked clock signal Fvco.When the phase place of leading (leading) the reference signal Fref of the phase place of feedback signal Fdiv, control signal C makes charge pump 22 produce the Control current Icp of negative (negative), therefore controls voltage Vc1 and descends; Otherwise, when the phase place of phase lag (lagging) the reference signal Fref of feedback signal Fdiv, control signal C control charge pump 22 produces the just Control current Icp of (positive), control voltage Vc is risen, so that the phase-locked clock Fvco semaphore lock of output is at certain value.
In the present embodiment, phase detectors 31, charge pump 32, loop filter 33, voltage controlled oscillator 34 and frequency eliminator 35 can be the technology of the close function that present existing known technology or future development goes out, those skilled in the art will be understood that the framework and the function mode of those devices, for avoiding fuzzy focus, the details of those elements is not described in detail in detail at this.Wherein, frequency eliminator 35 is done FEEDBACK CONTROL in order to phase-locked clock signal Fvco is carried out down conversion process so that feedback signal Fdiv to be provided, and can omit according to the side circuit demand.
In one embodiment; the capacitance of capacitor C 2 can be made as greater than capacitor C 1; therefore at PLL device 30 duration of works; the level of voltage Vc2 on the node N2 and the voltage Vc1 on the node N1 ten minutes are approaching; but voltage Vc2 can be more more stable than voltage Vc1; therefore, under the consideration based on protection memory cell 36 and raising stability, the memory cell 36 of present embodiment is coupled to node N2.Certainly, in other embodiment, memory cell 36 also can couple node N1.In addition, because node N2 coupling capacitance C2, the memory cell 36 of present embodiment is according to a digital value, and the initialize signal that provides current forms when starting PLL device 30 shortens locking time to node N2 to capacitor C 2 chargings.As previously mentioned, digital value in the memory cell 36 of present embodiment can be preset number value, the decision of the voltage Vc2 when starting for the first time on the detection node N2 that is preset in the memory cell 36, or behind PLL device 30 each steady operations, the voltage Vc2 on the detection node N2 and resetting.In one embodiment, also be provided with a look-up table (Look up table) in the memory cell 36, have a plurality of respective value in this look-up table, it can obtain corresponding digital value by look-up table according to the voltage of node N1 or N2, and is stored.
Fig. 4 is the schematic diagram according to another embodiment of phase-locked loop of the present invention.The framework of PLL device 40 and the PLL device of Fig. 3 30 are roughly the same, but the memory cell 37 of PLL device 40 is made up of a memory 371 and a digital/analog converter 372.Wherein memory 371 has the preset number value, and when starting in system, digital/analog converter 372 is according to this preset number value in the memory 371 at every turn, and conversion provides initialize signal to node N2, to allow PLL device 40 restart fast.In another embodiment, there is look-up table in the memory 371.
Fig. 5 shows the flow chart according to control method one embodiment of the present invention.This method includes the following step:
Step S502: beginning.
Step S504: produce an initialize signal according to a preset number value.
Step S506: make a control voltage return to a preset value and offer a phase-locked loop by this initialize signal.
Step S508: produce a phase-locked clock signal according to this control voltage.
Step S510: finish.
Fig. 6 A is the schematic diagram of another embodiment of PLL device of the present invention.The memory cell Mu of PLL device 60 include an analog/digital converter (Analog to digital convertor, ADC) 381 with digital/analog converter (Digital to analog convertor) 382.When the control voltage on the node N1 reached Vc 1, the voltage on the node N2 was Vc2.Then, analog/digital converter 381 receives this voltage Vc2, and this voltage Vc2 is simulated to digital translation, producing a digital value, and is stored.Wherein, analog/digital converter 381 can include a nonvolatile memory, and utilizes this memory storage digital value.And afterwards, PLL device 60 is through closing and when restarting, 382 pairs of digital values of digital/analog converter are carried out numeral to analog-converted, and the generation initialize signal provides to node N2 (for example voltage Vc2 or electric current are to node N2).At this moment, PLL device 60 just can quickly recover to Vc1 with the voltage on the node N1 by voltage Vc2, to reach the effect of locking frequency.Note that the time span that PLL device 60 starts for the first time is t1, the time span that restarts is t2.Shown in Fig. 6 B, t2 is much smaller than t1.This figure is the analogous diagram that PLL device produced that adopts 250MHZ.Drawing left icon display begins to charge to the waveform of locking frequency, spended time t1 by voltage 0V; And the right-hand icon display of drawing begins to charge to the waveform of locking frequency by voltage (initial voltage) Vc2, and spended time t2 can be known by Fig. 6 B and to find out that time t2 is less than time t1.
Moreover the analog/digital converter 381 of the embodiment of the invention is high more with the resolution of digital/analog converter 382, and then the voltage after the conversion of two transducers is more near voltage Vc1.Moreover when PLL device 60 was closed, analog/digital converter 381 only must use a spot of power supply with digital/analog converter 382 and carry out memory function.Therefore, can not influence the energy-saving effect of integrated circuit system.
Palpus attention person, the loop filter of Fig. 3 of the present invention, 4,6A embodiment can be in order to stablize this control voltage Vc1.And loop filter of the present invention is not limited to this type, and it also can adopt the present existing or future various loop filters that of developing, for example the loop filter that discloses of the loop filter shown in Fig. 7 A 42 and Fig. 7 B.In addition, memory cell of the present invention couples this loop filter.In Fig. 3 of the present invention, 4,6A, memory cell Mu couples the node N2 of 2 of the filter element-resistance R of loop filter and capacitor C; Relatively, among another embodiment, memory cell also can directly couple node N1, and complexity does not illustrate among Fig. 3,4, the 6A in order to avoid illustrating too, and those skilled in the art should be understood the mode of connection of Fig. 3,4,6A by Fig. 7 B.
Fig. 8 shows the flow chart of control method one embodiment of the present invention.This method includes the following step:
Step S802: beginning.
Step S804: provide a control voltage to a PLL device.
Step S806: produce a phase-locked clock signal according to this control voltage, and produce a digital value according to this control voltage.
Step S808:, store this digital value in PLL device running and/or down periods.
Step S810: when PLL device starts, produce initialize signal according to this digital value, for producing this phase-locked clock signal apace once more.
Step S912: finish.
Though more than with embodiment the present invention is described, therefore do not limit scope of the present invention, only otherwise break away from main idea of the present invention, those skilled in the art can carry out various distortion or change.
Claims (34)
1. PLL device includes:
One phase-locked loop circuit produces a phase-locked clock signal according to a control voltage; And
One memory cell couples this phase-locked loop circuit, when this phase-locked loop circuit starts, provides an initialize signal to this phase-locked loop circuit according to a digital value, makes this control voltage return to a preset value.
2. PLL device according to claim 1, wherein this phase-locked loop circuit includes a voltage controlled oscillator, and this voltage controlled oscillator couples this control voltage, produces this phase-locked clock signal according to this control voltage.
3. PLL device according to claim 1, wherein this memory cell includes:
One analog/digital converter is simulated to digital translation this control voltage, to produce this digital value; And
One digital/analog converter carries out numeral to analog-converted to this digital value, to produce this initialize signal.
4. PLL device according to claim 1, wherein this memory cell includes:
One memory has at least one preset number value; And
One digital/analog converter carries out numeral to analog-converted according to this preset number value, to produce this initialize signal.
5. PLL device according to claim 1, wherein this memory cell includes:
One memory is provided with a look-up table, and this look-up table has a plurality of respective value, for choosing a respective value as this digital value according to this control voltage; And
One digital/analog converter carries out numeral to analog-converted to this digital value, to produce this initialize signal.
6. PLL device according to claim 3, wherein this analog/digital converter comprises a nonvolatile memory, in order to store this digital value.
7. PLL device according to claim 1, wherein this initialize signal is voltage or electric current.
8. PLL device according to claim 1, wherein this phase-locked loop circuit comprises a loop filter, in order to filtering and stablize this first control voltage.
9. PLL device according to claim 8, wherein this memory cell couples this loop filter.
10. store the circuit of controlling voltage and locking frequency signal for one kind, include:
One voltage controlled oscillator produces a frequency signal according to a control voltage;
One control circuit produces this control voltage according to an initialize signal, and when the frequency of this frequency signal changes, adjusts this control voltage accordingly, so that this frequency signal is locked to a preset value; And
One memory cell in order to storing the digital value of this control voltage after conversion, and provides one in fact to equal this initialize signal of this control voltage to this control circuit according to this digital value in one during default.
11. circuit according to claim 10, wherein this memory cell includes:
One analog/digital converter is simulated to digital translation this control voltage, to produce this digital value; And
One digital/analog converter carries out numeral to analog-converted to this digital value, to produce this reference voltage during this is default.
12. circuit according to claim 11 was that this circuit is by during restarting after closing during wherein should presetting.
13. circuit according to claim 11, wherein this analog/digital converter comprises a nonvolatile memory, in order to store this digital value.
14. circuit according to claim 10, wherein this control circuit comprises a loop filter, in order to filtering and stablize this control voltage.
15. circuit according to claim 14, wherein this memory cell couples this loop filter.
16. PLL device according to claim 10, wherein this initialize signal is voltage or electric current.
17. a PLL device includes:
One phase detectors detect the phase difference value of a reference signal and a phase-locked clock signal, produce a control signal according to this phase difference value;
One charge pump produces a Control current according to this control signal;
One loop filter produces one first control voltage according to this Control current;
One memory cell couples a node, this first control voltage is saved as a digital value during default in one first, and produces an initialize signal according to this digital value in one second during default; And
One voltage controlled oscillator couples this node, first produces this phase-locked clock signal according to this first control voltage during default in this, and second produces this phase-locked clock signal according to this initialize signal during default in this.
18. PLL device according to claim 17, wherein this first default during for this PLL device operate during.
19. PLL device according to claim 17 is wherein between this second starting period of restarting after closing for this PLL device during default.
20. PLL device according to claim 17, wherein this memory cell includes:
One analog/digital converter is simulated to digital translation this first control voltage, to produce this digital value; And
One digital/analog converter carries out numeral to analog-converted to this digital value, to produce this initialize signal.
21. PLL device according to claim 17 also comprises a frequency eliminator, this frequency eliminator is in order to carry out down conversion process with the phase-locked clock signal.
22. PLL device according to claim 20, wherein this analog/digital converter comprises a nonvolatile memory, in order to store this digital value.
23. PLL device according to claim 17, wherein this initialize signal is voltage or electric current.
24. the control method of a PLL device includes:
Provide a control voltage to a phase-locked loop;
Produce a phase-locked clock signal according to this control voltage, and produce a digital value according to this control voltage;
Store this digital value; And
When this phase-locked loop starts, this digital value is converted to an initialize signal gives this PLL device, use making this control voltage return to a preset value.
25. method according to claim 24, wherein this control voltage equates with this initialize signal or is equal in fact.
26. method according to claim 24, wherein this control voltage and this initialize signal have a difference.
27. method according to claim 24 wherein should produce a phase-locked clock signal according to this control voltage, and comprise according to this control voltage according to the step that this control voltage produces a digital value and to select a respective value as this digital value in a look-up table.
28. method according to claim 24 wherein should produce a phase-locked clock signal according to this control voltage, and according to the step that this control voltage produces a digital value comprise to this control voltage do simulate to digital translation to produce this digital value.
29. the control method of a PLL device includes:
Produce an initialize signal according to a preset number value;
Make a control voltage return to a preset value by this initialize signal, and should control voltage and offer a phase-locked loop; And
Produce a phase-locked clock signal according to this control voltage.
30. method according to claim 29, wherein this control voltage equates with this initialize signal or is equal in fact.
31. method according to claim 29, wherein this control voltage and this initialize signal have a difference.
32. method according to claim 29 also comprises according to this control voltage and upgrades this preset number value.
33. method according to claim 32 wherein should comprise according to the step that this control voltage upgrades this digital value according to this control voltage by selecting a respective value in the look-up table to upgrade this preset number value.
34. method according to claim 32, wherein the step that should upgrade this digital value according to this control voltage comprise this control voltage done and simulated to digital translation, produced this preset number value of digital value confession renewal.
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| CN2010101342718A CN102195640A (en) | 2010-03-11 | 2010-03-11 | Phase lock loop (PLL) device and control method thereof |
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| CN2010101342718A CN102195640A (en) | 2010-03-11 | 2010-03-11 | Phase lock loop (PLL) device and control method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106788406A (en) * | 2016-12-14 | 2017-05-31 | 深圳市海能达通信有限公司 | Frequency generating units and the method for reducing frequency locking time |
| CN106972855A (en) * | 2015-12-09 | 2017-07-21 | 格罗方德半导体公司 | Via the system and method for having stored band value and accelerating in subsequent calibrations PLL locking times |
| CN110299914A (en) * | 2018-03-21 | 2019-10-01 | 群联电子股份有限公司 | Phase-locked loop circuit bearing calibration, memorizer memory devices and connecting interface circuit |
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| US20070153953A1 (en) * | 2006-01-04 | 2007-07-05 | Matthias Garzarolli | Phase-Locked Loop |
| CN101471658A (en) * | 2007-12-26 | 2009-07-01 | 扬智科技股份有限公司 | Phase locked loop device and control method thereof |
| CN101622814A (en) * | 2007-03-02 | 2010-01-06 | Nxp股份有限公司 | Fast powering-up of data communication system |
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| US20050095992A1 (en) * | 2002-02-07 | 2005-05-05 | Thompson Ian V. | Synthesiser |
| US20070153953A1 (en) * | 2006-01-04 | 2007-07-05 | Matthias Garzarolli | Phase-Locked Loop |
| CN101622814A (en) * | 2007-03-02 | 2010-01-06 | Nxp股份有限公司 | Fast powering-up of data communication system |
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| CN106972855A (en) * | 2015-12-09 | 2017-07-21 | 格罗方德半导体公司 | Via the system and method for having stored band value and accelerating in subsequent calibrations PLL locking times |
| CN106972855B (en) * | 2015-12-09 | 2020-10-23 | 格罗方德半导体公司 | System and method for accelerating PLL lock time in subsequent calibration via stored band values |
| CN106788406A (en) * | 2016-12-14 | 2017-05-31 | 深圳市海能达通信有限公司 | Frequency generating units and the method for reducing frequency locking time |
| CN110299914A (en) * | 2018-03-21 | 2019-10-01 | 群联电子股份有限公司 | Phase-locked loop circuit bearing calibration, memorizer memory devices and connecting interface circuit |
| CN110299914B (en) * | 2018-03-21 | 2022-11-22 | 群联电子股份有限公司 | Phase-locked loop circuit correction method, memory storage device and connection interface circuit |
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Application publication date: 20110921 |