CN109698003B - Equalizer adjusting method, signal receiving circuit and memory storage device - Google Patents

Equalizer adjusting method, signal receiving circuit and memory storage device Download PDF

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CN109698003B
CN109698003B CN201710990270.5A CN201710990270A CN109698003B CN 109698003 B CN109698003 B CN 109698003B CN 201710990270 A CN201710990270 A CN 201710990270A CN 109698003 B CN109698003 B CN 109698003B
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signal
modulation
modulation circuit
parameter
eye
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CN109698003A (en
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陈圣文
孙世洋
陈维咏
吴仁钜
陈志铭
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Phison Electronics Corp
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Phison Electronics Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/011—Arrangements for interaction with the human body, e.g. for user immersion in virtual reality
    • G06F3/013—Eye tracking input arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Dc Digital Transmission (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

An exemplary embodiment of the present invention provides an equalizer adjusting method, a signal receiving circuit and a memory storage device, wherein the method includes: receiving a first signal; modulating the first signal by the first modulation circuit according to the first type of parameter and modulating the first signal by the second modulation circuit according to the second type of parameter; detecting a signal eye width value and a signal eye height value of the modulated first signal; and adjusting the first type of parameter according to the detected signal eye width value and adjusting the second type of parameter according to the detected signal eye height value.

Description

Equalizer adjusting method, signal receiving circuit and memory storage device
Technical Field
The invention relates to an equalizer adjusting method, a signal receiving circuit and a memory storage device.
Background
Digital cameras, mobile phones and MP3 players have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since a rewritable non-volatile memory module (e.g., a flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices.
As the signal transmission speed increases, the performance requirement of the receiver, which can be used to improve the data receiving capability of the receiving end, is also stronger. For example, an adaptive equalizer (adaptive equalizer) may be applied to a receiver of a wired transmission. Although some types of adaptive equalizers may achieve dynamic parameter adjustment, most adaptive equalizers are limited by the drawbacks of the adjustment algorithm, resulting in poor adjustment capability of the equalizer.
Disclosure of Invention
An exemplary embodiment of the present invention provides an equalizer adjusting method, a signal receiving circuit and a memory storage device, which can improve the adjusting accuracy of an equalizer.
An exemplary embodiment of the present invention provides an equalizer adjusting method for a signal receiving circuit of a memory storage device, the equalizer adjusting method including: receiving a first signal; modulating the first signal by a first modulation circuit according to a first type of parameter and modulating the first signal by a second modulation circuit according to a second type of parameter; detecting a signal eye width value of the modulated first signal and a signal eye height value of the modulated first signal; and adjusting the first type of parameter according to the detected signal eye width value and adjusting the second type of parameter according to the detected signal eye height value.
In an exemplary embodiment of the present invention, the step of modulating the first signal by the first modulation circuit according to the first type of parameter and modulating the first signal by the second modulation circuit according to the second type of parameter comprises: while one of the first modulation circuit and the second modulation circuit modulates the first signal by using a first modulation parameter, the other of the first modulation circuit and the second modulation circuit sequentially modulates the first signal by using a plurality of second modulation parameters.
In an exemplary embodiment of the present invention, the step of modulating the first signal by the first modulation circuit according to the first type of parameter and modulating the first signal by the second modulation circuit according to the second type of parameter further comprises: modulating the first signal by the other of the first modulation circuit and the second modulation circuit sequentially using a plurality of fourth modulation parameters during the one of the first modulation circuit and the second modulation circuit modulates the first signal using a third modulation parameter, wherein the first modulation parameter is different from the third modulation parameter.
In an exemplary embodiment of the present invention, the step of detecting the eye width value of the modulated first signal and the eye height value of the modulated first signal comprises: detecting a first signal eye width value of the first signal having a first signal eye height value during the period when the first signal is modulated by the one of the first modulation circuit and the second modulation circuit by using the first modulation parameter; and detecting a second signal eye width value of the first signal having a second signal eye height value during the period when the one of the first modulation circuit and the second modulation circuit modulates the first signal using the third modulation parameter, wherein the steps of adjusting the first type of parameter according to the detected signal eye width value and adjusting the second type of parameter according to the detected signal eye height value comprise: and adjusting the first type of parameters according to the first signal eye width value and the second signal eye width value.
In an exemplary embodiment of the present invention, the first eye height value is an optimum eye height value of the first signal detected during a period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the first modulation parameter, and the second eye height value is an optimum eye height value of the first signal detected during a period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the third modulation parameter.
In an exemplary embodiment of the present invention, the step of detecting the eye width value of the modulated first signal and the eye height value of the modulated first signal comprises: detecting a first signal eye height value of the first signal having a first signal eye width value during the period when the first signal is modulated by the one of the first modulation circuit and the second modulation circuit using the first modulation parameter; and detecting a second eye height value of the first signal having a second eye width value during the modulation of the first signal by the one of the first modulation circuit and the second modulation circuit using the third modulation parameter, wherein the adjusting the first type of parameter according to the detected eye width value and the adjusting the second type of parameter according to the detected eye height value comprises: and adjusting the second type of parameter according to the first signal eye height value and the second signal eye height value.
In an exemplary embodiment of the present invention, the first signal eye width value is an optimal signal eye width value of the first signal detected during a period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the first modulation parameter, and the second signal eye width value is an optimal signal eye width value of the first signal detected during a period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the third modulation parameter.
In an exemplary embodiment of the present invention, the equalizer adjusting method further includes: performing a phase-locking operation on the modulated first signal by a clock and data recovery circuit.
Another exemplary embodiment of the present invention provides a signal receiving circuit for a memory storage device, the signal receiving circuit including an equalizer circuit and a control circuit. The control circuit is connected to the equalizer circuit, wherein the equalizer circuit includes a first modulation circuit and a second modulation circuit, wherein the equalizer circuit is configured to receive a first signal, wherein the first modulation circuit is configured to modulate the first signal according to a first type of parameter and the second modulation circuit is configured to modulate the first signal according to a second type of parameter, wherein the control circuit is configured to detect a signal eye width value of the modulated first signal and a signal eye height value of the modulated first signal, wherein the control circuit is further configured to adjust the first type of parameter according to the detected signal eye width value and adjust the second type of parameter according to the detected signal eye height value.
In an exemplary embodiment of the present invention, the operation of the first modulation circuit modulating the first signal according to the first type of parameter and the operation of the second modulation circuit modulating the first signal according to the second type of parameter include: while one of the first modulation circuit and the second modulation circuit modulates the first signal by using a first modulation parameter, the other of the first modulation circuit and the second modulation circuit sequentially modulates the first signal by using a plurality of second modulation parameters.
In an exemplary embodiment of the present invention, the operations of the first modulation circuit modulating the first signal according to the first type of parameter and the second modulation circuit modulating the first signal according to the second type of parameter further include: modulating the first signal by the other of the first modulation circuit and the second modulation circuit sequentially using a plurality of fourth modulation parameters during the one of the first modulation circuit and the second modulation circuit modulates the first signal using a third modulation parameter, wherein the first modulation parameter is different from the third modulation parameter.
In an exemplary embodiment of the present invention, the control circuit includes an eye width detector, and the eye width detector is connected to the first modulation circuit and the second modulation circuit, the eye width detector is configured to detect a first signal eye width value of the first signal having a first signal eye height value during a period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the first modulation parameter, the eye width detector is further configured to detect a second signal eye width value of the first signal having a second signal eye height value during the period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the third modulation parameter, wherein the eye width detector is further configured to adjust the first type of parameter according to the first signal eye width value and the second signal eye width value.
In an exemplary embodiment of the present invention, the control circuit further includes an eye-height detector connected to the first modulation circuit and the second modulation circuit, the first signal eye-height value is an optimal signal eye-height value of the first signal detected by the eye-height detector during a period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the first modulation parameter, and the second signal eye-height value is an optimal signal eye-height value of the first signal detected by the eye-height detector during a period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the third modulation parameter.
In an exemplary embodiment of the present invention, the control circuit includes an eye-height detector, and the eye-height detector is connected to the first modulation circuit and the second modulation circuit, the eye-height detector is configured to detect a first signal eye-height value of the first signal having a first signal eye-width value during a period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the first modulation parameter, the eye-height detector is further configured to detect a second signal eye-height value of the first signal having a second signal eye-width value during the period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the third modulation parameter, wherein the eye-height detector is further configured to adjust the second type of parameter according to the first eye-height value and the second eye-height value.
In an exemplary embodiment of the present invention, the control circuit further includes an eye width detector connected to the first modulation circuit and the second modulation circuit, the first signal eye width value is an optimal signal eye width value of the first signal detected by the eye width detector during a period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the first modulation parameter, and the second signal eye width value is an optimal signal eye width value of the first signal detected by the eye width detector during a period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the third modulation parameter.
In an exemplary embodiment of the invention, the signal receiving circuit further includes a clock and data recovery circuit connected to the equalizer circuit and the control circuit, the clock and data recovery circuit performing a phase-locked operation on the modulated first signal.
Another exemplary embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module, the connection interface unit includes a signal receiving circuit, the signal receiving circuit includes a first modulation circuit and a second modulation circuit, the signal receiving circuit is used for receiving a first signal, the first modulation circuit is used for modulating the first signal according to a first type of parameter and the second modulation circuit is used for modulating the first signal according to a second type of parameter, the signal receiving circuit is used for detecting a signal eye width value of the modulated first signal and a signal eye height value of the modulated first signal, and the signal receiving circuit is further used for adjusting the first type of parameter according to the detected signal eye width value and adjusting the second type of parameter according to the detected signal eye height value.
In an exemplary embodiment of the present invention, the operation of the first modulation circuit modulating the first signal according to the first type of parameter and the operation of the second modulation circuit modulating the first signal according to the second type of parameter include: while one of the first modulation circuit and the second modulation circuit modulates the first signal by using a first modulation parameter, the other of the first modulation circuit and the second modulation circuit sequentially modulates the first signal by using a plurality of second modulation parameters.
In an exemplary embodiment of the present invention, the operations of the first modulation circuit modulating the first signal according to the first type of parameter and the second modulation circuit modulating the first signal according to the second type of parameter further include: modulating the first signal by the other of the first modulation circuit and the second modulation circuit sequentially using a plurality of fourth modulation parameters during the one of the first modulation circuit and the second modulation circuit modulates the first signal using a third modulation parameter, wherein the first modulation parameter is different from the third modulation parameter.
In an exemplary embodiment of the invention, the signal receiving circuit further includes a control circuit, and the control circuit is connected to the first modulation circuit and the second modulation circuit, the control circuit is configured to detect a first signal eye width value of the first signal having a first signal eye height value during a period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the first modulation parameter, the control circuit is further configured to detect a second eye width value of the first signal having a second eye height value during a period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the third modulation parameter, the control circuit is further configured to adjust the first type of parameter according to the first signal eye width value and the second signal eye width value.
In an exemplary embodiment of the present invention, the first eye height value is an optimum eye height value of the first signal detected by the control circuit during a period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the first modulation parameter, and the second eye height value is an optimum eye height value of the first signal detected by the control circuit during a period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the third modulation parameter.
In an exemplary embodiment of the invention, the signal receiving circuit further includes a control circuit, and the control circuit is connected to the first modulation circuit and the second modulation circuit, the control circuit is configured to detect a first eye height of the first signal having a first eye width during a period in which the first modulation parameter is used by the one of the first modulation circuit and the second modulation circuit to modulate the first signal, the control circuit is further configured to detect a second eye height value of the first signal having a second eye width value during a period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the third modulation parameter, the control circuit is further configured to adjust the second type of parameter according to the first eye height value and the second eye height value.
In an exemplary embodiment of the present invention, the first signal eye width value is an optimal signal eye width value of the first signal detected by the control circuit during a period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the first modulation parameter, and the second signal eye width value is an optimal signal eye width value of the first signal detected by the control circuit during a period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the third modulation parameter.
In an exemplary embodiment of the invention, the signal receiving circuit is further configured to perform a phase-locking operation on the modulated first signal.
Based on the above, the first modulation circuit and the second modulation circuit in the equalizer circuit can modulate the first signal according to the first type of parameter and the second type of parameter, respectively. Then, according to the signal eye width value and the signal eye height value of the modulated first signal, the first type of parameter used by the first modulation circuit and the second type of parameter used by the second modulation circuit can be adjusted, thereby improving the adjustment accuracy of the equalizer.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1A is a schematic diagram of a signal receiving circuit according to a first exemplary embodiment of the invention.
Fig. 1B is a diagram illustrating a first signal according to a first exemplary embodiment of the invention.
Fig. 2 is a flowchart illustrating an equalizer adjustment method according to a first exemplary embodiment of the invention.
Fig. 3A is a schematic diagram of a signal receiving circuit according to a second exemplary embodiment of the invention.
Fig. 3B is a diagram illustrating a table recorded with a first type parameter, a second type parameter, a signal eye height value and a signal eye width value according to a second exemplary embodiment of the invention.
Fig. 3C is a flowchart illustrating an equalizer adjustment method according to a second exemplary embodiment of the invention.
Fig. 4A is a schematic diagram of a signal receiving circuit according to a third exemplary embodiment of the invention.
Fig. 4B is a diagram illustrating a table recorded with a first type parameter, a second type parameter, a signal eye height value and a signal eye width value according to a third exemplary embodiment of the invention.
Fig. 4C is a flowchart illustrating an equalizer adjustment method according to a third exemplary embodiment of the invention.
FIG. 5 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention.
FIG. 6 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.
FIG. 7 is a diagram illustrating a host system and a memory storage device according to another exemplary embodiment of the invention.
FIG. 8 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.
Description of the reference numerals
10. 30, 40: signal receiving circuit
11. 31, 41: equalizer circuit
111. 112, 311, 312, 411, 412: modulation circuit
12. 32, 42: control circuit
13. 33, 43: clock and data recovery circuit
S201: step (receiving first signal)
S202: step (the first signal is modulated by the first modulation circuit according to the first kind of parameter and the first signal is modulated by the second modulation circuit according to the second kind of parameter)
S203: step (detecting the eye width value of the modulated first signal and the eye height value of the modulated first signal)
S204: step (adjusting the first type of parameter according to the detected eye width value of the signal and adjusting the second type of parameter according to the detected eye height value of the signal)
321. 422: eye height detector
322. 421: eye width detector
34. 44: table form
S301: step (receiving first signal)
S302: step (modulating the first signal by the first modulation circuit using a first type of parameter)
S303: step (modulating the first signal by the second modulation circuit using a second type of parameter)
S304: step (detecting the eye height of the modulated first signal and the eye width of the modulated first signal)
S305: step (whether the second preset modulation frequency is reached)
S306: step (adjusting second type parameters)
S307: step (recording the signal eye width value of the first signal with the best signal eye height value)
S308: step (whether the first preset modulation frequency is reached)
S309: step (adjusting first type parameters)
S310: step (determining the best signal eye width value according to the recorded signal eye width value)
S311: determining the first type of parameter to be used and the second type of parameter to be used according to the optimal signal eye width value
S401: step (receiving first signal)
S402: step (modulating the first signal by the second modulation circuit using a second type of parameter)
S403: step (modulating the first signal by the first modulation circuit using a first type of parameter)
S404: step (detecting the eye height of the modulated first signal and the eye width of the modulated first signal)
S405: step (whether the first preset modulation frequency is reached)
S406: step (adjusting first type parameters)
S407: step (recording the signal eye height value of the first signal with the best signal eye width value)
S408: step (whether the second preset modulation frequency is reached)
S409: step (adjusting second type parameters)
S410: step (determining the best eye height value of the signal according to the recorded eye height value of the signal)
S411: determining the first type of parameter to be used and the second type of parameter to be used according to the optimum eye height value of the signal
70. 90: memory storage device
71. 91: host system
710: system bus
711: processor with a memory having a plurality of memory cells
712: random access memory
713: read-only memory
714: data transmission interface
72: input/output (I/O) device
80: main machine board
801: u disk
802: memory card
803: solid state disk
804: wireless memory storage device
805: global positioning system module
806: network interface card
807: wireless transmission device
808: keyboard with a keyboard body
809: screen
810: horn type loudspeaker
92: SD card
93: CF card
94: embedded memory device
941: embedded multimedia card
942: embedded multi-chip packaging storage device
1002: connection interface unit
1004: memory control circuit unit
1006: rewritable nonvolatile memory module
Detailed Description
In the following, a number of embodiments are presented to illustrate the invention, however, the invention is not limited to the illustrated embodiments. Suitable combinations between the embodiments are also allowed. The term "coupled" as used throughout this specification, including the claims, may refer to any direct or indirect connection means. For example, if a first device couples to a second device, that connection should be interpreted as either being a direct connection, or a indirect connection via other devices and some means of connection. Furthermore, the term "signal" may refer to at least one current, voltage, charge, temperature, data, or any other signal or signals.
First exemplary embodiment
Fig. 1A is a schematic diagram of a signal receiving circuit according to a first exemplary embodiment of the invention. Fig. 1B is a diagram illustrating a first signal according to a first exemplary embodiment of the invention. Referring to fig. 1A and 1B, the signal receiving Circuit 10 includes an equalizer (equalizer) Circuit 11, a control Circuit 12, and a Clock and Data Recovery Circuit (CDR) 13.
The equalizer circuit 11 is used for receiving a signal S1 (also referred to as a first signal). In the present exemplary embodiment, the signal S1 is a data signal. For example, the signal S1 may have multiple pulses to convey a series of bits of data. For example, each bit data refers to one bit "0" or "1". Signal S1 is the signal attenuated by the channel. For example, more or less channel attenuation may be related to factors such as the length of the channel (e.g., wired/wireless channel) and the strength of the noise. The equalizer circuit 11 may compensate for the high frequency and/or low frequency portions of the signal S1. In the present exemplary embodiment, the equalizer circuit 11 modulates the signal S1 and outputs a signal S3. For example, the equalizer circuit 11 may perform modulation on the signal S1 using different parameters to attempt to output the signal S3 with better signal quality or better pulse waveform for analysis.
In the present exemplary embodiment, the pulse waveforms of the signals S1, S2, and S3 can be considered to include multiple eyes. For example, the signal eye width EW of the signal S3 can be used to represent the width of one eye in the pulse waveform of the signal S3. The eye height EH of the signal S3 is indicative of the height of one eye in the pulse waveform of the signal S3. Generally, the larger the signal eye width value EW and/or the larger the signal eye height value EH of the signal S3, the better the signal quality of the signal S3 (e.g., the easier and more accurate the sampling of the signal S3); conversely, a smaller signal eye width value EW and/or a smaller signal eye height value EH of the signal S3 indicates a poorer signal quality of the signal S3 (e.g., the signal S3 is harder and more prone to error).
The equalizer circuit 11 includes a modulation circuit 111 and a modulation circuit 112. The modulation circuit 112 is connected to the modulation circuit 111. In the present exemplary embodiment, the input terminal of the modulation circuit 112 is connected to the output terminal of the modulation circuit 111. However, in another exemplary embodiment, the input terminal of the modulation circuit 111 may be connected to the output terminal of the modulation circuit 112 or other connection methods may be adopted, and the invention is not limited thereto.
The modulation circuit 111 modulates the signal S1 and generates a signal S2. In other words, the signal S2 is the signal S1 modulated by the modulation circuit 111. The modulation circuit 112 modulates the signal S2 and generates a signal S3. In other words, the signal S3 is the signal S2 modulated by the modulation circuit 112 or the signal S1 modulated by the modulation circuits 111 and 112.
In the present exemplary embodiment, one of the modulation circuit 111 and the modulation circuit 112 includes at least one Continuous-Time Linear Equalizer (CTLE), and the other of the modulation circuit 111 and the modulation circuit 112 includes at least one Decision Feedback Equalizer (DFE). However, in another exemplary embodiment, at least one of the modulation circuits 111 and 112 may also include other types of equalizers or auxiliary circuits, such as an Infinite Impulse Response (IIR) circuit, and the like, which are not limited in the present invention.
In the present exemplary embodiment, one of the modulation circuits 111 and 112 is mainly used to improve the signal quality of the signal waveform of the signal S1 in one signal analysis direction (also referred to as a first signal analysis direction), and the other of the modulation circuits 111 and 112 is mainly used to improve the signal quality of the signal waveform of the signal S1 in the other signal analysis direction (also referred to as a second signal analysis direction). The first signal analysis direction is different from the second signal analysis direction. In an exemplary embodiment, the first signal analysis direction may be substantially perpendicular to the second signal analysis direction. Herein, substantially vertical means approximately vertical with a small tolerance.
In an exemplary embodiment, the modulation circuit 111 is configured to modulate the signal S1 to substantially change (e.g., increase) the eye width EW of the signal S3, and the modulation circuit 112 is configured to modulate the signal S2 to substantially change (e.g., increase) the eye height EH of the signal S3. In another exemplary embodiment, the modulation circuit 111 modulates the signal S1 to primarily change (e.g., increase) the eye height value EH of the signal S3, and the modulation circuit 112 modulates the signal S2 to primarily change (e.g., increase) the eye width value EW of the signal S3. In other words, in an exemplary embodiment, the first signal analysis direction is an adjustment direction and/or an analysis direction of one of the eye height and the eye width of the signal S1, and the second signal analysis direction is an adjustment direction and/or an analysis direction of the other of the eye height and the eye width of the signal S1. In addition, in practical applications, the modulation (e.g., eye width modulation or eye height modulation) performed by the modulation circuits 111 and 112 on the signal S1 may also affect each other, and is not limited to only modulating the signal eye width value EW or the signal eye height EH value individually.
The control circuit 12 is connected to the equalizer circuit 11. The control circuit 12 can analyze the signal S3 and detect the signal eye width value EW and the signal eye height value EH of the signal S3. The control circuit 12 can adjust the first type parameters (also referred to as first type modulation parameters) P1(1) -P1 (N) provided to the equalizer circuit 11 according to the detected signal eye width value EW. The control circuit 12 may adjust the second type of parameters (also referred to as second type of modulation parameters) P2(1) -P2 (M) provided to the equalizer circuit 11 according to the detected signal eye height value EH. N and M are positive integers, and N may be the same as or different from M.
In an exemplary embodiment, the first type of parameters P1(1) -P1 (N) are mainly related to the adjustment of the eye width value EW of the signal S3, and the second type of parameters P2(1) -P2 (M) are mainly related to the adjustment of the eye height value EH of the signal S3. However, in another exemplary embodiment, the first type of parameters P1(1) -P1 (N) may also affect the signal eye height value EH of the signal S3, and/or the second type of parameters P2(1) -P2 (M) may also affect the signal eye width value EW of the signal S3. One of the modulation circuits 111 and 112 receives the first type parameters P1(1) -P1 (N) and modulates the signal S1 (or S2) according to the first type parameters P1(1) -P1 (N). The other of the modulation circuits 111 and 112 receives the second type parameters P2(1) -P2 (M) and modulates the signal S1 (or S2) according to the second type parameters P2(1) -P2 (M).
In an exemplary embodiment, the modulation circuit of the modulation circuits 111 and 112 modulating the signal S1 (or S2) according to the first type of parameters P1(1) -P1 (N) is also referred to as a first modulation circuit, and the modulation circuit of the modulation circuits 111 and 112 modulating the signal S1 (or S2) according to the second type of parameters P2(1) -P2 (M) is also referred to as a second modulation circuit. In an exemplary embodiment, assuming that the first type parameters P1(1) -P1 (N) are for use with a continuous timeline type equalizer, N is, for example, 343(7 × 7 × 7) or other values. In an exemplary embodiment, assuming that the second type parameters P2(1) -P2 (M) are used for the decision feedback equalizer, M is, for example, 11025(15 × 15 × 7 × 7) or other values.
In the present exemplary embodiment, the clock and data recovery circuit 13 is connected to the equalizer circuit 11 and receives the signal S3. The clock and data recovery circuit 13 performs a phase lock operation on the signal S3 and generates a clock signal CK. The clock and data recovery circuit 13 will not be described in detail herein. In the present exemplary embodiment, the control circuit 12 can also receive the clock signal CK output by the clock and data recovery circuit 13 and is driven by the clock signal CK and/or performs a predetermined operation according to the clock signal CK. In another exemplary embodiment, the clock and data recovery circuit 13 may be independent from the signal receiving circuit 10.
Fig. 2 is a flowchart illustrating an equalizer adjustment method according to a first exemplary embodiment of the invention. Referring to fig. 2, in step S201, a first signal is received. In step S202, the first modulation circuit modulates the first signal according to the first type of parameter, and the second modulation circuit modulates the first signal according to the second type of parameter. In step S203, a signal eye width value of the modulated first signal and a signal eye height value of the modulated first signal are detected. In step S204, the first type of parameter is adjusted according to the detected signal eye width value, and the second type of parameter is adjusted according to the detected signal eye height value.
Second exemplary embodiment
Fig. 3A is a schematic diagram of a signal receiving circuit according to a second exemplary embodiment of the invention. Fig. 3B is a diagram illustrating a table recorded with a first type parameter, a second type parameter, a signal eye height value and a signal eye width value according to a second exemplary embodiment of the invention. Referring to fig. 3A, the signal receiving circuit 30 includes an equalizer circuit 31, a control circuit 32, and a clock and data recovery circuit 33. The clock and data recovery circuit 33 is the same as or similar to the clock and data recovery circuit 13 in fig. 1A, and is not described herein again.
The equalizer circuit 31 includes modulation circuits 311 and 312. The modulation circuit 311 is configured to receive the first type parameters P1(1) -P1 (N) and modulate the signal S1 according to the first type parameters P1(1) -P1 (N) to output a signal S2. The modulation circuit 312 is configured to receive the second type parameters P2(1) -P2 (M) and modulate the signal S2 according to the second type parameters P2(1) -P2 (M) to output a signal S3. For example, the modulation circuit 311 may include at least one continuous time linear equalizer, and/or the modulation circuit 312 may include at least one decision feedback equalizer.
The control circuit 32 includes an eye height detector 321 and an eye width detector 322. Eye-height detector 321 is configured to analyze signal S3 and detect signal eye-height EH of signal S3. The eye width detector 322 is used for analyzing the signal S3 and detecting a signal eye width value EW of the signal S3. The eye-height detector 321 may adjust the output second-type parameters P2(1) -P2 (M) according to the detected signal eye-height value EH. The eye width detector 322 may adjust the output first type parameters P1(1) -P1 (N) according to the detected signal eye width value EW.
In an exemplary embodiment, the eye width detector 322 may output the parameter P1(i) for the modulation circuit 311, where i is between 1 and N. During the period when the modulation circuit 311 modulates the signal S1 with the parameter P1(i), the eye-height detector 321 may sequentially output parameters P2(j) to P2(k), where j and k are integers less than or equal to M, and j is less than k. In other words, while the modulation circuit 311 modulates the signal S1 by using the parameter P1(i), the modulation circuit 312 sequentially modulates the signal S2 by using the parameters P2(j) to P2 (k).
After the modulation circuit 312 modulates the signal S2 by using the parameters P2(j) -P2 (k) in sequence, the eye width detector 322 can output a parameter P1(P) for the modulation circuit 311, where P is between 1 and N, and P is not equal to i. During the period when the modulation circuit 311 modulates the signal S1 with the parameter P1(P), the eye-height detector 321 may sequentially output parameters P2(q) to P2(r), where q and r are integers less than or equal to M, and q is less than r. In other words, while the modulation circuit 311 modulates the signal S1 with the parameter P1(P), the modulation circuit 312 modulates the signal S2 with the parameters P2(q) to P2(r) in sequence. In an exemplary embodiment, the modulation circuit 311 modulates the signal S1 by using at least a portion of the first type of parameters P1(1) -P1 (N), and the modulation circuit 312 modulates the signal S2 by using at least a portion of the second type of parameters P2(1) -P2 (M) while the modulation circuit 311 modulates the signal S1 by using one of the first type of parameters P1(1) -P1 (N).
In an exemplary embodiment, the eye-height detector 321 may dynamically adjust the output second type parameter according to the detected eye-height value EH of the signal during the period when the modulation circuit 311 modulates the signal S1 by using one of the first type parameters P1(1) -P1 (N). For example, in an exemplary embodiment, the eye-height detector 321 may adjust the output second type parameter using a Least Mean Square (LMS) algorithm according to the detected signal eye-height EH to achieve an optimization of the detected signal eye-height EH. Alternatively, in an exemplary embodiment, the eye-height detector 321 may also use a blind measurement method or other algorithm to adjust the second type parameter of the output, which is not limited in the invention.
In an exemplary embodiment, during the modulation circuit 311 modulates the signal S1 by using one of the first type parameters P1(1) -P1 (N), the eye-height detector 321 may detect an optimal eye-height value of the signal S3 and the eye-width detector 322 may detect a signal eye-width value of the signal S3 having the optimal eye-height value. For example, the optimum eye height of the signal S3 may be the maximum eye height of the detected signal S3 during the period when the modulation circuit 311 modulates the signal S1 by using one of the first type parameters P1(1) -P1 (N). From another perspective, during the modulation circuit 311 modulates the signal S1 by using one of the first type parameters P1(1) -P1 (N), the detected signal eye height value EH and the corresponding signal eye width value EW correspond to a combination of the first type parameter and the second type parameter.
Referring to fig. 3B, it is assumed that the first type and the second type of parameters used and the detected eye height and eye width values are at least partially recorded in the table 34 during the adjustment of the equalizer circuit 31. The table 34 may be temporarily stored in the control circuit 32. The information in the table 34 indicates that, during the period when the modulation circuit 311 modulates the signal S1 by using the parameter P1(1), the modulation circuit 312 modulates the signal S2 by using the parameter P2(6) to obtain the signal S3 having the optimal signal eye height value EH (1) and the optimal signal eye width value EW (1); while the modulation circuit 311 modulates the signal S1 with the parameter P1(2), the modulation circuit 312 modulates the signal S2 with the parameter P2(9) to obtain the signal S3 with the optimal eye height EH (2) and eye width EW (2); while the modulation circuit 311 modulates the signal S1 with the parameter P1(3), the modulation circuit 312 modulates the signal S2 with the parameter P2(1) to obtain the signal S3 with the optimal eye height EH (3) and eye width EW (3); while the modulation circuit 311 modulates the signal S1 with the parameter P1(4), the modulation circuit 312 modulates the signal S2 with the parameter P2(7) to obtain the signal S3 with the optimal signal eye height EH (4) and signal eye width EW (4).
In an exemplary embodiment, the eye height detector 321 and the eye width detector 322 can adjust the output parameters according to the information recorded in the table 34, so as to achieve the synchronous optimization of the eye height and the eye width of the signal. For example, eye width detector 322 may compare signal eye width values EW (1) -EW (4) and may consider the largest of signal eye width values EW (1) -EW (4) as the best signal eye width value, e.g., signal eye width value EW (2). According to the obtained optimal signal eye width value, the eye height detector 321 may set the parameter P2(9) in the second type of parameters as the optimal second type of parameters obtained after calibration and instruct the modulation circuit 312 to use the parameter P2(9), and the eye width detector 322 may set the parameter P1(2) in the first type of parameters as the optimal first type of parameters obtained after calibration and instruct the modulation circuit 311 to use the parameter P1 (2). Thus, the synchronous optimization of the eye height and the eye width of the signal can be achieved.
It is noted that, in the example embodiment of fig. 3B, the eye-height value EH (1) is the optimal eye-height value obtained based on the use of the parameter P1(1), the eye-height value EH (2) is the optimal eye-height value obtained based on the use of the parameter P1(2), the eye-height value EH (3) is the optimal eye-height value obtained based on the use of the parameter P1(3), and the eye-height value EH (4) is the optimal eye-height value obtained based on the use of the parameter P1 (4). However, in practice, the eye height value EH (2) may be less than the eye height values EH (1), EH (3), and/or EH (4), and the invention is not limited.
Fig. 3C is a flowchart illustrating an equalizer adjustment method according to a second exemplary embodiment of the invention. Referring to fig. 3C, in step S301, a first signal is received. In step S302, a first modulation circuit (e.g., the modulation circuit 311) modulates a first signal using a first type parameter. In step S303, a second modulation circuit (e.g., the modulation circuit 312) modulates the first signal using a second type of parameter. In step S304, a signal eye height value of the modulated first signal and a signal eye width value of the modulated first signal are detected. In step S305, it is determined whether the performed modulation operation reaches a second predetermined modulation frequency. In an exemplary embodiment, the second predetermined number of modulation times is used to determine whether all the second type of parameters to be tested (e.g., the parameters P2(1) -P2 (M)) are used.
If it is determined in step S305 that the performed modulation operation has not reached the second predetermined modulation number (e.g., there is an unused second type parameter), in step S306, the used second type parameter is adjusted (but the used first type parameter is not changed) and step S303 is repeated. In other words, if the determination in step S305 is negative, the first modulation circuit maintains the currently used first type of parameter, and the second modulation circuit switches to use the next second type of parameter to be tested.
If step S305 determines that the performed modulation operation has reached the second predetermined modulation number (e.g., all the second type parameters to be tested have been used), in step S307, the signal eye width value of the first signal with the best signal eye height value is recorded. In step S308, it is determined whether the performed modulation operation reaches a first predetermined modulation frequency. In an exemplary embodiment, the first predetermined number of modulation times is used to determine whether all the first type of parameters to be tested (e.g., the parameters P1(1) -P1 (N)) are used.
If it is determined in step S308 that the performed modulation operation has not reached the first predetermined modulation number (e.g., the first type parameter that is not yet used), in step S309, the first type parameter that is used is adjusted and step S302 is repeated. In other words, if the determination in step S308 is negative, the first modulation circuit is switched to use the next first type parameter to be tested. After returning to step S302, steps S303 and S304, etc. may be executed successively.
If step S308 determines that the performed modulation operation has reached the first predetermined number of modulations (e.g., all the first type parameters to be tested have been used), in step S310, an optimal signal eye width value is determined according to the recorded signal eye width value. In step S311, a first type parameter to be used (i.e., an optimal first type parameter) and a second type parameter to be used (i.e., an optimal second type parameter) are determined according to the optimal signal eye width value. For example, in fig. 3B, assuming that the optimal signal eye width value is the signal eye width value EW (2), the first type parameter P1(2) can be determined as the optimal first type parameter, and the second type parameter P2(9) can be determined as the optimal second type parameter. Then, the first modulation circuit and the second modulation circuit can modulate the subsequently received signal by using the optimal first type parameter and the optimal second type parameter respectively so as to improve the signal quality of the received signal.
Third exemplary embodiment
Fig. 4A is a schematic diagram of a signal receiving circuit according to a third exemplary embodiment of the invention. Fig. 4B is a diagram illustrating a table recorded with a first type parameter, a second type parameter, a signal eye height value and a signal eye width value according to a third exemplary embodiment of the invention. Referring to fig. 4A, the signal receiving circuit 40 includes an equalizer circuit 41, a control circuit 42, and a clock and data recovery circuit 43. The clock and data recovery circuit 43 is the same as or similar to the clock and data recovery circuit 13 in fig. 1A, and is not described herein again.
The equalizer circuit 41 includes modulation circuits 411 and 412. The modulation circuit 411 is configured to receive the second type parameters P2(1) -P2 (M) and modulate the signal S1 according to the second type parameters P2(1) -P2 (M) to output a signal S2. The modulation circuit 412 is configured to receive the first type parameters P1(1) -P1 (N) and modulate the signal S2 according to the first type parameters P1(1) -P1 (N) to output a signal S3. For example, the modulation circuit 411 may include at least one decision feedback equalizer, and/or the modulation circuit 412 may include at least one continuous time linear equalizer.
The control circuit 42 includes an eye width detector 421 and an eye height detector 422. Eye height width detector 421 is used for analyzing signal S3 and detecting signal eye width value EW of signal S3. The eye height detector 422 is used for analyzing the signal S3 and detecting the signal eye height H of the signal S3. The eye width detector 421 can adjust the output first type parameters P1(1) -P1 (N) according to the detected signal eye width value EW. The eye-height detector 422 may adjust the output second-type parameters P2(1) -P2 (M) according to the detected signal eye-height value EH.
In an exemplary embodiment, the eye-height detector 422 may output a parameter P2(s) for use by the modulation circuit 411, where s is between 1 and M. During the period when the modulation circuit 411 modulates the signal S1 with the parameter P2(S), the eye width detector 421 may sequentially output parameters P1(t) to P1(u), where t and u are integers less than or equal to N, and t is less than u. In other words, while the modulation circuit 411 modulates the signal S1 with the parameter P2(S), the modulation circuit 412 modulates the signal S2 with the parameters P1(t) -P1 (u) in sequence.
After the modulation circuit 412 modulates the signal S2 by using the parameters P1(t) -P1 (u) sequentially, the eye-height detector 422 can output a parameter P2(v) for the modulation circuit 411, where v is between 1 and M, and v is not equal to S. During the period when the modulation circuit 411 modulates the signal S1 with the parameter P2(v), the eye width detector 421 may sequentially output parameters P1(w) to P1(x), where w and x are integers less than or equal to N, and w is less than x. In other words, while the modulation circuit 411 modulates the signal S1 by using the parameter P2(v), the modulation circuit 412 modulates the signal S2 by using the parameters P1(w) to P1(x) in sequence. By analogy, in an exemplary embodiment, the modulation circuit 411 may sequentially modulate the signal S1 using at least a portion of the second type of parameters P2(1) to P2(M), and the modulation circuit 412 may sequentially modulate the signal S2 using at least a portion of the first type of parameters P1(1) to P1(N) while the modulation circuit 411 modulates the signal S1 using one of the second type of parameters P2(1) to P2 (M).
In an exemplary embodiment, during the modulation circuit 411 modulates the signal S1 by using one of the second type parameters P2(1) -P2 (M), the eye width detector 421 may dynamically adjust the output first type parameter according to the detected eye width value EW of the signal. For example, in an exemplary embodiment, the eye width detector 421 can adjust the first type of parameter of the output according to the detected signal eye width value EW by using a continuous time linear algorithm to achieve the optimization of the detected signal eye width value EW. Alternatively, in an exemplary embodiment, the eye width detector 421 may also use a blind measurement method or other algorithm to adjust the first type parameter of the output, and the invention is not limited thereto.
In an exemplary embodiment, during the modulation circuit 411 modulates the signal S1 by using one of the second type parameters P2(1) -P2 (M), the eye width detector 421 may detect the optimal eye width value of the signal S3 and the eye height detector 422 may detect the eye height value of the signal S3 having the optimal eye width value. For example, the optimum signal eye width value of the signal S3 may be the maximum of a plurality of signal eye width values of the detected signal S3 during the period when the modulation circuit 411 modulates the signal S1 by using any one of the second-type parameters P2(1) -P2 (M). From another perspective, during the modulation circuit 411 modulates the signal S1 by using one of the second type parameters P2(1) -P2 (M), the detected signal eye width value EH and the corresponding signal eye height value EW also correspond to a combination of the first type parameter and the second type parameter.
Referring to fig. 4B, it is assumed that the first type and the second type of parameters used and the detected eye height and eye width values are at least partially recorded in the table 44 during the adjustment of the equalizer circuit 41. The table 44 may be temporarily stored in the control circuit 42. The information in table 44 indicates that, during the period when the modulation circuit 411 modulates the signal S1 by using the parameter P2(1), the modulation circuit 412 modulates the signal S2 by using the parameter P1(3) to obtain the signal S3 with the optimal signal eye width value EW (1) and signal eye height value EH (1); while the modulation circuit 411 modulates the signal S1 by using the parameter P2(2), the modulation circuit 412 modulates the signal S2 by using the parameter P1(1) to obtain the signal S3 having the optimal signal eye width value EW (2) and the optimal signal eye height value EH (2); while the modulation circuit 411 modulates the signal S1 by using the parameter P2(3), the modulation circuit 412 modulates the signal S2 by using the parameter P1(5) to obtain the signal S3 having the optimal signal eye width value EW (3) and the optimal signal eye height value EH (3); and while the modulation circuit 411 modulates the signal S1 by using the parameter P2(4), the modulation circuit 412 modulates the signal S2 by using the parameter P1(2) to obtain the signal S3 with the optimal signal eye width value EW (4) and signal eye height value EH (4).
In an exemplary embodiment, the eye width detector 421 and the eye height detector 422 can dynamically adjust the output parameters according to the information recorded in the table 44, so as to achieve the synchronous optimization of the eye width and the eye height of the signal. For example, eye height detector 422 may compare signal eye height values EH (1) -EH (4) and may consider the largest of signal eye height values EH (1) -EH (4) as the optimal signal eye height value, e.g., signal eye height value EH (3). Alternatively, in an exemplary embodiment, the eye-height detector 422 may use a least-mean-square algorithm to determine the optimal eye-height value from the eye-height values EH (1) -EH (4).
According to the obtained optimal signal eye height value, the eye width detector 421 may set the parameter P1(5) in the first type of parameters as the optimal first type of parameters obtained after calibration and instruct the modulation circuit 412 to use the parameter P1(5), and the eye height detector 422 may set the parameter P2(3) in the second type of parameters as the optimal second type of parameters obtained after calibration and instruct the modulation circuit 411 to use the parameter P2 (3). Thus, the synchronous optimization of the eye height and the eye width of the signal can be achieved.
Note that, in the example embodiment of fig. 4B, the signal eye width value EW (1) is the optimum signal eye width value obtained based on the use of the parameter P2(1), the signal eye width value EW (2) is the optimum signal eye width value obtained based on the use of the parameter P2(2), the signal eye width value EW (3) is the optimum signal eye width value obtained based on the use of the parameter P2(3), and the signal eye width value EW (4) is the optimum signal eye width value obtained based on the use of the parameter P2 (4). In practice, however, signal eye width value EW (3) may be less than signal eye width values EW (1), EW (2) and/or EW (4), although the invention is not limited.
Fig. 4C is a flowchart illustrating an equalizer adjustment method according to a third exemplary embodiment of the invention. Referring to fig. 4C, in step S401, a first signal is received. In step S402, a second modulation circuit (e.g., modulation circuit 411) modulates the first signal using a second type of parameter. In step S403, a first modulation circuit (e.g., the modulation circuit 412) modulates a first signal using a first type parameter. In step S404, a signal eye width value of the modulated first signal and a signal eye height value of the modulated first signal are detected. In step S405, it is determined whether the performed modulation operation reaches a first preset modulation frequency. For example, the first predetermined number of modulation times can be used to determine whether all the first type of parameters to be tested (e.g., the parameters P1(1) -P1 (N)) are used.
If it is determined in step S405 that the performed modulation operation has not reached the first predetermined number of modulations (e.g., there is still an unused first type parameter), in step S406, the used first type parameter is adjusted (but the used second type parameter is not changed) and step S403 is repeated. In other words, if the determination in step S405 is negative, the second modulation circuit maintains the currently used second type of parameter, and the first modulation circuit switches to use the next first type of parameter to be tested.
If step S405 determines that the performed modulation operation has reached the first predetermined modulation number (e.g., all the first type parameters to be tested have been used), in step S407, the eye height value of the first signal with the best eye width value is recorded. In step S408, it is determined whether the performed modulation operation reaches a second predetermined modulation frequency. For example, the second predetermined modulation times can be used to determine whether all the second type of parameters to be tested (e.g., the parameters P2(1) -P2 (M)) are used.
If it is determined in step S408 that the performed modulation operation has not reached the second predetermined modulation number (e.g., there is still unused second type parameter), in step S409, the used second type parameter is adjusted and step S402 is repeated. In other words, if the determination in step S408 is negative, the second modulation circuit is switched to use the next second type parameter to be tested.
If step S408 determines that the performed modulation operation has reached a second predetermined number of modulations (e.g., all of the second type parameters to be tested have been used), then in step S410, an optimal eye height value is determined according to the recorded eye height values. In step S411, a first type parameter to be used (i.e., an optimal first type parameter) and a second type parameter to be used (i.e., an optimal second type parameter) are determined according to the optimal eye height. For example, in fig. 4B, assuming that the optimal eye height is the eye height EH (3), the first type P1(5) may be determined as the optimal first type and the second type P2(3) may be determined as the optimal second type. Then, the first modulation circuit and the second modulation circuit can modulate the subsequently received signal by using the optimal first type parameter and the optimal second type parameter respectively so as to improve the signal quality of the received signal.
According to the foregoing exemplary embodiments, the control circuit in the signal receiving circuit may adjust the first type parameter and the second type parameter according to the eye width value and the eye height value of the modulated first signal, respectively (or independently). Even though the eye width and the eye height of the first signal may affect each other during the signal modulation process, the (optimal) first type parameter and the (optimal) second type parameter obtained through the calibration may be used to generate the signal with the best signal quality for the subsequent signal analysis operation (e.g., sampling, etc.). In addition, the (optimal) first-type parameter and the (optimal) second-type parameter which are finally determined to be used are respectively adjusted by eye width detection and eye height detection, rather than being generated by only a single adjustment mechanism of eye width detection or eye height detection.
However, the steps in fig. 2, fig. 3C and fig. 4C have been described in detail above, and are not repeated herein. It is to be noted that, the steps in fig. 2, fig. 3C and fig. 4C can be implemented as a plurality of program codes or circuits, and the present invention is not limited thereto. In addition, the methods shown in fig. 2, fig. 3C and fig. 4C may be used with the above exemplary embodiments, or may be used alone, and the present invention is not limited thereto.
It should be noted that, in some exemplary embodiments not mentioned above, the connection relationship of at least some of the components in the signal receiving circuits 10, 30 and 40 may be adjusted, at least some of the components in the signal receiving circuits 10, 30 and 40 may be replaced by circuit components with the same or similar functions, and more circuit components may be added to the signal receiving circuits 10, 30 and 40 to provide additional functions.
In addition, the aforementioned control circuits 12, 32 and 42 can be composed of a plurality of circuit components in combination with an embedded controller or microcontroller. For example, eye height detector 321, eye height detector 422, eye width detector 322, AND eye width detector 421 may each include at least one of a sampling circuit, a logic (e.g., AND, OR, AND/OR XOR) circuit, a delay circuit, a flip-flop circuit, a latch circuit, an embedded controller, AND a microcontroller. In addition, in an exemplary embodiment, the control circuits 12, 32 and 42 may also include at least one memory and a microprocessor, and the microprocessor may load the required programs and information from the memory to perform the corresponding functions.
In an example embodiment, the receive side circuitry is configured for use in a memory storage device (also referred to as a memory storage system). Generally, a memory storage device includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.
FIG. 5 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 6 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.
Referring to fig. 5 and 6, the host system 71 generally includes a processor 711, a Random Access Memory (RAM) 712, a Read Only Memory (ROM) 713, and a data transmission interface 714. The processor 711, the RAM 712, the ROM 713, and the data transfer interface 714 are all coupled to the system bus 110.
In the exemplary embodiment, host system 71 is coupled to memory storage device 70 via data transfer interface 714. For example, the host system 71 may store data to the memory storage device 70 or read data from the memory storage device 70 via the data transmission interface 114. The host system 71 is connected to the I/O device 72 via a system bus 710. For example, the host system 71 may transmit output signals to the I/O device 72 or receive input signals from the I/O device 72 via the system bus 710.
In the present exemplary embodiment, the processor 711, the ram 712, the rom 713 and the data transmission interface 714 may be disposed on the motherboard 80 of the host system 71. The number of data transfer interfaces 714 may be one or more. The motherboard 80 may be connected to the memory storage device 70 via a wired or wireless connection via the data transmission interface 114. The memory storage device 70 may be, for example, a U disk 801, a memory card 802, a Solid State Drive (SSD) 803, or a wireless memory storage device 804. The wireless memory storage 804 may be, for example, a Near Field Communication (NFC) memory storage, a wireless facsimile (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a low power Bluetooth memory storage (iBeacon), which are based on various wireless Communication technologies. In addition, the motherboard 80 may also be connected to various I/O devices such as a Global Positioning System (GPS) module 805, a network interface card 806, a wireless transmission device 807, a keyboard 808, a screen 809, and a speaker 810 through a System bus 710. For example, in an exemplary embodiment, the motherboard 80 may access the wireless memory storage device 804 via the wireless transmission device 807.
In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 7 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 7, in another exemplary embodiment, the host system 91 may also be a Digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 90 may be various non-volatile memory storage devices such as a Secure Digital (SD) card 92, a Compact Flash (CF) card 93, or an embedded storage device 94. The embedded memory device 94 may include embedded Multi-Media Card (eMMC) 941 and/or embedded Multi-Chip Package (eMCP) 942, which may be of various types to directly connect the memory module to the host system substrate.
FIG. 8 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to fig. 8, the memory storage device 70 includes a connection interface unit 1002, a memory control circuit unit 1004, and a rewritable nonvolatile memory module 1006.
The connection interface unit 1002 is used to connect the memory storage device 70 to the host system 71. In the exemplary embodiment, connection interface unit 1002 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 1002 may also conform to Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, High-Speed Peripheral Component connection interface (PCI Express) standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) interface standard, Ultra High Speed-II (UHS-II) interface standard, Memory Stick (Memory Stick, MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, Universal Flash Memory (Flash Storage, CF interface standard, Device Electronics interface (Electronic drive interface), IDE) standard or other suitable standard. The connection interface unit 1002 may be packaged in one chip with the memory control circuit unit 1004, or the connection interface unit 1002 may be disposed outside a chip including the memory control circuit unit 1004.
In an exemplary embodiment, the signal receiving circuit 10 of fig. 1A, the signal receiving circuit 30 of fig. 3A, or the signal receiving circuit 40 of fig. 4A is disposed in the connection interface unit 1002 to receive and process the signal S1 from the host system 71. Alternatively, in an example embodiment, at least a portion of the signal receiving circuit 10 of fig. 1A, the signal receiving circuit 30 of fig. 3A, or the signal receiving circuit 40 of fig. 4A may also be configured in the memory control circuit unit 1004 and may likewise receive and process the signal S1 from the host system 71.
The memory control circuit unit 1004 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a solid state type, and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 1006 according to commands of the host system 71.
The rewritable nonvolatile memory module 1006 is connected to the memory control circuit unit 1004 and is used for storing data written by the host system 71. The rewritable nonvolatile memory module 1006 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module capable of storing 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 bits in one memory Cell), a Multi-Level Cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.
Each memory cell in the rewritable nonvolatile memory module 1006 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 1006 has multiple memory states. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.
In the present exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 1006 form a plurality of physical programming cells, and the physical programming cells form a plurality of physical erasing cells. Specifically, the memory cells on the same word line constitute one or more physical programming cells. If each memory cell can store more than 2 bits, the physical programming cells on the same word line can be classified into at least a lower physical programming cell and an upper physical programming cell. For example, the Least Significant Bit (LSB) of a cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.
In the present exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, the physical programming unit is a physical page (page) or a physical fan (sector). If the physical program cells are physical pages, the physical program cells usually include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundant bit region stores system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit region includes 32 physical fans, and the size of one physical fan is 512-bit group (B). However, in other example embodiments, the data bit region may also include 8, 16, or a greater or lesser number of physical fans, and the size of each physical fan may also be greater or lesser. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. For example, the physical erase unit is a physical block (block).
In summary, the first modulation circuit and the second modulation circuit in the equalizer circuit can modulate the first signal according to the first type of parameter and the second type of parameter, respectively. Then, according to the signal eye width value and the signal eye height value of the modulated first signal, the first type of parameter used by the first modulation circuit and the second type of parameter used by the second modulation circuit can be respectively and independently determined and adjusted, thereby improving the adjustment accuracy of the equalizer.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (21)

1. An equalizer adjusting method for a signal receiving circuit of a memory storage device, the equalizer adjusting method comprising:
receiving a first signal;
modulating the first signal by a first modulation circuit according to a first type of parameter and modulating the first signal by a second modulation circuit according to a second type of parameter;
detecting a signal eye width value of the modulated first signal and a signal eye height value of the modulated first signal; and
adjusting the first type of parameter according to the detected signal eye width value and adjusting the second type of parameter according to the detected signal eye height value,
wherein the step of modulating the first signal by the first modulation circuit according to the first type of parameter and modulating the first signal by the second modulation circuit according to the second type of parameter comprises:
while one of the first modulation circuit and the second modulation circuit modulates the first signal by using a first modulation parameter, the other of the first modulation circuit and the second modulation circuit sequentially modulates the first signal by using a plurality of second modulation parameters.
2. The equalizer tuning method as claimed in claim 1, wherein the step of modulating the first signal by the first modulation circuit according to the first type of parameter and modulating the first signal by the second modulation circuit according to the second type of parameter further comprises:
modulating the first signal by the other of the first modulation circuit and the second modulation circuit sequentially using a plurality of fourth modulation parameters during the period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using a third modulation parameter,
wherein the first modulation parameter is different from the third modulation parameter.
3. The equalizer adjustment method according to claim 2, wherein the step of detecting the eye width value of the modulated first signal and the eye height value of the modulated first signal comprises:
detecting a first signal eye width value of the first signal having a first signal eye height value during the period when the first signal is modulated by the one of the first modulation circuit and the second modulation circuit by using the first modulation parameter; and
detecting a second signal eye width value of the first signal having a second signal eye height value during the period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the third modulation parameter,
wherein the step of adjusting the first type of parameter according to the detected signal eye width value and adjusting the second type of parameter according to the detected signal eye height value comprises:
and adjusting the first type of parameters according to the first signal eye width value and the second signal eye width value.
4. The equalizer adjustment method according to claim 3, wherein the first eye height is an optimum eye height of the first signal detected during the modulation of the first signal by the one of the first modulation circuit and the second modulation circuit using the first modulation parameter,
wherein the second eye height is an optimum eye height of the first signal detected during the modulation of the first signal by the one of the first modulation circuit and the second modulation circuit using the third modulation parameter.
5. The equalizer adjustment method according to claim 2, wherein the step of detecting the eye width value of the modulated first signal and the eye height value of the modulated first signal comprises:
detecting a first signal eye height value of the first signal having a first signal eye width value during the period when the first signal is modulated by the one of the first modulation circuit and the second modulation circuit using the first modulation parameter; and
detecting a second eye height value of the first signal having a second eye width value during the period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the third modulation parameter,
wherein the step of adjusting the first type of parameter according to the detected signal eye width value and adjusting the second type of parameter according to the detected signal eye height value comprises:
and adjusting the second type of parameter according to the first signal eye height value and the second signal eye height value.
6. The equalizer adjustment method according to claim 5, wherein the first signal eye width value is an optimal signal eye width value of the first signal detected during the period when the one of the first modulation circuit and the second modulation circuit modulates the first signal using the first modulation parameter,
wherein the second signal eye width value is an optimal signal eye width value of the first signal detected during the period when the one of the first modulation circuit and the second modulation circuit modulates the first signal using the third modulation parameter.
7. The equalizer tuning method as claimed in claim 1, further comprising:
performing a phase-locking operation on the modulated first signal by a clock and data recovery circuit.
8. A signal receiving circuit for a memory storage device, the signal receiving circuit comprising:
an equalizer circuit; and
a control circuit connected to the equalizer circuit,
wherein the equalizer circuit comprises a first modulation circuit and a second modulation circuit,
wherein the equalizer circuit is configured to receive a first signal,
wherein the first modulation circuit is used for modulating the first signal according to a first type of parameter and the second modulation circuit is used for modulating the first signal according to a second type of parameter,
wherein the control circuit is used for detecting a signal eye width value of the modulated first signal and a signal eye height value of the modulated first signal,
wherein the control circuit is further configured to adjust the first type of parameter according to the detected eye width value and adjust the second type of parameter according to the detected eye height value,
wherein the operations of the first modulation circuit modulating the first signal according to the first type of parameter and the second modulation circuit modulating the first signal according to the second type of parameter comprise:
while one of the first modulation circuit and the second modulation circuit modulates the first signal by using a first modulation parameter, the other of the first modulation circuit and the second modulation circuit sequentially modulates the first signal by using a plurality of second modulation parameters.
9. The signal receiving circuit of claim 8, wherein the operation of the first modulation circuit modulating the first signal according to the first type of parameter and the second modulation circuit modulating the first signal according to the second type of parameter further comprises:
modulating the first signal by the other of the first modulation circuit and the second modulation circuit sequentially using a plurality of fourth modulation parameters during the period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using a third modulation parameter,
wherein the first modulation parameter is different from the third modulation parameter.
10. The signal receiving circuit of claim 9, wherein the control circuit comprises an eye width detector, and the eye width detector is connected to the first modulation circuit and the second modulation circuit,
wherein the eye width detector is configured to detect a first signal eye width value of the first signal having a first signal eye height value during a period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the first modulation parameter,
wherein the eye width detector is further configured to detect a second signal eye width value of the first signal having a second signal eye height value during the period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the third modulation parameter,
wherein the eye width detector is further configured to adjust the first type of parameter according to the first signal eye width value and the second signal eye width value.
11. The signal receiving circuit of claim 10, wherein the control circuit further comprises an eye-height detector, and the eye-height detector is connected to the first modulation circuit and the second modulation circuit,
wherein the first eye height value is an optimum eye height value of the first signal detected by the eye height detector during a period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the first modulation parameter,
wherein the second eye height value is an optimal eye height value of the first signal detected by the eye height detector during a period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the third modulation parameter.
12. The signal receiving circuit of claim 8, wherein the control circuit comprises an eye-height detector, and the eye-height detector is connected to the first modulation circuit and the second modulation circuit,
wherein the eye-height detector is configured to detect a first signal eye-height value of the first signal having a first signal eye-width value during a period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the first modulation parameter,
wherein the eye-height detector is further configured to detect a second signal eye-height value of the first signal having a second signal eye-width value during a period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using a third modulation parameter,
wherein the eye-height detector is further configured to adjust the second type of parameter according to the first eye-height value and the second eye-height value.
13. The signal receiving circuit of claim 12, wherein the control circuit further comprises an eye width detector, and the eye width detector is connected to the first modulation circuit and the second modulation circuit,
wherein the first signal eye width value is an optimal signal eye width value of the first signal detected by the eye width detector during a period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the first modulation parameter,
wherein the second signal eye width value is an optimal signal eye width value of the first signal detected by the eye width detector during a period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the third modulation parameter.
14. The signal receiving circuit of claim 8, further comprising:
a clock and data recovery circuit connected to the equalizer circuit and the control circuit,
wherein the clock and data recovery circuit is configured to perform a phase-lock operation on the modulated first signal.
15. A memory storage device, comprising:
a connection interface unit for connecting to a host system;
a rewritable non-volatile memory module; and
a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,
wherein the connection interface unit includes a signal receiving circuit,
wherein the signal receiving circuit comprises a first modulation circuit and a second modulation circuit,
wherein the signal receiving circuit is used for receiving a first signal,
wherein the first modulation circuit is used for modulating the first signal according to a first type of parameter and the second modulation circuit is used for modulating the first signal according to a second type of parameter,
wherein the signal receiving circuit is used for detecting a signal eye width value of the modulated first signal and a signal eye height value of the modulated first signal,
wherein the signal receiving circuit is further configured to adjust the first type of parameter according to the detected eye width value and adjust the second type of parameter according to the detected eye height value,
wherein the operations of the first modulation circuit modulating the first signal according to the first type of parameter and the second modulation circuit modulating the first signal according to the second type of parameter comprise:
while one of the first modulation circuit and the second modulation circuit modulates the first signal by using a first modulation parameter, the other of the first modulation circuit and the second modulation circuit sequentially modulates the first signal by using a plurality of second modulation parameters.
16. The memory storage device of claim 15, wherein the operation of the first modulation circuit modulating the first signal according to the first type of parameter and the second modulation circuit modulating the first signal according to the second type of parameter further comprises:
modulating the first signal by the other of the first modulation circuit and the second modulation circuit using a plurality of fourth modulation parameters in sequence while the one of the first modulation circuit and the second modulation circuit modulates the first signal using a third modulation parameter,
wherein the first modulation parameter is different from the third modulation parameter.
17. The memory storage device of claim 16, wherein the signal receiving circuit further comprises a control circuit, and the control circuit is connected to the first modulation circuit and the second modulation circuit,
wherein the control circuit is configured to detect a first signal eye width value of the first signal having a first signal eye height value during a period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the first modulation parameter,
wherein the control circuit is further configured to detect a second eye width value of the first signal having a second eye height value during the period when the one of the first modulation circuit and the second modulation circuit modulates the first signal using the third modulation parameter,
the control circuit is further configured to adjust the first type of parameter according to the first signal eye width value and the second signal eye width value.
18. The memory storage device of claim 17, wherein the first signal eye height value is an optimal signal eye height value of the first signal detected by the control circuit during modulation of the first signal by the one of the first modulation circuit and the second modulation circuit using the first modulation parameter,
wherein the second eye height is an optimum eye height of the first signal detected by the control circuit during a period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the third modulation parameter.
19. The memory storage device of claim 16, wherein the signal receiving circuit further comprises a control circuit, and the control circuit is connected to the first modulation circuit and the second modulation circuit,
wherein the control circuit is configured to detect a first eye height value of the first signal having a first eye width value during a period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the first modulation parameter,
wherein the control circuit is further configured to detect a second eye height value of the first signal having a second eye width value during the period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the third modulation parameter,
wherein the control circuit is further configured to adjust the second type of parameter according to the first eye height value and the second eye height value.
20. The memory storage device of claim 19, wherein the first signal eye width value is an optimal signal eye width value of the first signal detected by the control circuit during the modulation of the first signal by the one of the first modulation circuit and the second modulation circuit using the first modulation parameter,
wherein the second signal eye width value is an optimal signal eye width value of the first signal detected by the control circuit during a period in which the one of the first modulation circuit and the second modulation circuit modulates the first signal using the third modulation parameter.
21. The memory storage device of claim 15, wherein the signal receiving circuit is further to perform a phase lock operation on the first modulated signal.
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