CN110290227A - Dynamic allocation method, system and the storage medium of IC bus address - Google Patents
Dynamic allocation method, system and the storage medium of IC bus address Download PDFInfo
- Publication number
- CN110290227A CN110290227A CN201910448825.2A CN201910448825A CN110290227A CN 110290227 A CN110290227 A CN 110290227A CN 201910448825 A CN201910448825 A CN 201910448825A CN 110290227 A CN110290227 A CN 110290227A
- Authority
- CN
- China
- Prior art keywords
- address
- slave
- bus
- equipment
- host
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L61/00—Network arrangements, protocols or services for addressing or naming
- H04L61/50—Address allocation
Abstract
The invention discloses the dynamic allocation method of IC bus address, system and storage medium, method includes: to send address distribution instruction to the first slave by host based on address allocation rule；Address distribution instruction is successively sent to the second slave by the first slave；The first number of addresses information is successively fed back into the host by the second slave；According to the first number of addresses information, IC bus is opened by host；Wherein, second slave is the least significant end slave in IC bus.The present invention can realize and distribute the dynamic arrangement of slave devices address, improve efficiency in the case where not disassembling slave devices；In addition, for by dismantling linking relationship, come the case where increasing and decreasing slave devices, the present invention can distribute the address stable instructed to keep slave devices by address, practicability height can be widely applied to communication technique field.
Description
Technical field
The present invention relates to communication technique field, the especially dynamic allocation method of IC bus address, system and deposit
Storage media.
Background technique
IIC, that is, Inter-Integrated Circuit (IC bus), this bus type are by Philip half
Conductor company designs in early eighties, is primarily used to connection integrated circuit (ICS), IIC is a kind of multidirectional control
Bus, that is to say, that multiple chips may be coupled under same bus structure, while each chip all can serve as real time data
The voltage input of transmission.This mode simplifies signal transmission bus interface.Only there are two two-way signals for the main composition of IIC
Line, one is data line SDA, and one is clock line SCL.
In the more device systems for connecting into chain structure, using must define device address before iic bus, such as
The chain device cluster without branch node being formed by connecting by sub- equipment needs to rearrange this little equipment, and address
The rule of allocation order is usually: the address of one end (head end) equipment is smaller, and the address of the other end (end) equipment is larger, owns
The ascending distribution in device address.Existing more device systems do not have dynamic address allocation ability, rearrange each time
When connexon equipment, address definition will be carried out to each sub- equipment, consume a large amount of working time, it is not practical enough.
In addition, being required to carry out row-and-column address with particular order for some specific more device systems, set when this more
Standby system needs when increasing and decreasing sub- equipment, inevitably to will cause by dismantling linking relationship and break particular order
It is bad, it is unfavorable for more device systems and flexibly increases and decreases sub- equipment, practicability is low.
Summary of the invention
In view of this, the embodiment of the present invention provides, a kind of high-efficient and practicability is high, and IC bus address is moved
State distribution method, system and storage medium.
In a first aspect, the embodiment of the invention provides the dynamic allocation method of IC bus address, including following step
It is rapid:
Based on address allocation rule, address distribution instruction is sent to the first slave by host；
Address distribution instruction is successively sent to the second slave by the first slave；
The first number of addresses information is successively fed back into the host by the second slave；
According to the first number of addresses information, IC bus is opened by host；
Wherein, second slave is the least significant end slave in IC bus.
Further, further comprising the steps of:
Judge with the presence or absence of branch in IC bus, if so, passing through the corresponding node module of the branch for ground
Location distribution instruction is successively sent to all devices on branch, and performs the next step rapid；Conversely, being then not processed；
It is through the most end end equipment on the branch after receiving address distribution instruction, the second number of addresses information is layer-by-layer
Feed back to the node module；
The the second number of addresses information received and address distribution instruction are sent to next node by the node module.
Further, the communications protocol between the host and slave or between slave and slave includes but is not limited to
USART agreement and/or SPI protocol；
The slave is equipped at least two communication interfaces.
Further, the address allocation rule includes:
The ascending order descending rule arranged by number of addresses size；
The functional rule arranged by preset function relationship；
The mapping ruler arranged by default mapping relations.
Further, the slave receives information to host feedback command according to the address distribution instruction received.
Further, address distribution instruction include but is not limited to the address information of sender, address allocation rule information,
Address generating function and cryptographic means.
Further, the maximum device number of IC bus is stored on the host.
Second aspect, the embodiment of the invention also provides the dynamic allocation systems of IC bus address, comprising: host
With several slaves；
Wherein, the host sends address distribution instruction to the first slave for being based on address allocation rule；And root
According to the first number of addresses information, IC bus is opened；
First slave, for address distribution instruction to be successively sent to the second slave；
Second slave, for the first number of addresses information successively to be fed back to the host；
Second slave is the least significant end slave in IC bus.
The third aspect, the embodiment of the invention also provides the dynamic allocation systems of IC bus address, comprising:
At least one processor；
At least one processor, for storing at least one program；
When at least one described program is executed by least one described processor, so that at least one described processor is realized
The dynamic allocation method of the IC bus address.
Fourth aspect, the embodiment of the invention also provides a kind of storage mediums, wherein being stored with the executable finger of processor
It enables, the executable instruction of the processor is when executed by the processor for executing the dynamic of the IC bus address
Distribution method.
One or more technical solutions in the embodiments of the present invention have the advantages that the embodiment of the present invention is based on
Address allocation rule sends address distribution instruction to the first slave by host, is then divided the address by the first slave
It successively is sent to the second slave with instruction, the first number of addresses information is successively then fed back to by the host by the second slave,
IC bus is opened finally by host；The present invention can be realized and be set to slave in the case where not disassembling slave devices
The dynamic arrangement of standby address is distributed, and efficiency is improved；In addition, for the feelings for increasing and decreasing slave devices by dismantling linking relationship
Condition, the present invention can distribute instruction by address to keep the address stable of slave devices, and practicability is high.
Detailed description of the invention
Fig. 1 is the step flow chart of the embodiment of the present invention；
Fig. 2 is more device systems structural schematic diagrams without branch node of the embodiment of the present invention；
Fig. 3 is more device systems structural schematic diagrams of the multi-branch node of the embodiment of the present invention；
Fig. 4 is the serial ports connection schematic diagram of more device systems of the multi-branch node of the embodiment of the present invention；
Fig. 5 is the address assigning step flow chart of more device systems of the multi-branch node of the embodiment of the present invention.
Specific embodiment
The present invention is further explained and is illustrated with specific embodiment with reference to the accompanying drawings of the specification.For of the invention real
The step number in example is applied, is arranged only for the purposes of illustrating explanation, any restriction is not done to the sequence between step, is implemented
The execution sequence of each step in example can be adaptively adjusted according to the understanding of those skilled in the art.
Referring to Fig.1, the embodiment of the invention provides the dynamic allocation methods of IC bus address, including following step
It is rapid:
Based on address allocation rule, address distribution instruction is sent to the first slave by host；
Address distribution instruction is successively sent to the second slave by the first slave；
The first number of addresses information is successively fed back into the host by the second slave；
According to the first number of addresses information, IC bus is opened by host；
Wherein, second slave is the least significant end slave in IC bus.
It is further used as preferred embodiment, further comprising the steps of:
Judge with the presence or absence of branch in IC bus, if so, passing through the corresponding node module of the branch for ground
Location distribution instruction is successively sent to all devices on branch, and performs the next step rapid；Conversely, being then not processed；
It is through the most end end equipment on the branch after receiving address distribution instruction, the second number of addresses information is layer-by-layer
Feed back to the node module；
The the second number of addresses information received and address distribution instruction are sent to next node by the node module.
It is further used as preferred embodiment, the communication association between the host and slave or between slave and slave
View includes but is not limited to USART agreement and/or SPI protocol；
The slave is equipped at least two communication interfaces.
It is further used as preferred embodiment, the address allocation rule includes:
The ascending order descending rule arranged by number of addresses size；
The functional rule arranged by preset function relationship；
The mapping ruler arranged by default mapping relations.
It is further used as preferred embodiment, the slave is fed back according to the address distribution instruction received to host
Command reception information.
It is further used as preferred embodiment, the address distribution instruction includes but is not limited to the address letter of sender
Breath, address allocation rule information, address generating function and cryptographic means.
It is further used as preferred embodiment, the maximum device number of IC bus is stored on the host.
The embodiment of the invention also provides the dynamic allocation systems of IC bus address, comprising: host and several
Slave；
Wherein, the host sends address distribution instruction to the first slave for being based on address allocation rule；And root
According to the first number of addresses information, IC bus is opened；
First slave, for address distribution instruction to be successively sent to the second slave；
Second slave, for the first number of addresses information successively to be fed back to the host；
Second slave is the least significant end slave in IC bus.
It is corresponding with the method for Fig. 1, the embodiment of the invention also provides the dynamic allocation system of IC bus address,
Include:
At least one processor；
At least one processor, for storing at least one program；
When at least one described program is executed by least one described processor, so that at least one described processor is realized
The dynamic allocation method of the IC bus address.
Below by taking chain is without more device systems of branch node structure as an example, the integrated electricity without node system is described in detail
The specific implementation step of the dynamic allocation method of road bus address:
As shown in Fig. 2, equipment (slave) A, B, C, D for four and host, it is desirable that connect into the chain of Fig. 2 without
More device systems of branch node structure, system are communicated when working using iic bus, it is desirable that no matter how to be connected between sub- equipment
It connects, the distribution of the address IIC remains 1,2,3,4.
Specific implementation step are as follows: host issues distribution instruction, address transmitting, number of addresses return, opens iic bus.
Such as: equipment is connected as A-B-C-D, and host first communicatively issues distribution command information, the information by with
Its sub- equipment A being connected directly is received, and sub- equipment A is assigned address=1 IIC, becomes slave, and then sub- equipment A will be processed
Information (information include sub- equipment B address information, i.e., the address+1 of sub- equipment A, address=2) be sent to directly phase
Sub- equipment B even, sub- equipment B are assigned address=2；And so on, until last sub- equipment D；Here it is address transmitting.
After last sub- equipment is assigned the address IIC, the equipment sum=information such as 4 are sent to and its phase by sub- equipment D
Upper one sub- equipment even, i.e., sub- equipment C, sub- equipment C send this information to sub- equipment B again, and so on, until host receives
To the information；Here it is number of addresses returns.So far, all sub- equipment, which are assigned the address IIC, becomes slave, and host knows address
The information such as number=4, that is, iic bus can be used to transmit data.
For another example, equipment is connected as B-D-A-C, and host first communicatively issues distribution command information, the information by with
Its sub- equipment B being connected directly is received, and sub- equipment B is assigned address=1 IIC, becomes slave, and then sub- equipment B will be processed
Information (information include sub- equipment D address information, i.e., the address+1 of sub- equipment B, address=2) be sent to directly phase
Sub- equipment D even, sub- equipment D are assigned address=2；And so on, until last sub- equipment C；Here it is address transmitting.
After last sub- equipment is assigned the address IIC, the equipment sum=information such as 4 are sent to coupled upper one by sub- equipment C
Sub- equipment, i.e., sub- equipment A, sub- equipment A send this information to sub- equipment D again, and so on, until host receives the letter
Breath；Here it is number of addresses returns.So far, all sub- equipment, which are assigned the address IIC, becomes slave, and host knows number of addresses=4
Etc. information, that is, iic bus can be used to transmit data.
If desired change the address of a certain sub- equipment, new address with address transfer mode or need to only be utilized enabled
Iic bus is sent to sub- equipment.The case where for address conflict, professional can be kept away in the way of enabling reserved address etc.
Exempt from address conflict, seldom repeats.
In practical applications, using this method can also deallocation, only need developer according to wish setting address arrange
Column rule, again using this without the address node IIC dynamic allocation method.
No matter what four sub- equipment, which do, arranges, or increases or decreases sub- number of devices, and this method can be pacified by certain rule
The address IIC of sub- equipment is arranged, and the address of some or multiple sub- equipment can be changed.
A kind of other application mode of the address no node IIC dynamic allocation method, in a row such as ascending order row-and-column address, descending
Certain function row-and-column address is pressed in location, belongs to the application of this method, not described here any more, professional should be able to understand its meaning；
Therefore different address arrangement sequences all belongs to the scope of protection of the present invention.
In conclusion the allocation step of more device systems of the present invention for chain without branch node structure are as follows:
Host issues distribution instruction, address transmitting, number of addresses return, opens iic bus.Host is first with the first communication side
Formula (such as SPI protocol) issues distribution command information, and first piece of sub- equipment which is directly connected receives, which sets
The standby assigned address IIC, becomes slave, then processed information is sent to directly connected next son by the sub- equipment
Equipment；And so on, until last sub- equipment；Here it is address transmitting.Last sub- equipment is assigned the address IIC
Afterwards, the information such as equipment sum are sent to upper one coupled sub- equipment, and so on, until host receives the information；
Here it is number of addresses returns.So far, sub- equipment, which is assigned the address IIC, becomes slave, and host knows the information such as number of addresses
Data are transmitted using the second communication modes (such as iic bus).
Below by taking chain there are more device systems of multiple branch node structures as an example, the collection of the multi-node system is described in detail
At the specific implementation step of the dynamic allocation method of circuit bus address:
As shown in figure 3, present embodiments providing a kind of dry more device systems of chain-branch.Include a host and multiple sons
Equipment, sub- equipment connect into dry chain-branched structure shown in Fig. 3.More device systems must include an IIC host, Yi Jiyi
A or multiple slaves between host and slave, between slave and slave, must have an IIC communication protocol connection, in addition to the IIC
Communication protocol must also have one or more kinds of communication modes, and support the communication mode equipped with two or more
Interface.In general, interface is respectively used to connection branch and dry chain.
As shown in figure 4, serial ports 0, serial ports 1 are for connecting dry chain, serial ports 2 connects in the system for connecting branch
Iic bus at the sub- equipment of more device systems be it is in parallel, by the address IIC distribution after system can directly use IIC agreement.
As shown in figure 5, sub- equipment is powered after booting, and waiting facilities signal and address allocation information, after receiving information, root
According to the information, the address IIC is set；And judge whether current device is branch chain equipment；If it is not, judging whether current device connects
Branch (whether being node module), if it is not, then dry chain device signal and address allocation information are sent to next sub- equipment, if working as
Preceding sub- equipment is branch equipment, then judges whether current device is branch terminals equipment；If so, the branch equipment that will have been counted
Number returns to a upper equipment；If it is not, then sending branch device signal and address allocation information to branch port, then wait branch
Number of devices information returns, then returns this information to an equipment, until information reaches node module.
If current device is connected to branch, become a node module, then to branch port send branch device signal and
Address allocation information, then branch number of devices information is waited to return until receiving.Further according to branch number of devices, to next sub- equipment
Send dry chain device signal and address allocation information.
Total number of addresses returns, and is the dry chain equipment upward one dry chain equipment transmission that sub- device cluster is connected to least significant end
Total number of addresses；Upward one sub- equipment transmits information to dry chain equipment again；And so on, until being transferred to host.Total number of devices
Equal to the sum of all branch equipment and dry chain equipment.
Host issues distribution instruction, address is transmitted, node-branch distribution, total number of addresses return, open iic bus.More than
After the completion of step, host and sub- equipment can be communicated by iic bus in parallel.
Specifically, the present embodiment is default distributes to equipment A for address 1, and equipment B ... is distributed to for address 10 in address 2
Distribute to equipment J.Based on method of the invention, when beginning, host sends the address (address 1) of A and doing for equipment A to equipment A
Chain facility information, according to set allocation rule, the address IIC is set as address 1 by A；Then equipment A sends address+1 to
Equipment B, after address is set as 2 by equipment B, due to being connected to branch on its serial ports 2, B determines that itself is node, and address is distributed
Information and branch facility information are sent to equipment C, and address is set as address 3 by equipment C, since C receives branch facility information, determine
Itself is the sub- equipment of branch, address allocation information and branch facility information is then sent to equipment D, equipment D is set as address
Address 4 determines itself for the sub- equipment of branch, since D equipment does not reconnect next since D receives branch facility information
Chain equipment, equipment D determine the sub- equipment that itself is branch terminals, then return the branch number of devices (number of devices=2) of statistics
It is returned again to back to C, C and gives equipment B, equipment B passes to equipment E according to number of devices information, by address=5；And so on, Zhi Daoshe
Standby J is arranged address=10；Due to, without reconnecting equipment, determining the end-equipment that itself is dry chain, then total equipment behind J
Number (number of devices=10) returns to dry chain equipment F, then arrives equipment E, and so on, until equipment A, then arrive host.
At this point, host has known the controllable device sum of whole system, each sub- equipment is according to set sequence
Address is assigned in rule；System can open iic bus and communicate.Due to the characteristic in parallel of iic bus, system
Communication stability is higher than train, communicates high efficient and reliable.
If wanting to change the address allocation rule of equipment, only with need to reusing a kind of multinode IIC according to new rule
Location dynamic allocation method is reallocated successively, rearranges sub- equipment without disassembly.The present invention can be pacified by certain rule
The address IIC of all sub- equipment is arranged, and the address IIC of sub- equipment can be changed by certain rule.Such as: a certain sub- equipment
The change of the address IIC, the address IIC exchange of certain two sub- equipment etc..
It is further used as preferred embodiment, includes in the sub- equipment or not comprising the address IIC.IIC address information
It need to be stored in erasable electronic device.
In addition, the embodiment of the invention also provides a kind of storage mediums, wherein being stored with the executable instruction of processor, institute
The executable instruction of processor is stated when executed by the processor for executing the dynamic allocation of the IC bus address
Method.
In some selectable embodiments, the function/operation mentioned in a block diagram can not be mentioned according to operational illustrations
The sequence arrived occurs.For example, depending on related function/operation, two boxes continuously shown can actually be by substantially
On simultaneously execute or the box can be performed sometimes with reverse order.In addition, presented in flow chart of the invention and
The embodiment of description is provided in an illustrative manner, and it is an object of the present invention to provide technology is more completely understood.Disclosed method is not
It is limited to operation presented herein and logic flow.Selectable embodiment is it is contemplated that the wherein sequence quilt of various operations
The sub-operation of a part for changing and being wherein described as larger operation is executed independently.
Although in addition, describing the present invention under the background of functional module and being illustrated in the form of block diagram
It is bright, but it is to be understood that, unless otherwise indicated, one or more of the function and/or feature can be collected
At in single physical device and/or software module or one or more functions and/or feature can be filled in individual physics
Set or software module in be implemented.It will also be appreciated that the practical realization in relation to each module is discussed in detail for understanding
The present invention is unnecessary.More specifically, it is contemplated that the attribute of various functional modules, function in device disclosed herein
In the case where internal relations, it will understand that the practical realization of the module in the routine techniques of engineer.Therefore, this field skill
Art personnel can realize this illustrated in detail in the claims hair with ordinary skill in the case where being not necessarily to undue experimentation
It is bright.It will also be appreciated that disclosed specific concept is merely illustrative, it is not intended to limit the scope of the present invention, this
The range of invention is determined by the full scope of the appended claims and its equivalent program.
It, can be with if the function is realized in the form of SFU software functional unit and when sold or used as an independent product
It is stored in a computer readable storage medium.Based on this understanding, technical solution of the present invention is substantially in other words
The part of the part that contributes to existing technology or the technical solution can be embodied in the form of software products, the meter
Calculation machine software product is stored in a storage medium, including some instructions are used so that a computer equipment (can be a
People's computer, server or network equipment etc.) it performs all or part of the steps of the method described in the various embodiments of the present invention.
And storage medium above-mentioned includes: that USB flash disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), arbitrary access are deposited
The various media that can store program code such as reservoir (RAM, Random Access Memory), magnetic or disk.
Expression or logic and/or step described otherwise above herein in flow charts, for example, being considered use
In the order list for the executable instruction for realizing logic function, may be embodied in any computer-readable medium, for
Instruction execution system, device or equipment (such as computer based system, including the system of processor or other can be held from instruction
The instruction fetch of row system, device or equipment and the system executed instruction) it uses, or combine these instruction execution systems, device or set
It is standby and use.For the purpose of this specification, " computer-readable medium ", which can be, any may include, stores, communicates, propagates or pass
Defeated program is for instruction execution system, device or equipment or the dress used in conjunction with these instruction execution systems, device or equipment
It sets.
The more specific example (non-exhaustive list) of storage medium include the following: there is being electrically connected for one or more wirings
Socket part (electronic device), portable computer diskette box (magnetic device), random access memory (RAM), read-only memory (ROM),
Erasable edit read-only storage (EPROM or flash memory), fiber device and portable optic disk read-only storage
(CDROM).In addition, storage medium can even is that the paper that can print described program on it or other suitable media, because
It can then be edited, be interpreted or when necessary with other appropriate parties for example by carrying out optical scanner to paper or other media
Formula is handled electronically to obtain described program, is then stored in computer storage.
It should be appreciated that each section of the invention can be realized with hardware, software, firmware or their combination.Above-mentioned
In embodiment, software that multiple steps or method can be executed in memory and by suitable instruction execution system with storage
Or firmware is realized.It, and in another embodiment, can be under well known in the art for example, if realized with hardware
Any one of column technology or their combination are realized: having a logic gates for realizing logic function to data-signal
Discrete logic, with suitable combinational logic gate circuit specific integrated circuit, programmable gate array (PGA), scene
Programmable gate array (FPGA) etc..
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not
Centainly refer to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be any
One or more embodiment or examples in can be combined in any suitable manner.
In conclusion dynamic allocation method, system and the storage medium of IC bus address of the present invention are with following
Advantage:
1, sub- equipment is not disassembled, and that realizes the address sub- equipment IIC rearranges distribution；
2, dismantling rearranges connexon equipment, and the sequence of IIC address arrangement is constant；
3, using this method, the address for overcoming IIC agreement dynamically distributes problem, improves the stability of system；
4, using this method, the design of sub- equipment can height unification, system can high modularization, communication it is efficient；
5, the address IIC can be dynamically distributed for the more device systems of dry chain-branched structure of multinode.
It is to be illustrated to preferable implementation of the invention, but the present invention is not limited to the embodiment above, it is ripe
Various equivalent deformation or replacement can also be made on the premise of without prejudice to spirit of the invention by knowing those skilled in the art, this
Equivalent deformation or replacement are all included in the scope defined by the claims of the present application a bit.
Claims (10)
1. the dynamic allocation method of IC bus address, it is characterised in that: the following steps are included:
Based on address allocation rule, address distribution instruction is sent to the first slave by host；
Address distribution instruction is successively sent to the second slave by the first slave；
The first number of addresses information is successively fed back into the host by the second slave；
According to the first number of addresses information, IC bus is opened by host；
Wherein, second slave is the least significant end slave in IC bus.
2. the dynamic allocation method of IC bus address according to claim 1, it is characterised in that: further include following
Step:
Judge with the presence or absence of branch in IC bus, if so, being divided address by the corresponding node module of the branch
The all devices being successively sent to instruction on branch, and perform the next step rapid；Conversely, being then not processed；
Through the most end end equipment on the branch after receiving address distribution instruction, the second number of addresses information is successively fed back
To the node module；
The the second number of addresses information received and address distribution instruction are sent to next node by the node module.
3. the dynamic allocation method of IC bus address according to claim 1, it is characterised in that:
Communications protocol between the host and slave or between slave and slave include but is not limited to USART agreement and/or
SPI protocol；
The slave is equipped at least two communication interfaces.
4. the dynamic allocation method of IC bus address according to claim 1, it is characterised in that: the address point
Include: with rule
The ascending order descending rule arranged by number of addresses size；
The functional rule arranged by preset function relationship；
The mapping ruler arranged by default mapping relations.
5. the dynamic allocation method of IC bus address according to claim 1, it is characterised in that: the slave root
According to the address distribution instruction received, information is received to host feedback command.
6. the dynamic allocation method of IC bus address according to claim 1, it is characterised in that: the address point
It include but is not limited to address information, address allocation rule information, address generating function and the cryptographic means of sender with instruction.
7. the dynamic allocation method of IC bus address according to claim 1, it is characterised in that: on the host
Store the maximum device number of IC bus.
8. the dynamic allocation system of IC bus address, it is characterised in that: include: host and several slaves；
Wherein, the host sends address distribution instruction to the first slave for being based on address allocation rule；And according to
One number of addresses information opens IC bus；
First slave, for address distribution instruction to be successively sent to the second slave；
Second slave, for the first number of addresses information successively to be fed back to the host；
Second slave is the least significant end slave in IC bus.
9. the dynamic allocation system of IC bus address, it is characterised in that: include:
At least one processor；
At least one processor, for storing at least one program；
When at least one described program is executed by least one described processor, so that at least one described processor is realized as weighed
Benefit requires the dynamic allocation method of IC bus address described in any one of 1-7.
10. a kind of storage medium, wherein being stored with the executable instruction of processor, it is characterised in that: the processor is executable
Instruction when executed by the processor for executes as IC bus address of any of claims 1-7 move
State distribution method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910448825.2A CN110290227B (en) | 2019-05-28 | 2019-05-28 | Dynamic distribution method, system and storage medium for integrated circuit bus address |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910448825.2A CN110290227B (en) | 2019-05-28 | 2019-05-28 | Dynamic distribution method, system and storage medium for integrated circuit bus address |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110290227A true CN110290227A (en) | 2019-09-27 |
| CN110290227B CN110290227B (en) | 2022-07-29 |
Family
ID=68002498
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910448825.2A Active CN110290227B (en) | 2019-05-28 | 2019-05-28 | Dynamic distribution method, system and storage medium for integrated circuit bus address |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110290227B (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111211955A (en) * | 2019-11-15 | 2020-05-29 | 华为技术有限公司 | Method for distributing slave node address and node management system |
| CN112422704A (en) * | 2020-09-27 | 2021-02-26 | 量道(深圳)储能科技有限公司 | Address allocation method and device for multiple devices and storage medium |
| CN112799990A (en) * | 2021-01-04 | 2021-05-14 | 中车株洲电力机车研究所有限公司 | Parallel bus data space management method, master device and system |
| CN112905508A (en) * | 2021-02-01 | 2021-06-04 | 浙江中拓合控科技有限公司 | Address allocation method, communication device and storage medium for serial communication equipment |
| CN112948299A (en) * | 2021-02-01 | 2021-06-11 | 浙江中拓合控科技有限公司 | Serial port communication system and communication method |
| CN113949692A (en) * | 2021-09-27 | 2022-01-18 | 北京三快在线科技有限公司 | Address allocation method and device, electronic equipment and computer readable storage medium |
| CN115396256A (en) * | 2022-09-14 | 2022-11-25 | 江苏安科瑞电器制造有限公司 | RS 485-based networking mode for rapidly acquiring data |
| CN116955265A (en) * | 2023-09-20 | 2023-10-27 | 合肥创发微电子有限公司 | I2C bus system communication method, device, equipment and medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102012885A (en) * | 2010-09-15 | 2011-04-13 | 开源集成电路(苏州)有限公司 | System and method for realizing communication by adopting dynamic I2C bus |
| CN102957761A (en) * | 2012-11-01 | 2013-03-06 | 奇点新源国际技术开发(北京)有限公司 | Communication network connecting device, communication address allocation method and bus access device |
| CN107133188A (en) * | 2017-04-24 | 2017-09-05 | 京信通信技术(广州)有限公司 | The master-slave communication of daisy chain connection distributes address approach, system and slave, main frame |
| CN108616610A (en) * | 2018-05-21 | 2018-10-02 | 深圳前海有电物联科技有限公司 | Address distribution method, host, slave and bus system |
| CN109656849A (en) * | 2018-12-25 | 2019-04-19 | 深圳市慎勇科技有限公司 | A kind of bus address distribution system and communication means based on cascade father node gating |
-
2019
- 2019-05-28 CN CN201910448825.2A patent/CN110290227B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102012885A (en) * | 2010-09-15 | 2011-04-13 | 开源集成电路(苏州)有限公司 | System and method for realizing communication by adopting dynamic I2C bus |
| CN102957761A (en) * | 2012-11-01 | 2013-03-06 | 奇点新源国际技术开发(北京)有限公司 | Communication network connecting device, communication address allocation method and bus access device |
| CN107133188A (en) * | 2017-04-24 | 2017-09-05 | 京信通信技术(广州)有限公司 | The master-slave communication of daisy chain connection distributes address approach, system and slave, main frame |
| CN108616610A (en) * | 2018-05-21 | 2018-10-02 | 深圳前海有电物联科技有限公司 | Address distribution method, host, slave and bus system |
| CN109656849A (en) * | 2018-12-25 | 2019-04-19 | 深圳市慎勇科技有限公司 | A kind of bus address distribution system and communication means based on cascade father node gating |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111211955A (en) * | 2019-11-15 | 2020-05-29 | 华为技术有限公司 | Method for distributing slave node address and node management system |
| CN111211955B (en) * | 2019-11-15 | 2022-03-29 | 华为技术有限公司 | Method for distributing slave node address and node management system |
| CN112422704B (en) * | 2020-09-27 | 2023-04-18 | 量道(深圳)储能科技有限公司 | Address allocation method and device for multiple devices and storage medium |
| CN112422704A (en) * | 2020-09-27 | 2021-02-26 | 量道(深圳)储能科技有限公司 | Address allocation method and device for multiple devices and storage medium |
| CN112799990A (en) * | 2021-01-04 | 2021-05-14 | 中车株洲电力机车研究所有限公司 | Parallel bus data space management method, master device and system |
| CN112799990B (en) * | 2021-01-04 | 2022-05-20 | 中车株洲电力机车研究所有限公司 | Parallel bus data space management method, master device and system |
| CN112905508A (en) * | 2021-02-01 | 2021-06-04 | 浙江中拓合控科技有限公司 | Address allocation method, communication device and storage medium for serial communication equipment |
| CN112948299A (en) * | 2021-02-01 | 2021-06-11 | 浙江中拓合控科技有限公司 | Serial port communication system and communication method |
| CN112905508B (en) * | 2021-02-01 | 2021-08-20 | 浙江中拓合控科技有限公司 | Address allocation method, communication device and storage medium for serial communication equipment |
| CN113949692A (en) * | 2021-09-27 | 2022-01-18 | 北京三快在线科技有限公司 | Address allocation method and device, electronic equipment and computer readable storage medium |
| CN115396256A (en) * | 2022-09-14 | 2022-11-25 | 江苏安科瑞电器制造有限公司 | RS 485-based networking mode for rapidly acquiring data |
| CN116955265A (en) * | 2023-09-20 | 2023-10-27 | 合肥创发微电子有限公司 | I2C bus system communication method, device, equipment and medium |
| CN116955265B (en) * | 2023-09-20 | 2023-12-05 | 合肥创发微电子有限公司 | I2C bus system communication method, device, equipment and medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110290227B (en) | 2022-07-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110290227A (en) | Dynamic allocation method, system and the storage medium of IC bus address | |
| US8037328B2 (en) | Protocol and interface between a LAN on motherboard (LOM) and a powered device (PD) for a personal computing device (PCD) | |
| CN102160341B (en) | Unified multi-transport medium connector architecture | |
| CN102486741B (en) | Serial ports sharing system and method | |
| CN101819556B (en) | Signal-processing board | |
| CN104348673B (en) | A kind of method of commissioning, master control borad and business board | |
| CN102347904B (en) | Router equipment, main card thereof and method for adapting main card to interface card | |
| CN207264377U (en) | Programmable I2C multiple selector and interchanger | |
| CN102281254A (en) | Design system and method of server serial port | |
| CN110321313A (en) | Configurable interface card | |
| CN105487999B (en) | The extensive usb expansion device of tandem type and working method, system | |
| CN105425918A (en) | Miniature server system | |
| CN103795517A (en) | Scalable multifunction serial link interface | |
| CN103514119A (en) | Method, device and application for presenting multifunctional devices to mainframe in USB compound device form | |
| CN106528469A (en) | Mainboard | |
| CN110362511A (en) | A kind of PCIE device | |
| CN104050127A (en) | IIC topological structure and design method thereof | |
| CN204595794U (en) | USB computer switcher signal extender and extender system | |
| CN116401065A (en) | Server, heterogeneous equipment and data processing device thereof | |
| CN110287141A (en) | A kind of FPGA reconstructing method and system based on multiple interfaces | |
| CN109039955A (en) | A kind of storage system based on optical-fibre channel | |
| CN104516852B (en) | The circuit of I/O links divides multiplexing | |
| CN106685588A (en) | Adapter, data transmission system and method | |
| CN207882728U (en) | A kind of control system | |
| CN101334763B (en) | Data transfer method between mainframe and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |