CN108616610A - Address distribution method, host, slave and bus system - Google Patents
Address distribution method, host, slave and bus system Download PDFInfo
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- CN108616610A CN108616610A CN201810214002.9A CN201810214002A CN108616610A CN 108616610 A CN108616610 A CN 108616610A CN 201810214002 A CN201810214002 A CN 201810214002A CN 108616610 A CN108616610 A CN 108616610A
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- slave
- host
- address
- enabled pin
- slaves
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L61/00—Network arrangements, protocols or services for addressing or naming
- H04L61/50—Address allocation
- H04L61/5038—Address allocation for local use, e.g. in LAN or USB networks, or in a controller area network [CAN]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
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- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Small-Scale Networks (AREA)
Abstract
The present invention relates to a kind of bus systems, the bus system includes host and multiple slaves, and the host is connect with the multiple slave by bus communication, and each slave is communicated to connect with adjacent slave, each slave includes enabled pin, wherein the address distribution to slave includes：Draw high the enabled pin of one of slave, host sends the address distribution instruction for the slave being raised, the slave being raised distributes instruction setting Self address according to the address, and after the slave addresses being raised are provided with, the enabled pin of the slave being raised is pulled low.The present invention also provides a kind of address distribution method, host, slaves.The bus system can distribute slave addresses automatically, and address is distributed into power height.
Description
Technical field
The present invention relates to slave addresses distribution technique more particularly to a kind of address distribution method, host, slave and total linear systems
System.
Background technology
Universal serial bus is widely used in industrial control field.When using universal serial bus, all devices in bus are shared
Communication media, the communication information that any one equipment is sent out can be received by the miscellaneous equipment in bus.It is sent to indicate
Or the equipment for receiving information, it is necessary to distribute a mailing address for each equipment.
Currently, in the serial bus system under using master-slave communication pattern, manual setting device address is usually used.
The setting of usual address is all that artificially manual setting toggle switch distributes device address on slave in advance, is then recorded
The address number of distribution, then the allocated from the address of equipment, just foundation communication in this way is inputted to host.In commercial Application,
Such as in central air conditioner system, many slaves can be connected below usual host, and the position of slave is all not fixed and distance
Far, manual setting device address is likely to the address that setting repeats.And many hosts are all to belong to closing host, only
Opening machine casing could be simply arranged, if after user repairs slave or newly increases slave devices, often
Bring some chance failures.
Prior art slave needs to manually enter the address of each slave setting, it is therefore desirable to which an input unit is dialled
Code input switch.According to the electrical characteristic of bus, device address does not allow to repeat, and the device address in bus is unique.So
And during setting by hand, if two slaves, such as the address of slave 1 and slave 3 are both configured to for example accidentally
0x01, then according to bus characteristics, if host is sent to the order for the slave that address is 0x01, slave 1 and slave 3 can
It receives, and all can thus cause there are two slaves sending message simultaneously in synchronization in a network to host response, this
The communication failure of all terminals will be caused, that is, bus collision has occurred, so that whole system cannot work.
Invention content
In consideration of it, it is necessary to provide a kind of address distribution method, host, slave and bus systems.
A kind of address distribution method is applied to host, and the host is communicated to connect by bus and multiple slaves, Mei Yicong
Machine includes enabled pin, the method includes：
A. the enabled pin of No. 1 slave is drawn high；
B. the address distribution instruction of N slaves, N=1 are sent；
C. the enabled pin of No. 1 slave is dragged down after receiving the reply of No. 1 slave or the scheduled duration that is delayed；
D. it is delayed after scheduled duration, N=N+1；
E. the address distribution instruction of N slaves is sent；
Step d and e are repeated, the address distribution until completing all slaves.
In some embodiments, the enabled pin of the slave include the first enabled pin and the second enabled pin, first
Enabled pin is drawn high or is dragged down by the host or a upper slave for receiving control signal；Second enabled pin is for sending
Signal is controlled, the enabled pin of next slave is dragged down.
In some embodiments, when detecting that new slave is added, the corresponding address distribution instruction for newly increasing slave is sent.
A kind of host, the host are communicated to connect by bus and multiple slaves, which is characterized in that the host includes master
Machine controller, mainframe memory, host communication module, the host controller respectively with the mainframe memory and the host
Communication module communicates to connect, wherein the host controller controls the host communication module and sends and receives letter by bus
Breath, the mainframe memory are used to store quantity and the address of slave, and the host controller controls the host and executes institute
The address distribution method applied to host stated.
A kind of address distribution method is applied to slave, and the slave is connect by bus with main-machine communication, the slave packet
Enabled pin is included, the number of the slave is N, and N is natural number, the method includes：
When itself the first enabled pin is raised, the address distribution that the host is sent is received by bus and is instructed, and according to
Described address distribution instruction setting Self address；
It sends characterization address and successful information is set to the host.
In some embodiments, the method further includes：
When itself enabling pin and being pulled low, judge whether N is slave total quantity, if it is not, then drawing high the enabled of N+1 slaves
Pin；
Receive host transmission N+1 slaves address distribution instruction after, be delayed a scheduled duration after drag down described No. N+1 from
The enabled pin of machine.
In some embodiments, the method includes：
When thering is new slave to access the slave, and receiving the address distribution instruction of N+1 slaves of host transmission, N+ is drawn high
The enabled pin of No. 1 slave；
After the scheduled duration that is delayed, the enabled pin of the N+1 slaves is dragged down.
A kind of slave, the slave are communicated to connect by bus and host slave, the slave include from machine controller, from
Machine memory, slave communication module are described logical with the slave memory and the slave communication module respectively from machine controller
Letter connection, wherein described to be sent and received information from the machine controller control slave communication module by bus, the slave
Memory is used to store quantity and the address of slave, and described controlled from machine controller is applied to slave described in the slave execution above
Method.
A kind of bus system, the bus system include host and multiple slaves, and the host is logical with the multiple slave
Bus communication connection is crossed, each slave is communicated to connect with adjacent slave, and each slave includes enabled pin, wherein to the ground of slave
Location is distributed：The enabled pin of one of slave is drawn high, host sends the address distribution instruction for being raised slave, the quilt
It draws high slave and distributes instruction setting Self address according to the address, be raised after slave addresses are provided with described, the quilt
The enabled pin for drawing high slave is pulled low.
In some embodiments, when there is new slave to access the bus system, the host sends correspondence and newly increases
The address distribution instruction of slave, the adjacent slave of slave is newly increased in the address for newly increasing slave for receiving host transmission with this
When distribution instruction, after drawing high the enabled pin for newly increasing slave, and delay scheduled duration, drags down and described newly increase slave
Enabled pin.
A kind of electronic device, including memory, processor and be stored on the memory and can be on the processor
The slave addresses distribution program of operation realizes side as described above when the slave addresses distribution program is executed by the processor
The step of method.
A kind of computer readable storage medium, is stored thereon with computer program, and the computer program is held by processor
The step of method as described above is realized when row.
Described address distribution method, host, slave and bus system can distribute slave addresses automatically, and address is allocated successfully
Rate is high, and is not required to setting initialisation switch, and control is simple, at low cost.
Description of the drawings
Fig. 1 is the Organization Chart of the bus system of one embodiment of the invention.
Fig. 2 is the slave connection diagram of one embodiment of the invention.
Fig. 3 is the flow chart of the address distribution method applied to host of one embodiment of the invention.
Fig. 4 is the flow chart of the address distribution method applied to slave of one embodiment of the invention.
Fig. 5 is the flow chart of the address distribution method applied to slave of another embodiment of the present invention.
Following specific implementation mode will be further illustrated the present invention in conjunction with above-mentioned attached drawing.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
It should be noted that term " and or " used herein includes appointing for one or more relevant Listed Items
Meaning and all combinations.
To better understand the objects, features and advantages of the present invention, below in conjunction with the accompanying drawings and specific real
Applying example, the present invention will be described in detail.It should be noted that in the absence of conflict, embodiments herein and embodiment
In feature can be combined with each other.
Elaborate many details in the following description to facilitate a thorough understanding of the present invention, described embodiment only
It is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill
The every other embodiment that personnel are obtained without making creative work, shall fall within the protection scope of the present invention.
Unless otherwise defined, all of technologies and scientific terms used here by the article and belong to the technical field of the present invention
The normally understood meaning of technical staff is identical.Used term is intended merely to description tool in the description of the invention herein
The purpose of the embodiment of body, it is not intended that in the limitation present invention.
This exposure discloses a kind of bus system, and the bus system includes host and multiple slaves, the host with it is described
Multiple slaves are connected by bus communication, and each slave is communicated to connect with adjacent slave, and each slave includes enabled pin, wherein
The address of slave is distributed and includes：The enabled pin of one of slave is drawn high, host sends the address distribution for being raised slave
Instruction, the slave that is raised distribute instruction setting Self address according to the address, are set up in the slave addresses that are raised
Cheng Hou, the enabled pin for being raised slave are pulled low.
Wherein described address distribution instructs the number of the slave of the total quantity, address to be allocated that include, but are not limited to slave
And address.
The bus system can be the serial bus system of any suitable, for example, universal asynchronous receiving-transmitting transmitter
（Universal Asynchronous Receiver/Transmitter, UART）, proposed standard 232（Recommend
Standard 232, RS232）, RS485, RS422, Controller Area Network BUS（Controller Area Network,
CAN）, universal serial bus（Universal Serial Bus, USB）Deng.
Specifically, host is to the address allocation procedure of adjacent slave：Draw high the enabled pin of adjacent slave；It sends adjacent
The address distribution instruction of slave；Making for the adjacent slave is dragged down after receiving the reply of the adjacent slave or the scheduled duration that is delayed
It can pin.
The address of the non-slave adjacent with host is distributed and includes：N（N is natural number, and is not the total quantity of slave）Number
Slave draws high the enabled pin of N+1 slaves, host sends the N+1 slaves when detecting that itself enabled pin is pulled low
Address distribution instruction, N slaves receive the N+1 slaves address distribution instruction after delay scheduled duration after drag down N+
The enabled pin of No. 1 slave.
Wherein, the enabled pin of the slave includes the first enabled pin and the second enabled pin, and the first enabled pin is used
Signal is controlled in receiving, the second enabled pin is for sending control signal.That is, the first enabled pin be by host or on
What one slave dragged down, and the second enabled pin is used to drag down the enabled pin of next slave.
In some embodiments, when there is new slave to access the bus system, the host sends correspondence and newly increases
The address distribution instruction of slave, the adjacent slave of slave is newly increased in the address for newly increasing slave for receiving host transmission with this
When distribution instruction, after drawing high the enabled pin for newly increasing slave, and delay scheduled duration, drags down and described newly increase slave
Enabled pin.
This exposure also discloses a kind of address distribution method, is applied to host, and the host is logical by bus and multiple slaves
Letter connection, each slave include enabled pin, the method includes：
A. the enabled pin of No. 1 slave is drawn high；
B. the address distribution instruction of N slaves, N=1 are sent；
C. the enabled pin of No. 1 slave is dragged down after receiving the reply of No. 1 slave or the scheduled duration that is delayed；
D. it is delayed after scheduled duration, N=N+1；
E. the address distribution instruction of N slaves is sent；
Step d and e are repeated, the address distribution until completing all slaves.
In some embodiments, when detecting that new slave is added, the corresponding address distribution instruction for newly increasing slave is sent.
A kind of host, the host are communicated to connect by bus and multiple slaves, which is characterized in that the host includes master
Machine controller, mainframe memory, host communication module, the host controller respectively with the mainframe memory and the host
Communication module communicates to connect, wherein the host controller controls the host communication module and sends and receives letter by bus
Breath, the mainframe memory are used to store quantity and the address of slave, and the host controller controls the host and executes institute
The address distribution method applied to host stated.
A kind of address distribution method is applied to slave, and the slave is connect by bus with main-machine communication, the slave packet
Enabled pin is included, the number of the slave is N, and N is natural number, the method includes：
When itself the first enabled pin is raised, the address distribution that the host is sent is received by bus and is instructed, and according to
Described address distribution instruction setting Self address；
It sends characterization address and successful information is set to the host.
In some embodiments, the method further includes：
When itself enabling pin and being pulled low, judge whether N is slave total quantity, if it is not, then drawing high the enabled of N+1 slaves
Pin；
Receive host transmission N+1 slaves address distribution instruction after, be delayed a scheduled duration after drag down described No. N+1 from
The enabled pin of machine.
In some embodiments, the method includes：
When thering is new slave to access the slave, and receiving the address distribution instruction of N+1 slaves of host transmission, N+ is drawn high
The enabled pin of No. 1 slave；
After the scheduled duration that is delayed, the enabled pin of the N+1 slaves is dragged down.
A kind of slave, the slave are communicated to connect by bus and host slave, the slave include from machine controller, from
Machine memory, slave communication module are described logical with the slave memory and the slave communication module respectively from machine controller
Letter connection, wherein described to be sent and received information from the machine controller control slave communication module by bus, the slave
Memory is used to store quantity and the address of slave, and described controlled from machine controller is applied to slave described in the slave execution above
Address distribution method.
This exposure address distribution method, host, slave and the bus system can distribute slave addresses, address automatically
It is distributed into power height, and is not required to setting initialisation switch, control is simple, at low cost.
Fig. 1 is the system architecture diagram of bus system 1 provided in an embodiment of the present invention.The bus system 1 includes, but unlimited
In host 10 and multiple slaves 20.The host 10 is connect with the slave 20 using master-slave communication pattern communication.
In some embodiments, the host 10, the slave 20 can be various intelligent or non intelligent electronic equipment,
Such as central air-conditioning, network access equipment etc..
In one embodiment, the host 10 includes host controller 100, mainframe memory 102 and host communication module
104.The host controller 100 is communicated to connect respectively at the mainframe memory 102 and the host communication module 104.
The host controller 100 is the control centre of host, utilizes various interfaces and the entire host of connection 10
Various pieces.The host controller 100 can be microprocessor（Micro Controller Unit, MCU）, central processing
Unit (Central Processing Unit, CPU), can also be other general processors, digital signal processor
(Digital Signal Processor, DSP), application-specific integrated circuit (Application Specific Integrated
Circuit, ASIC), ready-made programmable gate array (Field-Programmable Gate Array, FPGA) or other
Programmable logic device, discrete gate or transistor logic, discrete hardware components etc..
The mainframe memory 102 can be used for storing the computer program and/or module, the host controller 100
By running or execute the computer program being stored in the mainframe memory 102 and/or module, and calls and be stored in institute
The data in mainframe memory 102 are stated, realize the various functions of the host 10.The mainframe memory 102 can include mainly
Storing program area and storage data field, wherein storing program area can store the application program needed at least one function（Such as
Location is distributed）Deng；Storage data field can be stored uses created data according to the host 10（Such as the distribution address of slave
Deng）Deng.In addition, the mainframe memory 102 may include high-speed random access memory, can also include non-volatile memories
Device, such as hard disk, memory, plug-in type hard disk, intelligent memory card（Smart Media Card, SMC）, secure digital（Secure
Digital, SD）Card, flash card（Flash Card）, at least one disk memory, flush memory device or other volatibility
Solid-state memory.
The host communication module 104 is used under the control of the host controller 100 and 20 communication link of the slave
It connects.The host communication module 104 is communicatively coupled with the slave 20 using master slave mode.The host communication module
Communications protocol between 104 and the slave 20 includes but not limited to UART, RS232, RS485, RS422, CAN, USB etc..
In one embodiment, the slave 20 includes from machine controller 200, slave memory 202 and slave communication module
204.It is described to be communicated to connect from machine controller 200 respectively at the slave memory 202 and the slave communication module 204.
Described is the control centre of host from machine controller 200, utilizes various interfaces and the entire slave of connection 20
Various pieces.It is described from machine controller 200 can be microprocessor（Micro Controller Unit, MCU）, central processing
Unit (Central Processing Unit, CPU), can also be other general processors, digital signal processor
(Digital Signal Processor, DSP), application-specific integrated circuit (Application Specific Integrated
Circuit, ASIC), ready-made programmable gate array (Field-Programmable Gate Array, FPGA) or other
Programmable logic device, discrete gate or transistor logic, discrete hardware components etc..
The slave memory 202 can be used for storing the computer program and/or module, described from machine controller 200
By running or execute the computer program being stored in the slave memory 202 and/or module, and calls and be stored in institute
The data in slave memory 202 are stated, realize the various functions of the slave 20.The slave memory 202 can include mainly
Storing program area and storage data field, wherein storing program area can store the application program needed at least one function（Such as
Location is distributed）Deng；Storage data field can be stored uses created data according to the slave 20（Such as the distribution address of slave
Deng）Deng.In addition, the slave memory 202 may include high-speed random access memory, can also include non-volatile memories
Device, such as hard disk, memory, plug-in type hard disk, intelligent memory card（Smart Media Card, SMC）, secure digital（Secure
Digital, SD）Card, flash card（Flash Card）, at least one disk memory, flush memory device or other volatibility
Solid-state memory.
The slave communication module 204 be used for it is described under the control of machine controller 200 with 20 communication link of the slave
It connects.The slave communication module 204 is communicatively coupled with the slave 20 using master slave mode.The slave communication module
Communications protocol between 204 and the slave 20 includes but not limited to UART, RS232, RS485, RS422, CAN, USB etc..
For ease of description, illustrating the connection relation between host 10 and slave 20 by taking UART as an example as follows.Please refer to Fig. 2 institutes
Show, is the connection diagram of the host 10 and slave 20 of one embodiment of the invention.The host 10 and multiple slaves 20 successively phase
It connects.
The slave 10 includes host power supply terminal VCC, host ground terminal GND, and slave enables pin terminals SLAVE
EN and host information send terminal UART TX, host information receiving terminal UART RX.The wherein described slave enables pin terminals
SLAVE EN are for controlling（It drags down or draws high）The enabled pin of adjacent slave.The host information sends terminal UART TX and uses
In the address distribution instruction of transmission information, such as slave；The host information receiving terminal UART RX are for receiving information, example
Successful information is arranged from the characterization slave addresses of slave in Tathagata.
The slave 20 include two groups respectively with the host power supply terminal VCC slave power supply terminal VCC connecting and institute
State the slave ground terminal GND of host ground terminal GND connections, the first enabled pin EN1, the second enabled pin SLAVE EN,
The sub- UART TX of the two groups of slave information transmitting terminals and sub- UART RX of slave information receiving end.The wherein described first enabled pin EN1
It for the control of receiving host, is drawn high or is dragged down by the host or a upper slave, the second enabled pin SLAVE EN are for controlling
Next slave is made, the enabled pin of next slave is drawn high or drag down.The sub- UART TX of slave information transmitting terminal believe for sending
Successful information is arranged in breath, such as characterization address；The sub- UART RX of slave information receiving end are used to receive information, such as come
Instruction is distributed from the address of host.Two group information transmissions/receiving terminal of the slave, one of which by bus and host,
Other slaves connect, and another group connect with host or adjacent slave.
Fig. 3 is the schematic flow diagram of address distribution method provided in an embodiment of the present invention.Address distribution side as shown in Figure 3
Method may include following steps：
Step 31, host receives address distribution instruction.In one embodiment, described address distribution instruction is from logical with the host
Believe the host computer of connection.It is understood that in other embodiments, described address distribution instruction also may be from and the host
The remote terminal of communication connection.
Step 32, the host draws high the enabled pin of slave adjacent thereto.In some embodiments, adjacent with host
The number of slave be set as No. 1.
Step 33, the host sends the distribution instruction of the addresses N, wherein N=1.Described address distribution instruction includes that exchange is total
The address of quantity, the number of N slaves and N slaves.
Step 34, the host judges whether to receive the return information from slave, wherein the return information characterizes
The address of the N slaves is arranged successfully.If so, 36 are entered step, if it is not, then entering step 35.
Step 35, the first scheduled duration of the host delay, such as 100ms, it is to be understood that the described first pre- timing
Length can determine that the scheduled duration may be configured as being more than the reality according to the time needed for practical slave setting Self address
The number of any suitable of the time needed for Self address is arranged in slave.
Step 36, the host drags down the enabled pin of adjacent slave.
Step 37, be delayed the second scheduled duration, such as 100ms.It is predetermined that second scheduled duration can be equal to described first
Duration can also be differed with the first scheduled duration, can be set according to actual conditions.
Step 38, the host judges whether N is slave total quantity.That is, judging whether N slaves are last
Platform slave, if so, indicating that the address for completing all slave addresses is arranged, flow terminates, if it is not, then entering step 39.
Step 39, N=N+1 is set, that is, is opened to next slave（N+1）The address setting procedure of number slave.
Step 310, the distribution instruction of the addresses N is sent.
Step 37 is repeated later to step 310, it is known that the address of all slaves is respectively provided with completion.
In some embodiments, so slave addresses are distributed after being completed, if detecting, new slave access is described total
Linear system is united, then slave total quantity M is updated to M+1 by the host, and is referred to by the address distribution of bus transmission M+1 slaves
It enables.The upper slave for newly increasing slave is detecting new slave access and is receiving the address for newly increasing slave point
When with instruction, the enabled pin for newly increasing slave is drawn high, and drags down described newly increase after being delayed a third scheduled duration
The enabled pin of slave.The flow for newly increasing slave setting Self address is consistent with general slave, please join shown in Fig. 4.
Fig. 4 is a kind of schematic flow diagram of address distribution method applied to slave provided in an embodiment of the present invention.Fig. 4 institutes
The method stated is applied to slave, and the number of the slave is N, and wherein N waits natural numbers for 1,2,3 ....
Step 41, the slave judges whether itself enabled pin is raised.When itself enabled pin is raised,
42 are entered step, if it is not, then return to step 41.
Step 42, the slave is received to distribute from the address that the host is sent from the bus and be instructed, and according to this
Address distribution instruction setting Self address.Wherein described address distribution instruction includes that number, address and the slave of the slave are total
Quantity.
Step 43, the slave returns to the successful information of characterization address setting after Self address is provided with.At some
In embodiment, the characterization address is arranged successful information and is back to the host by bus, in other embodiments, described
Characterization address is arranged successful information and is back to the upper slave and/or host being connected with the slave by bus.
Step 44, the slave judges whether itself pin is pulled low, if so, 45 are entered step, if it is not, then returning to step
Rapid 44.
Step 45, the slave judges whether N is slave total quantity.That is, judging whether N slaves are last
Platform slave, if so, indicating that the address for completing all slave addresses is arranged, flow terminates, if it is not, then entering step 46.
Step 46, the slave draws high the enabled pin of N+1 slaves.
Step 47, the slave judges whether that the address distribution for receiving the N+1 slaves sent from the host refers to
It enables, if so, 48 are entered step, if it is not, then return to step 47.
Step 48, be delayed the 4th scheduled duration（Such as 100ms）, drag down the enabled pin of N+1 slaves.Described 4th is pre-
Timing length can be according to actual conditions（Such as the reaction speed etc. of network speed or host and slave processors）To be arranged to the number of any suitable
Word.
Fig. 5 is the schematic flow diagram of another address distribution method for being applied to slave provided in an embodiment of the present invention.Fig. 5
The method is applied to slave, and the number of the slave is N, and wherein N is the total quantity of slave.
Step 51, the slave judges whether there is new slave access, if so, 52 are entered step, if it is not, then returning to step
Rapid 51.
Step 52, the slave judges whether that the address distribution for receiving the N+1 slaves sent from the host refers to
It enables, if so, 53 are entered step, if it is not, then return to step 52.
Step 53, the slave draws high the enabled pin of N+1 slaves.
Step 54, be delayed the 5th scheduled duration（Such as 100ms）, drag down the enabled pin of N+1 slaves.Described 5th is pre-
Timing length can be according to actual conditions（Such as the reaction speed etc. of network speed or host and slave processors）To be arranged to the number of any suitable
Word.
Finally it should be noted that the above examples are only used to illustrate the technical scheme of the present invention and are not limiting, although reference
Preferred embodiment describes the invention in detail, it will be understood by those of ordinary skill in the art that, it can be to the present invention's
Technical solution is modified or equivalent replacement, without departing from the spirit of the technical scheme of the invention and range.
Claims (10)
1. a kind of address distribution method is applied to host, the host is communicated to connect by bus and multiple slaves, and feature exists
In, each slave includes enabled pin, the method includes：
A. the enabled pin of No. 1 slave is drawn high；
B. the address distribution instruction of N slaves, N=1 are sent；
C. the enabled pin of No. 1 slave is dragged down after receiving the reply of No. 1 slave or the scheduled duration that is delayed；
D. it is delayed after scheduled duration, N=N+1；
E. the address distribution instruction of N slaves is sent；
Step d and e are repeated, the address distribution until completing all slaves.
2. the method as described in claim 1, which is characterized in that the enabled pin of the slave includes the first enabled pin and the
Two enabled pins, the first enabled pin are drawn high or are dragged down by the host or a upper slave for receiving control signal；Second makes
Energy pin drags down the enabled pin of next slave for sending control signal.
3. the method as described in claim 1, which is characterized in that when detecting that new slave is added, send it is corresponding newly increase from
The address distribution instruction of machine.
4. a kind of host, the host is communicated to connect by bus and multiple slaves, which is characterized in that the host includes host
Controller, mainframe memory, host communication module, the host controller are logical with the mainframe memory and the host respectively
Interrogate module communication connection, wherein the host controller controls the host communication module and is sent and received information by bus,
The mainframe memory is used to store quantity and the address of slave, and the host controller controls the host perform claim requirement
1 to 3 any one of them method.
5. a kind of address distribution method, is applied to slave, the slave is connect by bus with main-machine communication, which is characterized in that
The slave includes enabled pin, and the number of the slave is N, and N is natural number, the method includes：
When itself the first enabled pin is raised, the address distribution that the host is sent is received by bus and is instructed, and according to
Described address distribution instruction setting Self address；
It sends characterization address and successful information is set to the host.
6. method as claimed in claim 5, which is characterized in that the method further includes：
When itself enabling pin and being pulled low, judge whether N is slave total quantity, if it is not, then drawing high the enabled of N+1 slaves
Pin；
Receive host transmission N+1 slaves address distribution instruction after, be delayed a scheduled duration after drag down described No. N+1 from
The enabled pin of machine.
7. the method as described in claim 1, which is characterized in that the method includes：
When thering is new slave to access the slave, and receiving the address distribution instruction of N+1 slaves of host transmission, N+ is drawn high
The enabled pin of No. 1 slave；
After the scheduled duration that is delayed, the enabled pin of the N+1 slaves is dragged down.
8. a kind of slave, the slave is communicated to connect by bus and host slave, which is characterized in that the slave includes slave
Controller, slave memory, slave communication module are described logical with the slave memory and the slave respectively from machine controller
Interrogate module communication connection, wherein it is described to be sent and received information from the machine controller control slave communication module by bus,
The slave memory is used to store quantity and the address of slave, described to control the slave perform claim requirement from machine controller
5 to 7 any one of them methods.
9. a kind of bus system, which is characterized in that the bus system includes host and multiple slaves, the host with it is described more
A slave is connected by bus communication, and each slave is communicated to connect with adjacent slave, and each slave includes enabled pin, wherein right
The address of slave is distributed：The enabled pin of one of slave is drawn high, host sends the address distribution for the slave being raised
Instruction, the slave being raised distribute instruction setting Self address according to the address, are set in the slave addresses being raised
After the completion of setting, the enabled pin for being raised slave is pulled low.
10. bus system as claimed in claim 9, which is characterized in that when there is new slave to access the bus system, institute
It states host and sends the corresponding address distribution instruction for newly increasing slave, newly increasing the adjacent slave of slave with this is receiving host hair
When the address distribution instruction for newly increasing slave sent, after drawing high the enabled pin for newly increasing slave, and delay scheduled duration,
Drag down the enabled pin for newly increasing slave.
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