CN110289840B - Clock switching circuit and clock switching method for clock switching circuit - Google Patents

Clock switching circuit and clock switching method for clock switching circuit Download PDF

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CN110289840B
CN110289840B CN201910567423.4A CN201910567423A CN110289840B CN 110289840 B CN110289840 B CN 110289840B CN 201910567423 A CN201910567423 A CN 201910567423A CN 110289840 B CN110289840 B CN 110289840B
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clock
unit
signal
state
turn
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CN110289840A (en
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闻军会
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Beijing Baidu Netcom Science and Technology Co Ltd
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Beijing Baidu Netcom Science and Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/002—Switching arrangements with several input- or output terminals
    • H03K17/005—Switching arrangements with several input- or output terminals with several inputs only
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Electronic Switches (AREA)

Abstract

The embodiment of the application discloses a clock switching circuit and a clock switching method for the same. One embodiment of the clock switching circuit comprises: the clock switching circuit comprises a state control unit, a decoding unit, a clock turn-off unit and a clock updating unit; the state control unit is used for switching the current state to a clock off state if a clock switching request is received, and sending notification information for updating the clock to the clock updating unit if the input multi-channel clock is determined to be off; the decoding unit is used for outputting a clock turn-off signal to the clock turn-off unit if the current state of the state control unit is detected to be a clock turn-off state; the clock turn-off unit is used for turning off the multi-channel clock if receiving a clock turn-off signal; and the clock updating unit is used for selecting and updating the clock indicated by the input clock selection signal from the multi-path clock if the notification information is received. This embodiment can avoid the occurrence of glitches during the clock update.

Description

Clock switching circuit and clock switching method for clock switching circuit
Technical Field
The embodiment of the application relates to the field of integrated circuits, in particular to a clock switching circuit and a clock switching method for the same.
Background
Clock switching is a problem often encountered in integrated circuit design. For example, when the system is powered on, the system firstly works on a crystal oscillator clock, and is switched to a Phase Locked Loop (PLL) clock after the PLL is stabilized. In addition, according to different working modes, sometimes an internal clock needs to be switched to an external associated clock; or to switch from one frequency to another. For synchronous clocks, direct switching is sufficient, but for asynchronous clocks, special care is needed in switching, and a glitch is generated on an output clock when the glitch is not properly processed, so that a system is broken down.
Disclosure of Invention
The embodiment of the application provides a clock switching circuit and a clock switching method for the clock switching circuit.
In a first aspect, an embodiment of the present application provides a clock switching circuit, where the clock switching circuit includes a state control unit, a decoding unit, a clock turn-off unit, and a clock update unit; the state control unit comprises a clock off state and is used for responding to a received clock switching request, switching the current state to the clock off state, responding to the fact that the input multi-channel clock is turned off, and sending notification information for updating the clock to the clock updating unit; the decoding unit is used for responding to the clock off state detected by the state control unit and outputting a clock off signal to the clock off unit; the clock turn-off unit is used for turning off the multi-path clock in response to receiving the clock turn-off signal; and the clock updating unit is used for selecting and updating the clock indicated by the input clock selection signal from the multiple clocks in response to the received notification information.
In some embodiments, the state control unit further includes an idle state, and the state control unit is further configured to switch the current state to the idle state in response to determining that the clock update unit completes the clock update; the decoding unit is also used for responding to the detection that the current state of the state control unit is an idle state and outputting a clock turn-on signal to the clock turn-off unit; the clock turn-off unit is also used for responding to the received clock turn-on signal and turning on the multipath clock; and the clock updating unit is also used for outputting the updated clock.
In some embodiments, the state control unit is further configured to determine that the multi-way clock is turned off in response to determining that the time length from the current time to the clock turn-off time is greater than a preset number of clock cycles of a target clock, where the target clock is a clock with a longest clock cycle in the multi-way clock.
In some embodiments, the state control unit further comprises a clock update state, and the state control unit is further configured to switch the current state to the clock update state in response to determining that the input multi-way clock has been gated off.
In some embodiments, the clock switching circuit further comprises an input detection unit; and an input detection unit for notifying the state control unit in response to determining that the clock switching request is received.
In some embodiments, the input detection unit is further configured to determine whether a clock switching request is received based on the input clock selection signal.
In some embodiments, the input detection unit includes a shift register and a comparator; the shift register is used for delaying the input clock selection signal to obtain a delayed clock selection signal; and the comparator is used for comparing the input clock selection signal with the delayed clock selection signal to obtain a comparison result, wherein the comparison result is used for indicating whether a clock switching request is received or not.
In some embodiments, the clock gating cell comprises a first flip-flop register, a second flip-flop register, and an and gate; the first trigger register is used for responding to the detection of the rising edge of each path of clock in the multi-path clock and outputting a clock turn-off signal or a clock turn-on signal to the second trigger register; the second trigger register is used for responding to the detection of the falling edge of each path of clock in the multi-path clock and outputting a clock turn-off signal or a clock turn-on signal to an AND gate; and the AND gate is used for AND-ing the clock turn-off signal or the clock turn-on signal with the path clock aiming at each path clock in the multipath clocks.
In some embodiments, the clock update unit includes a third flip-flop register and a data selector; and a third flip-flop register for outputting a clock selection signal to the data selector in response to receiving the notification information; and the data selector is used for selecting and outputting the clock indicated by the clock selection signal from the multi-path clock output by the clock gating unit.
In a second aspect, an embodiment of the present application provides a clock switching method for a clock switching circuit, including: in response to receiving a clock switching request, switching off a plurality of paths of clocks input to a clock switching circuit, wherein the clock switching request comprises a clock selection signal; determining whether the multi-path clock is turned off; in response to determining that the multi-way clock has been gated off, selecting and updating the clock indicated by the clock select signal from the multi-way clock; and outputting the updated clock.
In some embodiments, determining whether the multi-way clock has been gated off comprises: and determining that the multipath clock is turned off in response to the fact that the time length from the current moment to the clock turning-off moment is larger than the preset number of clock cycles of the target clock, wherein the target clock is the clock with the longest clock cycle in the multipath clock.
In some embodiments, before turning off the multiplexed clocks input to the clock switching circuit in response to receiving a clock switching request, the method further comprises: comparing the currently input clock selection signal with the clock selection signal of the previous period to obtain a comparison result, wherein the comparison result is used for indicating whether a clock switching request is received; based on the comparison result, it is determined whether a clock switching request is received.
The clock switching circuit provided by the embodiment of the application comprises a state control unit, a decoding unit, a clock turn-off unit and a clock updating unit, wherein: the state control unit is used for responding to a received clock switching request, switching the current state to a clock off state, responding to the fact that the input multi-channel clock is determined to be off, and sending notification information for updating the clock to the clock updating unit; the decoding unit is used for responding to the detection that the current state of the state control unit is a clock turn-off state and outputting a clock turn-off signal to the clock turn-off unit; the clock turn-off unit is used for turning off the multi-path clock in response to receiving the clock turn-off signal; and the clock updating unit is used for selecting and updating the clock indicated by the input clock selection signal from the multiple clocks in response to the received notification information. The clock switching circuit can avoid the occurrence of glitches in the clock updating process.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings:
FIG. 1 is a schematic block diagram illustrating one embodiment of a clock switching circuit according to the present application;
FIG. 2 is a schematic block diagram of yet another embodiment of a clock switching circuit according to the present application;
FIG. 3 is a schematic block diagram illustrating one embodiment of an input detection unit in a clock switching circuit according to the present application;
FIG. 4 is a schematic diagram illustrating an embodiment of a clock gating cell in a clock switching circuit according to the present application;
FIG. 5 is a schematic block diagram illustrating an embodiment of a clock update unit in a clock switching circuit according to the present application;
FIG. 6 is a timing diagram of an embodiment of a clock switching circuit according to the present application;
FIG. 7 is a flow diagram of one embodiment of a clock switching method for a clock switching circuit according to the present application.
Detailed Description
The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the related invention are shown in the drawings.
It should be noted that, in the present application, the embodiments and features of the embodiments may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Referring to fig. 1, a schematic diagram of an embodiment of a clock switching circuit according to the present application is shown. The clock switching circuit in the present embodiment may include a state control unit 1, a decoding unit 2, a clock gating-off unit 3, and a clock updating unit 4.
In this embodiment, the inputs of the clock switching circuit may be N clocks and nbit clock selection signal, wherein 2 n-1 ≤N≤2 n . The clock may also be referred to as a clock signal. The clock signal is the basis of sequential logic, which determines when the state in a logic cell is updated, and is a semaphore with a fixed period and which is independent of operation. The clock signal is generated by a clock generator. It has only two levels, one low and the other high. As an example, if the input clock is 16-way, the clock selection signal may be 4 bits.
In the present embodiment, the state control unit 1 described above may include a clock-off state. The state control unit 1 may determine whether a clock switching request is received, and if the clock switching request is received, the state control unit 1 may switch the current state to a clock off state. It should be noted that the clock switching request usually includes a clock selection signal.
The state control unit 1 may determine whether the input multi-channel clock is turned off, and may transmit notification information for updating the clock to the clock updating unit 4 if it is determined that the input multi-channel clock is turned off.
It should be noted that, while the state control unit 1 waits for a clock switching request, the state control unit 1 is normally in an idle state.
In this embodiment, after the state control unit 1 switches the current state, the current state may be sent to the decoding unit 2. The decoding unit 2 may detect whether the current state of the state control unit 1 is a clock off state, and may output a clock off signal to the clock off unit 3 if the current state of the state control unit 1 is detected to be the clock off state. If the clock input to the clock switching circuit is N-way, the clock off signal is usually Nbit. Here, the clock-off signal may be characterized as clk _ en =0.
In this embodiment, the clock gating unit 3 may determine whether the clock gating signal is received. If the clock off signal is received, the multi-path clock can be turned off.
In this embodiment, the clock updating unit 4 may determine whether notification information for updating the clock transmitted by the state control unit 1 is received. When the notification information is received, the clock indicated by the input clock selection signal may be selected from the multiplexed clocks and updated. Here, the clock updating unit 4 may select a clock corresponding to the input clock selection signal from among the input multiplexed clocks by using a predetermined correspondence relationship between the clock selection signal and the clock.
In summary, the clock switching circuit provided in the embodiment of the present application can avoid the occurrence of glitches in the process of switching multiple clocks.
Alternatively, the state control unit 1 described above may include an idle state. The state control unit 1 may determine whether the clock update unit 4 completes the clock update. If it is determined that the clock updating unit 4 completes the clock updating, the current state may be switched to the idle state. After the state switching is completed, the state control unit 1 may send the current state to the decoding unit 2, and the decoding unit 2 may detect whether the current state of the state control unit 1 is an idle state. If the current state of the state control unit 1 is detected to be an idle state, a clock turn-on signal may be output to the clock gating unit 3. If the clock input to the clock switching circuit is N-way, the clock-on signal is usually Nbit. Here, the above clock-on signal may be characterized as clk _ en =1. The clock gating-off unit 3 may determine whether the clock gating-on signal is received, and may gate on the multi-channel clock if the clock gating-on signal is received. At this time, the clock updating unit 4 may output the updated clock. In this way, glitches can be avoided during the switching of the multiple clocks.
Here, the state control unit 1 may switch from an idle state to a clock off state to cause the clock off unit 3 to turn off multiple clocks; after that, the state control unit 1 may switch from the clock-off state to the clock update state to make the clock update unit 4 complete the clock update.
Here, after the clock updating unit 4 completes the clock updating, the state control unit 1 may switch from the clock updating state to the idle state, so that the clock gating unit 3 turns on the multiple clocks, and at this time, the clock updating unit 4 may output the updated clock.
It should be noted that, when the state control unit 1 is in the clock update state, the clock gating-off unit 3 needs to keep each clock in the off state.
Alternatively, the state control unit 1 may determine whether the multi-way clock is turned off by: the state control unit 1 may determine whether a time length from a current time to a clock turn-off time is greater than a preset number of clock cycles of the target clock. The clock gating-off timing may be a timing at which the clock gating-off unit 3 gates off the multiplexed clock. The target clock may be a clock having a longest clock period among the plurality of clocks. Here, the preset number may be 3. If the state control unit 1 determines that the time length from the current time to the clock turn-off time is greater than the preset number of clock cycles of the target clock, it may be determined that the multi-channel clock is turned off. By the method, whether the clock is closed or not can be accurately determined, and burrs are further avoided in the clock switching process.
Optionally, the state control unit 1 may further include a clock update state, and the state control unit 1 may further determine whether the input multi-way clock is turned off. If the input multi-channel clock is determined to be switched off, the current state can be switched to a clock updating state.
Optionally, please refer to fig. 2, which shows a schematic structural diagram of another embodiment of the clock switching circuit provided in the present application. As shown in fig. 2, the clock switching circuit may further include an input detection unit 5. The above-described input detection unit 5 can determine whether a clock switching request is received. The state control unit 1 may be notified if a clock switching request is received.
Alternatively, the input detection unit 5 may receive an input clock selection signal, and then may determine whether a clock switching request is received based on the input clock selection signal. Specifically, the input detection unit 5 may determine whether the clock selection signal received at the current time is the same as the clock selection signal received in the previous period. If the clock switching request is the same as the clock switching request, the clock switching request is not received. If not, the clock switching request is received.
Optionally, please refer to fig. 3, which shows a schematic structural diagram of an embodiment of an input detection unit in a clock switching circuit provided in the present application. As shown in fig. 3, the input detection unit may include a shift register 31 and a comparator 32. The shift register 31 may delay the input clock selection signal to obtain a delayed clock selection signal. The comparator 32 may compare the input clock selection signal with the delayed clock selection signal output from the shift register 31 to obtain a comparison result. The comparison result may be used to indicate whether a clock switch request is received. If the comparison result is that the input clock selection signal is the same as the delayed clock selection signal, it indicates that the clock switching request is not received. And if the comparison result is that the input clock selection signal is different from the delayed clock selection signal, the clock switching request is received.
Optionally, please refer to fig. 4, which shows a schematic structural diagram of an embodiment of a clock gating unit in a clock switching circuit provided in the present application. As shown in fig. 4, the clock gating off unit may include a first flip-flop register 41, a second flip-flop register 42, and an and gate 43. Flip-flop registers are edge sensitive memory cells, and the data storage is synchronized by the rising or falling edge of a signal. The first flip-flop register 41 may determine, for each of the multiple clocks, whether a rising edge of the path clock is detected. If the rising edge of the clock is detected, the clock off signal or the clock on signal may be output to the second flip-flop register 42. Here, the clock-off signal may be characterized as clk _ en =0, and the clock-on signal may be characterized as clk _ en =1. The second flip-flop register 42 may determine, for each of the plurality of clocks, whether a falling edge of the way clock is detected. If the falling edge of the way clock is detected, the clock off signal or the clock on signal may be output to the and gate 43. The and gate 43 may and the clock off signal or the clock on signal with the way clock for each way clock of the multi-way clock. By using the trigger register triggered by the rising edge and the trigger register triggered by the falling edge, the completeness of the output clock period can be ensured, and the occurrence of burrs is prevented.
As an example, if the input is the clock off signal (clk _ en = 0), the and gate 43 and the way clock with the clock off signal, and at this time, the output is low (clk _ g = 0), indicating that the way clock is turned off. If the input is the clock-on signal (clk _ en = 1), the and gate 43 ands the way clock with the clock-on signal, and at this time, the output is the way clock, which indicates that the way clock is turned on.
In addition, when the decoding unit 2 outputs a clock off signal, the first flip-flop register 41 and the second flip-flop register 42 output clock off signals. If the decoding unit 2 outputs a clock-on signal, the first flip-flop register 41 and the second flip-flop register 42 output a clock-on signal.
Optionally, please refer to fig. 5, which shows a schematic structural diagram of an embodiment of a clock updating unit in a clock switching circuit provided in the present application. As shown in fig. 5, the clock update unit may include a third flip-flop register 51 and a data selector 52. The third flip-flop register 51 may determine whether notification information for updating the clock, which is transmitted by the state control unit, is received. Upon receiving the notification information, the clock selection signal may be output to the data selector 52. The data selector 52 may select and output a clock indicated by the clock selection signal from among the plurality of clocks output from the clock gating unit.
If the data selector 52 receives a low level (i.e., the clock is turned off at this time), the data selector 52 outputs a low level. If the multiplexer 52 receives the multiplexed clock (i.e., the clock is turned on), the multiplexer 52 outputs the updated clock.
With continued reference to FIG. 6, a timing diagram of an embodiment of a clock switching circuit according to the present application is shown.
As shown in fig. 6, in step 601, the state control unit switches the current state to the clock-off state in response to receiving a clock switching request.
Here, the state control unit may include a clock-off state. The state control unit may determine whether a clock switching request is received, and may switch a current state to a clock off state if the clock switching request is received. It should be noted that the clock switching request usually includes a clock selection signal.
In step 602, the state control unit sends the current state to the decoding unit.
Here, after the state control unit switches the current state to the clock-off state, the current state may be transmitted to the decoding unit.
In step 603, the decoding unit detects whether the current state of the state control unit is a clock-off state.
Here, the decoding unit may detect whether a current state of the state control unit is a clock-off state.
In step 604, the decoding unit outputs a clock off signal to the clock off unit in response to detecting that the current state of the state control unit is the clock off state.
Here, the decoding unit may output a clock off signal to the clock off unit when detecting that the current state of the state control unit is the clock off state. Note that, if the clock input to the clock switching circuit is N-way, the clock off signal is usually Nbit. Here, the clock-off signal may be characterized as clk _ en =0.
In step 605, the clock gating off unit gates off the multi-way clock in response to receiving the clock gating off signal.
Here, the clock gating unit may determine whether the clock gating signal is received. If the clock turn-off signal is received, the multi-path clock can be turned off.
In step 606, the state control unit determines whether the input multi-way clock has been turned off.
Here, the state control unit may determine whether the input multi-way clock has been turned off.
Alternatively, the state control unit may determine whether the multi-way clock is turned off by: the state control unit may determine whether a time length from a current time to a clock turn-off time is greater than a preset number of clock cycles of the target clock. The clock gating-off timing may be a timing at which the clock gating-off unit gates off the multiplexed clock. The target clock may be a clock having a longest clock period among the plurality of clocks. Here, the preset number may be 3. If the state control unit determines that the time length from the current time to the clock turn-off time is greater than the preset number of clock cycles of the target clock, it may be determined that the multi-path clock is turned off. By the method, whether the clock is closed or not can be accurately determined, and burrs are further avoided in the clock switching process.
In step 607, the state control unit transmits notification information for updating the clocks to the clock updating unit in response to determining that the input multi-way clock has been turned off.
Here, if the state control unit determines that the input multi-clock is turned off, notification information for updating the clock may be transmitted to the clock updating unit.
In step 608, the clock updating unit selects and updates the clock indicated by the input clock selection signal from among the multiple clocks in response to receiving the notification information.
Here, the clock updating unit may determine whether notification information for updating the clock transmitted by the state control unit is received. The clock updating unit may select and update a clock indicated by the input clock selection signal from the multiplexed clocks, upon receiving the notification information. Here, the clock updating unit may select a clock corresponding to the input clock selection signal from among the input multiplexed clocks by using a predetermined correspondence relationship between the clock selection signal and the clock.
In step 609, the state control unit switches the current state to the idle state in response to determining that the clock update unit completes the clock update.
Here, the state control unit may determine whether the clock update unit completes the clock update. If it is determined that the clock updating unit completes the clock updating, the current state may be switched to an idle state.
In step 610, the state control unit sends the current state to the decoding unit.
Here, the state control unit may transmit the current state to the decoding unit after the state switching is completed.
In step 611, the decoding unit detects that the current state of the state control unit is an idle state.
Here, the decoding unit may detect whether a current state of the state control unit is an idle state.
In step 612, the decoding unit outputs a clock-on signal to the clock gating unit in response to detecting that the current state of the state control unit is an idle state.
Here, if the decoding unit detects that the current state of the state control unit is an idle state, a clock on signal may be output to the clock gating unit. Note that, if the clock input to the clock switching circuit is N-way, the clock on signal is usually Nbit. Here, the above clock-on signal may be characterized as clk _ en =1.
In step 613, the clock gating off unit turns on the multi-way clock in response to receiving the clock on signal.
The clock gating unit may determine whether the clock gating signal is received, and may gate the multi-way clock on if the clock gating signal is received.
In step 614, the clock update unit outputs the updated clock.
Here, the clock updating unit may output the updated clock.
The present application also provides a clock switching method for a clock switching circuit, which can be used for the clock switching circuit in the above embodiments. As shown in fig. 7, a flowchart 700 of one embodiment of a clock switching method for a clock switching circuit is provided. The method may comprise the steps of:
step 701, determining whether a clock switching request is received.
In this embodiment, the clock switching circuit may determine whether a clock switching request is received. The clock switching request typically includes a clock select signal. If the clock switching request is received, step 702 may be executed.
In this embodiment, the inputs of the clock switching circuit may be N clocks and nbit clock selection signal, wherein 2 n-1 ≤N≤2 n . The clock may also be referred to as a clock signal. The clock signal is the basis of sequential logic, which determines when the state in a logic cell is updated, and is a semaphore with a fixed period and which is independent of operation. The clock signal is generated by a clock generator. It has only two levels, one low and the other high. As an example, if the input clock is 16-way, the clock selection signal may be 4 bits.
In step 702, in response to receiving the clock switching request, the multi-channel clock input to the clock switching circuit is turned off.
In this embodiment, if it is determined in step 701 that the clock switching request is received, the multi-clock input to the clock switching circuit may be turned off. Specifically, the clock switching circuit may generate a clock off signal if a clock switching request is received. Here, the clock-off signal may be characterized as clk _ en =0. Then, the clock gating signal may be and-ed with each of the input multiple clocks. At this time, since the clock off signal is clk _ en =0, the result obtained after performing the and operation is a low level signal, which represents that the multi-way clock is turned off.
At step 703, it is determined whether the multi-way clock has been gated off.
In this embodiment, the clock switching circuit may determine whether the input multi-way clock is turned off. If it is determined that the multi-way clock has been gated off, step 704 may be performed.
Step 704, in response to determining that the multi-way clock has been gated off, selects and updates the clock indicated by the clock select signal from the multi-way clock.
In this embodiment, if it is determined in step 703 that the multi-clock is turned off, the clock switching circuit may select and update the clock indicated by the clock selection signal from the multi-clock. The clock switching circuit may select a clock corresponding to the input clock selection signal from among the input multiple clocks by using a predetermined correspondence relationship between the clock selection signal and the clock.
Step 705, the updated clock is output.
In this embodiment, the clock switching circuit may determine whether the clock update is completed. The clock switching circuit may generate a clock on signal if it is determined that the clock update is complete. Here, the above clock-on signal may be characterized as clk _ en =1. Then, the clock-on signal may be anded with each of the input multiple clocks. At this time, since the clock off signal is clk _ en =1, the result obtained after performing the and operation is the updated clock. Then, the clock switching circuit may output the updated clock.
In some optional implementations of this embodiment, the clock switching circuit may determine whether the multi-way clock is turned off by: the clock switching circuit can determine whether the time length from the current time to the clock turn-off time is greater than the preset number of clock cycles of the target clock. The clock off timing may be a timing at which the clock switching circuit turns off the multiplexed clock. The target clock may be a clock having a longest clock period among the plurality of clocks. Here, the preset number may be 3. If the clock switching circuit determines that the time length from the current time to the clock turn-off time is longer than the preset number of clock cycles of the target clock, it can be determined that the multi-path clock is turned off.
In some optional implementations of this embodiment, the clock switching circuit may compare a currently input clock selection signal with a clock selection signal of a previous period to obtain a comparison result. The comparison result may be used to indicate whether a clock switch request is received. Thereafter, the clock switching circuit may determine whether a clock switching request is received based on the comparison result. Specifically, if the comparison result indicates that the currently input clock selection signal is the same as the clock selection signal of the previous cycle, it indicates that the clock switching request is not received. If the comparison result indicates that the currently input clock selection signal is different from the clock selection signal of the previous period, the clock switching request is received.
In the method provided by the above embodiment of the present application, the multiple clocks input to the clock switching circuit are turned off in response to receiving the clock switching request; then, determining whether the multi-path clock is turned off; if the multi-path clock is determined to be switched off, selecting the clock indicated by the clock selection signal from the multi-path clock and updating; and finally, outputting the updated clock. Therefore, the clock switching method is provided, and the occurrence of burrs can be avoided in the clock updating process.
The above description is only a preferred embodiment of the application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention according to the present application is not limited to the specific combination of the above-mentioned features, but also covers other embodiments where any combination of the above-mentioned features or their equivalents is made without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims (11)

1. A clock switching circuit comprises a state control unit, a decoding unit, a clock turn-off unit and a clock updating unit; and
the state control unit comprises a clock off state, and is used for responding to a received clock switching request, switching the current state to the clock off state, and responding to the fact that the input multi-channel clock is turned off, and sending notification information for updating the clock to the clock updating unit; the state control unit is further used for responding to the fact that the time length from the current time to the clock turn-off time is larger than the preset number of clock cycles of a target clock, and determining that the multi-path clock is turned off, wherein the target clock is the clock with the longest clock cycle in the multi-path clock;
the decoding unit is used for responding to the detection that the current state of the state control unit is a clock turn-off state and outputting a clock turn-off signal to the clock turn-off unit;
the clock turn-off unit is used for turning off the multi-path clock in response to receiving the clock turn-off signal;
and the clock updating unit is used for selecting and updating the clock indicated by the input clock selection signal from the multipath clock in response to receiving the notification information.
2. The clock switching circuit of claim 1, wherein the state control unit further comprises an idle state, the state control unit further to switch a current state to the idle state in response to determining that the clock update unit completes a clock update;
the decoding unit is further used for responding to the detection that the current state of the state control unit is an idle state and outputting a clock turn-on signal to the clock turn-off unit;
the clock turn-off unit is further used for turning on the multi-path clock in response to receiving the clock turn-on signal;
the clock updating unit is also used for outputting the updated clock.
3. The clock switching circuit of claim 1, wherein the state control unit further comprises a clock update state, the state control unit further operable to switch the current state to the clock update state in response to determining that the input multi-way clock has been gated off.
4. The clock switching circuit of claim 1, wherein the clock switching circuit further comprises an input detection unit; and
the input detection unit is configured to notify the state control unit in response to determining that a clock switching request is received.
5. The clock switching circuit of claim 4, wherein the input detection unit is further configured to determine whether a clock switching request is received based on an input clock selection signal.
6. The clock switching circuit of claim 5, wherein the input detection unit comprises a shift register and a comparator; and
the shift register is used for delaying an input clock selection signal to obtain a delayed clock selection signal;
the comparator is configured to compare the input clock selection signal with the delayed clock selection signal to obtain a comparison result, where the comparison result is used to indicate whether a clock switching request is received.
7. The clock switching circuit of claim 2, wherein the clock gating cell comprises a first flip-flop register, a second flip-flop register, and an AND gate; and
the first flip-flop register is configured to, for each of the multiple clocks, output the clock off signal or the clock on signal to the second flip-flop register in response to detecting a rising edge of the way clock;
the second flip-flop register is configured to, for each of the multiple clocks, output the clock turn-off signal or the clock turn-on signal to the and gate in response to detecting a falling edge of the way clock;
and the AND gate is used for AND-ing the clock turn-off signal or the clock turn-on signal with the path of clock aiming at each path of clock in the multi-path clock.
8. The clock switching circuit of claim 1, wherein the clock update unit comprises a third flip-flop register and a data selector; and
the third flip-flop register is configured to output the clock selection signal to the data selector in response to receiving the notification information;
and the data selector is used for selecting and outputting the clock indicated by the clock selection signal from the multi-path clocks output by the clock gating unit.
9. A clock switching method for a clock switching circuit as claimed in one of claims 1 to 8, comprising:
in response to receiving a clock switching request, switching off a plurality of clocks input to the clock switching circuit, wherein the clock switching request comprises a clock selection signal;
determining whether the multi-way clock has been gated off;
in response to determining that the multi-way clock has been gated off, selecting and updating the clock indicated by the clock selection signal from the multi-way clock;
and outputting the updated clock.
10. The method of claim 9, wherein said determining whether the multi-way clock has been gated off comprises:
and determining that the multi-path clock is turned off in response to the fact that the time length from the current moment to the clock turn-off moment is greater than the preset number of clock cycles of a target clock, wherein the target clock is the clock with the longest clock cycle in the multi-path clock.
11. The method of claim 9, wherein prior to said gating off the multiplexed clocks input to the clock switching circuit in response to receiving a clock switching request, the method further comprises:
comparing a currently input clock selection signal with a clock selection signal of a previous period to obtain a comparison result, wherein the comparison result is used for indicating whether a clock switching request is received or not;
based on the comparison result, it is determined whether a clock switching request is received.
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