CN100426182C - Realizing circuit of asynchronous clock signal switching and method thereof - Google Patents
Realizing circuit of asynchronous clock signal switching and method thereof Download PDFInfo
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- CN100426182C CN100426182C CNB2006101608560A CN200610160856A CN100426182C CN 100426182 C CN100426182 C CN 100426182C CN B2006101608560 A CNB2006101608560 A CN B2006101608560A CN 200610160856 A CN200610160856 A CN 200610160856A CN 100426182 C CN100426182 C CN 100426182C
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Abstract
The invention discloses asynchronous clock signal switching circuit and method. It includes the following steps: preliminarily setting state machine; closing the current asynchronous clock signal while the state machine changing; selecting target asynchronous clock signal; opening it as the current asynchronous clock signal and outputting. The invention can avoid burr signal caused by asynchronous clock signal switching, realize stable switching.
Description
Technical field
The present invention relates to a kind of hardware circuit design technology, realization circuit and method that particularly a kind of asynchronous clock signal switches.
Background technology
At present, along with chip integration, the increase of complexity and functional requirement, in a lot of digital circuitries, each functional module of chip internal or processor need frequency and phase place asynchronous clock signal all inequality, and can change mutually between the asynchronous clock signal of each functional module of these chip internals or processor.
When chip normally moves, the dynamic power consumption that the main power consumption of digital circuitry produces when deriving from the signal condition upset.The dynamic power consumption that produces when overturning because of signal condition in order to reduce digital circuitry, when functional module or processor are in free time or halted state, is the standby clock signal of lower frequency with the clock signal of functional module or processor from the work clock conversion of signals of upper frequency, and work clock signal and standby clock signal are asynchronous clock signals.
At present, the conversion between asynchronous clock signal can adopt selector switch to realize.Fig. 1 is the structural representation that MUX (MUX) realizes circuit, as shown in Figure 1, suppose that MUX is a two-way selector switch, what passage 1 was imported is fast clock signal, what passage 2 was imported is slow clock signal, selector switch is selected input channel under the control of clock selection signal, and clock signal is the clock signal on the selected input channel.Such as when clock selection signal is 1, selected passage 1 is an input channel, and clock signal is the fast clock signal on the passage 1, and when the clock selection signal of MUX was 0, selected passage 2 was an input channel, and clock signal is the slow clock signal on the passage 2.Herein, signal is that 1 expression signal is a logic high, and signal is that 0 expression signal is a logic low.
Fig. 2 is the view that the clock signal of MUX switches under actual conditions, as shown in Figure 2, abscissa axis is a time shaft, axis of ordinates is an amplitude axis, oscillogram in each coordinate is represented the clock signal 203 of fast clock signal 201, slow clock signal 202, MUX, the clock selection signal 204 of MUX respectively from top to bottom, wherein, have burr signal 205 on the clock signal 203 of MUX, fast clock signal 201 and slow clock signal 202 are asynchronous clock signals.In conjunction with Fig. 1, the original state of the clock selection signal 204 of MUX is to be 0, and at this moment, the clock signal 203 of MUX is a slow clock signal 202; At t1 constantly, saltus step is 1 on the clock selection signal 204 of MUX, at this moment the clock signal 203 of MUX becomes fast clock signal 201, as can be seen from Fig. 2, when the clock selection signal 204 of MUX when t1 becomes 1 by 0 constantly, if fast clock signal 201 t 1 constantly be in the hopping edge near, can produce a burr signal 205.
This shows that under actual conditions, when asynchronous clock signal switched, the clock signal of MUX can produce burr signal.
Summary of the invention
In view of this, fundamental purpose of the present invention is to provide a kind of realization circuit of asynchronous clock signal switching, the burr signal that this circuit produces in the time of can avoiding switching between asynchronous clock signal.
Another object of the present invention is to provide a kind of implementation method of asynchronous clock signal switching, the burr signal that this method produces in the time of can avoiding switching between asynchronous clock signal.
Be an aspect that achieves the above object, the invention provides the realization circuit that a kind of asynchronous clock signal switches, this circuit comprises: state machine, synchronizing circuit, switch element and selector switch, wherein,
State machine is used to receive external input signal, produces different duties under the control of input signal, exports to the Clock gating signal of synchronizing circuit and the state of exporting to the clock selection signal of selector switch with control;
Synchronizing circuit is used for receive clock gate-control signal and asynchronous clock signal, guarantees that Clock gating signal and asynchronous clock signal are synchronous, and the Clock gating signal behind output synchronous is sent to switch element;
Switch element, be used to receive asynchronous clock signal and come self synchronization circuit synchronously after the Clock gating signal, open or close asynchronous clock signal according to the Clock gating signal synchronously, and the asynchronous clock signal that receives exported to selector switch;
Selector switch receives the clock selection signal from state machine, selects input channel according to the state of clock selection signal, and clock signal is the asynchronous clock signal from switch element.
Described asynchronous clock signal comprises current asynchronous clock signal and target asynchronous clock signal, and described state machine comprises first state and second state;
When described state machine was in first state, the present clock gate-control signal was for opening the current asynchronous clock signal;
When state machine switches to second state by first state, state machine output present clock gate-control signal is closed the current asynchronous clock signal, output clock selection signal select target asynchronous clock signal is as the output of selector switch, and export target Clock gating signal is opened the target asynchronous clock signal.
Described selector switch is two-way or the above selector switch of two-way, and described synchronizing circuit is two or more.
Described selector switch is the two-way selector switch, and described synchronizing circuit comprises first synchronizing circuit and second synchronizing circuit; Described switch element is and door, comprise first with door and second and; Described asynchronous clock signal comprises first asynchronous clock signal and second asynchronous clock signal, and described Clock gating signal comprises the first Clock gating signal and second clock gate-control signal;
When described state machine is in first state:
The clock selection signal that state machine sends to selector switch is an input channel for selecting first passage, the first Clock gating signal that sends to first synchronizing circuit is for opening first asynchronous clock signal, and the second clock gate-control signal that sends to second synchronizing circuit is for closing second asynchronous clock signal;
First synchronizing circuit receives first asynchronous clock signal and the first Clock gating signal, will with the first Clock gating signal of first asynchronous clock signal after synchronously send to first with door;
First with door receive first asynchronous clock signal and with the first Clock gating signal of first asynchronous clock signal after synchronously, and do with computing after, first asynchronous clock signal is sent to selector switch and from first passage input, the clock signal of selector switch is first asynchronous clock signal;
When described state machine switches to second state:
The clock signal of described state machine was carved with first hopping edge at default first o'clock, the clock selection signal that state machine sends to selector switch is an input channel for selecting first passage, and the first Clock gating signal that sends to first synchronizing circuit switches to closes first asynchronous clock signal;
After first synchronizing circuit receives first asynchronous clock signal and the first Clock gating signal, will with the first Clock gating signal of first asynchronous clock signal after synchronously send to first with door;
First with door receive first asynchronous clock signal and with the first Clock gating signal of first asynchronous clock signal after synchronously, and do with computing after, invalid signals is sent to selector switch and import on first passage, the clock signal of selector switch is an invalid signals;
The clock signal of described state machine was carved with second hopping edge at default second o'clock, the clock selection signal that state machine sends to selector switch is an input channel for selecting second channel, and the second clock gate-control signal is for closing second asynchronous clock signal;
After second synchronizing circuit receives second asynchronous clock signal and second clock gate-control signal, will with the second clock gate-control signal of second asynchronous clock signal after synchronously send to second with door;
Second with door receive second asynchronous clock signal and with the second clock gate-control signal of second asynchronous clock signal after synchronously, and do with computing after, invalid signals is sent to selector switch and import on second channel, the clock signal of selector switch is an invalid signals;
The clock signal of described state machine was carved with the 3rd hopping edge at default the 3rd o'clock, the clock selection signal that state machine sends to selector switch is an input channel for selecting second channel, and the second clock gate-control signal that state machine sends to second synchronizing circuit switches to opens second asynchronous clock signal;
After second synchronizing circuit receives second asynchronous clock signal and second clock gate-control signal, will with the second clock gate-control signal of second asynchronous clock signal after synchronously send to second with door;
Second with door receive second asynchronous clock signal and with the second clock gate-control signal of second asynchronous clock signal after synchronously, and carry out with computing after, second asynchronous clock signal is sent to selector switch and import on second channel, the selector switch clock signal is second asynchronous clock signal.
Be another aspect that achieves the above object, the invention provides the implementation method that a kind of asynchronous clock signal switches, this method comprises:
Set in advance state machine and receive external input signal,, the current asynchronous clock signal is switched to the target asynchronous clock signal, comprising when described state machine when externally state changes under the control of input signal:
A, state machine output present clock gate-control signal after described present clock gate-control signal and current asynchronous clock signal are synchronous, are used to close the current asynchronous clock signal;
B, state machine output clock selection signal, described clock selection signal is used for the selected target asynchronous clock signal;
C, state machine export target Clock gating signal after described target clock gate-control signal and target asynchronous clock signal are synchronous, are used to open the target asynchronous clock signal as current asynchronous clock signal and output.
Synchronous clock gate-control signal and asynchronous clock signal; Described state machine comprises first state and second state;
When described state machine was in first state, the present clock gate-control signal was for opening the current asynchronous clock signal;
When state machine switches to second state by first state, state machine output present clock gate-control signal is closed the current asynchronous clock signal, output clock selection signal select target asynchronous clock signal is as the output of selector switch, and export target Clock gating signal is opened the target asynchronous clock signal.
By above technical scheme as seen, the present invention sets in advance state machine, when state machine state changes, close the current asynchronous clock signal, the selected target asynchronous clock signal, open the target asynchronous clock signal as current asynchronous clock signal and output, the clock signal of selector switch switches to the target asynchronous clock signal by the present clock signal reposefully like this, has avoided the generation of burr signal.And the present invention can realize conversion stably between a plurality of asynchronous clock signals.
Description of drawings
Fig. 1 realizes the structural representation of circuit for MUX;
Fig. 2 is the view that the clock signal of MUX switches under actual conditions;
Fig. 3 is the process flow diagram of the implementation method of a kind of asynchronous clock signal switching of the present invention;
Fig. 4 is the structural representation of the realization circuit of a kind of asynchronous clock signal switching of the present invention;
Fig. 5 is the structural representation of the realization embodiment of circuit of a kind of asynchronous clock signal switching of the present invention;
Fig. 6 is the synoptic diagram according to the clock signal of the selector switch under the embodiment shown in Figure 5.
Embodiment
Fig. 3 is the process flow diagram of the implementation method of a kind of asynchronous clock signal switching of the present invention, as shown in Figure 3, may further comprise the steps:
Fig. 4 specifically is described below in conjunction with Fig. 3 for the structural representation of the realization circuit of a kind of asynchronous clock signal switching of the present invention.As shown in Figure 4, this circuit comprises state machine 401, selector switch 402, switch element and synchronizing circuit, be that the two-way selector switch is an example with selector switch 402 among Fig. 4, switch element comprises switch element n and switch element m, synchronizing circuit comprises synchronizing circuit n and synchronizing circuit m, and clock signal m and clock signal n are asynchronous clock signal.
Wherein, state machine 401 receives the clock signal of external input signal and state machine, produces different duties under the control of the clock signal of input signal and state machine, with the Clock gating signal of control output, and the state of the clock selection signal of output.State machine 401 sends to synchronizing circuit to the Clock gating signal, and clock selection signal is sent to selector switch 402.The specific implementation of state machine can be by existing hardware circuit developing instrument, and (FPGA) realizes such as field programmable gate array, repeats no more here.
Table 1 is the state table example of state machine 401, as shown in table 1, when the input signal of state machine 401 is in state 1, the clock n gate-control signal of state machine 401 outputs is for opening clock n signal, the clock m gate-control signal of output is for closing clock m signal, and the clock selection signal of output is the signal of selector channel 1.
The clock signal of state machine 401 is carved with first hopping edge when T, when the input signal of state machine 401 switches to state 2, the clock n gate-control signal of state machine 401 outputs switches to closes clock n signal, this moment, clock n gate-control signal was a hopping edge, the clock m gate-control signal of output is for closing clock m signal, and the clock selection signal of output is the signal of selector channel 1.The clock signal of state machine 401 is carved with second hopping edge when 2T, the clock n gate-control signal of state machine 401 outputs is for closing clock n signal, the clock m gate-control signal of output is for closing clock m signal, and the clock selection signal of output switches to the signal of selector channel 2.The clock signal of state machine 401 is carved with the 3rd hopping edge when 3T, the clock n gate-control signal of state machine 401 outputs is for closing clock n signal, the clock m gate-control signal of output switches to opens clock m signal, this moment, clock m gate-control signal was a hopping edge, and the clock selection signal of output is the signal of selector channel 2.When the clock signal of state machine 401 was come the hopping edge again, the state of the Clock gating signal of state machine 401 outputs and the clock selection signal of selector switch 402 was constant.
Table 1
Synchronizing circuit is used for receive clock gate-control signal and asynchronous clock signal, guarantees that Clock gating signal and asynchronous clock signal are synchronous, and the Clock gating signal behind output synchronous is sent to switch element.The specific implementation of synchronizing circuit belongs to technology as well known to those skilled in the art, can be referring to the correlation technique books.
Switch element, be used to receive asynchronous clock signal and come self synchronization circuit synchronously after the Clock gating signal, open or close asynchronous clock signal according to the Clock gating signal synchronously, and the asynchronous clock signal or the invalid signals that receive are exported to selector switch 402.
From foregoing description as seen, when the clock selection signal of selector switch 402 switches to the state of selector channel 2 by the state of selector channel 1, clock n gate-control signal and clock m gate-control signal are closes clock signal, clock signal n and clock signal m have promptly been closed simultaneously, when the clock signal of state machine 401 is carved with the 3rd hopping edge when 3T, clock m gate-control signal is for opening clock m signal, simultaneously, it is synchronous that Clock gating signal and asynchronous clock signal have kept, like this, the clock signal of selector switch 402 switches to clock signal m by clock signal n reposefully, has avoided the generation of burr signal.
For making purpose of the present invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
The structural representation of the realization embodiment of circuit that Fig. 5 switches for a kind of asynchronous clock signal of the present invention, as shown in Figure 5, this realizations circuit comprises: with door 1, with 2, state machine 501, selector switch 502, synchronizing circuit 1 and synchronizing circuit 2.Selector switch 502 is the two-way selector switch, when the clock selection signal of selector switch 502 is 1, selector switch 502 selector channel 1 are as input channel, when the clock selection signal of selector switch 502 is 0, selector switch 502 selector channel 2 are as input channel, and fast clock signal and slow clock signal are asynchronous clock signal.
Suppose when state 1, the input signal of state machine 501 is 1, at this moment, the clock selection signal that state machine 501 sends to selector switch 502 is 1, and the fast Clock gating signal of state machine 501 outputs is promptly opened fast clock signal for opening fast Clock gating signal 1, and a fast Clock gating signal sends to synchronizing circuit 1, the slow Clock gating signal of state machine 501 outputs is promptly closed slow clock signal for closing slow Clock gating signal 0, and slow Clock gating signal is sent to synchronizing circuit 2;
After synchronizing circuit 1 receives fast clock signal and fast Clock gating signal, will send to and door 1 with the fast Clock gating signal 1 of fast clock signal after synchronously;
With door 1 receive fast clock signal and with the fast Clock gating signal 1 of fast clock signal after synchronously, and do with computing after, fast clock signal sent to selector switch 502 and from passage 1 input, at this moment, because the clock selection signal of selector switch 502 is 1, so the clock signal of selector switch 502 is fast clock signal.
Fig. 6 is the synoptic diagram according to the clock signal of the selector switch under the embodiment shown in Figure 5, among Fig. 6, abscissa axis is a time shaft, axis of ordinates is an amplitude axis, and the oscillogram in each coordinate is represented the clock signal 603 of fast clock signal 601, slow clock signal 602, selector switch 502, the clock selection signal 604 of selector switch 502 and the clock signal 605 of state machine 501 respectively from top to bottom.
In conjunction with Fig. 5, the clock signal of state machine 501 is carved with first rising edge when T, state machine 501 switches to state 2, the input signal of state machine 501 switches to 0 by 1, the fast Clock gating signal of state machine 501 outputs is promptly closed fast clock signal for closing fast Clock gating signal 0, and fast Clock gating signal is sent to synchronizing circuit 1, at this moment, fast Clock gating signal is a negative edge;
After synchronizing circuit 1 receives fast clock signal and fast Clock gating signal, will send to and door 1 with the fast Clock gating signal 0 of fast clock signal after synchronously;
With door 1 receive fast clock signal and with the fast Clock gating signal 0 of fast clock signal after synchronously, and do with computing after, invalid signals 0 sent to selector switch 502 and from passage 1 input, at this moment, because the clock selection signal of selector switch 502 is 1, so the clock signal of selector switch 502 is 0.
The clock signal of state machine 501 is carved with second rising edge when 2T, the clock selection signal that state machine 501 sends to selector switch 502 is 0, and promptly the clock selection signal of selector switch 502 switches to 0 by 1, and at this moment, slow Clock gating signal is 0;
After synchronizing circuit 2 receives slow clock signals and slow Clock gating signal, will send to and door 2 with the slow Clock gating signal 0 of slow clock signal after synchronously;
With door 2 receive slow clock signals and with the slow Clock gating signal 0 of slow clock signal after synchronously, and do with computing after, invalid signals 0 sent to selector switch 502 and from passage 2 input, at this moment, because the clock selection signal of selector switch 502 is 0, therefore, the clock signal of selector switch 502 is 0.
The clock signal of state machine 501 is carved with the 3rd rising edge when 3T, the slow Clock gating signal of state machine 501 outputs is promptly opened slow clock signal for opening slow Clock gating signal 1, and slow Clock gating signal is sent to synchronizing circuit 2, at this moment, slow Clock gating signal is a rising edge;
After synchronizing circuit 2 receives slow clock signals and slow Clock gating signal, will send to and door 2 with the slow Clock gating signal 1 of slow clock signal after synchronously;
With door 2 receive slow clock signals and with the slow Clock gating signal 1 of slow clock signal after synchronously, and carry out with computing after, slow clock signal sent to selector switch 502 and from passage 2 input, at this moment, because the clock selection signal of selector switch 502 is 0, therefore, the clock signal of selector switch 502 is a slow clock signal.
Wherein being carved with rising edge with the clock signal of state machine 501 when T, 2T and the 3T in the present embodiment is example, and the clock signal of state machine 501 constantly also can have negative edge at T, 2T and 3T.
As seen from the above-described embodiment, when the clock selection signal of selector switch of the present invention switches to the state of selector channel 2 by the state of selector channel 1, fast Clock gating signal and slow Clock gating signal are closes clock signal, fast clock signal and slow clock signal have promptly been closed simultaneously, when the clock signal of state machine is carved with the 3rd rising edge when 3T, slow Clock gating signal is for opening slow clock signal, simultaneously, it is synchronous that Clock gating signal and asynchronous clock signal have kept, like this, the clock signal of selector switch switches to slow clock signal by fast clock signal reposefully, has avoided the generation of burr signal.
The above is preferred embodiment of the present invention only, is not to be used for limiting protection scope of the present invention.
Claims (6)
1, a kind of realization circuit of asynchronous clock signal switching is characterized in that this circuit comprises: state machine, synchronizing circuit, switch element and selector switch, wherein,
State machine is used to receive external input signal, produces different duties under the control of input signal, exports to the Clock gating signal of synchronizing circuit and the state of exporting to the clock selection signal of selector switch with control;
Synchronizing circuit is used for receive clock gate-control signal and asynchronous clock signal, guarantees that Clock gating signal and asynchronous clock signal are synchronous, and the Clock gating signal behind output synchronous is sent to switch element;
Switch element, be used to receive asynchronous clock signal and come self synchronization circuit synchronously after the Clock gating signal, open or close asynchronous clock signal according to the Clock gating signal synchronously, and the asynchronous clock signal that receives exported to selector switch;
Selector switch receives the clock selection signal from state machine, selects input channel according to the state of clock selection signal, and clock signal is the asynchronous clock signal from switch element.
2, circuit according to claim 1 is characterized in that, described asynchronous clock signal comprises current asynchronous clock signal and target asynchronous clock signal, and described state machine comprises first state and second state;
When described state machine was in first state, the present clock gate-control signal was for opening the current asynchronous clock signal;
When state machine switches to second state by first state, state machine output present clock gate-control signal is closed the current asynchronous clock signal, output clock selection signal select target asynchronous clock signal is as the output of selector switch, and export target Clock gating signal is opened the target asynchronous clock signal.
3, circuit according to claim 1 is characterized in that, described selector switch is two-way or the above selector switch of two-way, and described synchronizing circuit is two or more.
4, circuit according to claim 1 is characterized in that, described selector switch is the two-way selector switch, and described synchronizing circuit comprises first synchronizing circuit and second synchronizing circuit; Described switch element is and door, comprise first with door and second and; Described asynchronous clock signal comprises first asynchronous clock signal and second asynchronous clock signal, and described Clock gating signal comprises the first Clock gating signal and second clock gate-control signal;
When described state machine is in first state:
The clock selection signal that state machine sends to selector switch is an input channel for selecting first passage, the first Clock gating signal that sends to first synchronizing circuit is for opening first asynchronous clock signal, and the second clock gate-control signal that sends to second synchronizing circuit is for closing second asynchronous clock signal;
First synchronizing circuit receives first asynchronous clock signal and the first Clock gating signal, will with the first Clock gating signal of first asynchronous clock signal after synchronously send to first with door;
First with door receive first asynchronous clock signal and with the first Clock gating signal of first asynchronous clock signal after synchronously, and do with computing after, first asynchronous clock signal is sent to selector switch and from first passage input, the clock signal of selector switch is first asynchronous clock signal;
When described state machine switches to second state:
The clock signal of described state machine was carved with first hopping edge at default first o'clock, the clock selection signal that state machine sends to selector switch is an input channel for selecting first passage, and the first Clock gating signal that sends to first synchronizing circuit switches to closes first asynchronous clock signal;
After first synchronizing circuit receives first asynchronous clock signal and the first Clock gating signal, will with the first Clock gating signal of first asynchronous clock signal after synchronously send to first with door;
First with door receive first asynchronous clock signal and with the first Clock gating signal of first asynchronous clock signal after synchronously, and do with computing after, invalid signals is sent to selector switch and import on first passage, the clock signal of selector switch is an invalid signals;
The clock signal of described state machine was carved with second hopping edge at default second o'clock, the clock selection signal that state machine sends to selector switch is an input channel for selecting second channel, and the second clock gate-control signal is for closing second asynchronous clock signal;
After second synchronizing circuit receives second asynchronous clock signal and second clock gate-control signal, will with the second clock gate-control signal of second asynchronous clock signal after synchronously send to second with door;
Second with door receive second asynchronous clock signal and with the second clock gate-control signal of second asynchronous clock signal after synchronously, and do with computing after, invalid signals is sent to selector switch and import on second channel, the clock signal of selector switch is an invalid signals;
The clock signal of described state machine was carved with the 3rd hopping edge at default the 3rd o'clock, the clock selection signal that state machine sends to selector switch is an input channel for selecting second channel, and the second clock gate-control signal that state machine sends to second synchronizing circuit switches to opens second asynchronous clock signal;
After second synchronizing circuit receives second asynchronous clock signal and second clock gate-control signal, will with the second clock gate-control signal of second asynchronous clock signal after synchronously send to second with door;
Second with door receive second asynchronous clock signal and with the second clock gate-control signal of second asynchronous clock signal after synchronously, and carry out with computing after, second asynchronous clock signal is sent to selector switch and import on second channel, the selector switch clock signal is second asynchronous clock signal.
5, a kind of implementation method of asynchronous clock signal switching is characterized in that this method comprises:
Set in advance state machine and receive external input signal,, the current asynchronous clock signal is switched to the target asynchronous clock signal, comprising when described state machine when externally state changes under the control of input signal:
A, state machine output present clock gate-control signal after described present clock gate-control signal and current asynchronous clock signal are synchronous, are used to close the current asynchronous clock signal;
B, state machine output clock selection signal, described clock selection signal is used for the selected target asynchronous clock signal;
C, state machine export target Clock gating signal after described target clock gate-control signal and target asynchronous clock signal are synchronous, are used to open the target asynchronous clock signal as current asynchronous clock signal and output.
6, method according to claim 5 is characterized in that, synchronous clock gate-control signal and asynchronous clock signal; Described state machine comprises first state and second state;
When described state machine was in first state, the present clock gate-control signal was for opening the current asynchronous clock signal;
When state machine switches to second state by first state, state machine output present clock gate-control signal is closed the current asynchronous clock signal, output clock selection signal select target asynchronous clock signal is as the output of selector switch, and export target Clock gating signal is opened the target asynchronous clock signal.
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| CN100426182C true CN100426182C (en) | 2008-10-15 |
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| CN101135921B (en) * | 2007-10-10 | 2010-04-14 | 威盛电子股份有限公司 | Multiple clock switching mechanism and switch method thereof |
| CN110289840B (en) * | 2019-06-27 | 2023-04-11 | 百度在线网络技术（北京）有限公司 | Clock switching circuit and clock switching method for clock switching circuit |
Citations (3)
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| WO1997021163A1 (en) * | 1995-12-07 | 1997-06-12 | Ast Research, Inc. | Method and apparatus for determining the status of a shared resource |
| US5652536A (en) * | 1995-09-25 | 1997-07-29 | Cirrus Logic, Inc. | Non-glitch clock switching circuit |
| CN1442953A (en) * | 2002-06-11 | 2003-09-17 | 威盛-赛瑞斯公司 | Multiple nonsynchronous switch system |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5652536A (en) * | 1995-09-25 | 1997-07-29 | Cirrus Logic, Inc. | Non-glitch clock switching circuit |
| WO1997021163A1 (en) * | 1995-12-07 | 1997-06-12 | Ast Research, Inc. | Method and apparatus for determining the status of a shared resource |
| CN1442953A (en) * | 2002-06-11 | 2003-09-17 | 威盛-赛瑞斯公司 | Multiple nonsynchronous switch system |
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