CN110277360A - Power semiconductor including metal plate and the substrate being arranged on the metal plate - Google Patents

Power semiconductor including metal plate and the substrate being arranged on the metal plate Download PDF

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Publication number
CN110277360A
CN110277360A CN201910179118.8A CN201910179118A CN110277360A CN 110277360 A CN110277360 A CN 110277360A CN 201910179118 A CN201910179118 A CN 201910179118A CN 110277360 A CN110277360 A CN 110277360A
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China
Prior art keywords
metal plate
power semiconductor
main side
substrate
ceramic wafer
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CN201910179118.8A
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Chinese (zh)
Inventor
约尔格·阿蒙
哈拉尔德·科波拉
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Semikron GmbH and Co KG
Semikron Elektronik GmbH and Co KG
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Semikron GmbH and Co KG
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Publication of CN110277360A publication Critical patent/CN110277360A/en
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    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
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    • H01L2224/732—Location after the connecting process
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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The present invention relates to the power semiconductors (1) for including metal plate and the substrate being arranged on the metal plate comprising: metal plate (2)；It is disposed in substrate (3) on metal plate (2) and with ceramic wafer (3a), it is coated with the first metalization layer (3b) on the first main side (3a ') of the metal plate (2) in the ceramic wafer (3a), which is configured to form conductor rail (3b ')；It is disposed in power semiconductor assembly (4) that is on the conductor rail (3b ') and being conductively connected with the conductor rail (3b ')；And the adhesive (5) being disposed between the metal plate (2) and the substrate (3), the adhesive (5) has the corresponding Mechanical Contact with the first main side (3a ", 3c ') of the substrate (3) and the first main side (2a) of the metal plate (2), and is formed and the adhesive that the substrate (3) is connected to the metal plate (2) is combined connection in such a way that material combines.

Description

Power semiconductor including metal plate and the substrate being arranged on the metal plate
Technical field
The present invention relates to a kind of including metal plate and the power semiconductor device including being arranged substrate on a metal plate Part.
Background technique
10 2,016 104 283 A1 of DE discloses a kind of including metal plate and the base including being arranged on a metal plate The power semiconductor of plate, wherein substrate has ceramic wafer and through welding or sintering layer and in a manner of material combination It is integrated to bottom plate.In this case disadvantageously, during the connection of manufacture substrate and bottom plate, by welding or sintering layer, Entire arrangement is born compared with high heat load, and in the case where sinter layer, or even also in addition bears sizable pressure load, this It can result in and occur crack in ceramic wafer.
10 2,016 205 178 A1 of DE discloses a kind of substrate, is combined in a manner of material combination adhesive To radiator.
Summary of the invention
The object of the present invention is to provide a kind of reliable power semiconductor, can manufacture in a simple manner.
The target realized by a kind of power semiconductor, the power semiconductor: including metal plate；Including by cloth Set on a metal plate and substrate with ceramic wafer, coated with the on the first main side away from metal plate of the ceramic wafer One metalization layer, first metalization layer are configured to form conductor rail；Including be disposed in it is on conductor rail and The power semiconductor assembly being conductively connected with the conductor rail；And including the bonding being disposed between metal plate and substrate Agent, the adhesive have with the corresponding Mechanical Contact of the first main side of substrate and the first main side of metal plate, and formed with The adhesive that the mode that material combines connects the substrate to metal plate combines connection.
By being described below, advantageous embodiment of the invention is apparent.
Prove advantageously: the first main side of substrate is formed by the second main side towards metal plate of ceramic wafer, because this The thermal resistance of the second metalization layer is omitted in sample, and therefore, power semiconductor assembly is thermally coupled to metal plate well.
Furthermore, it was demonstrated that advantageously: the second metalization layer (its first main side that substrate is formed in face of the main side of metal plate) It is applied on the second main side in face of metal plate of ceramic wafer.Additional heat dissipation is realized by the second metalization layer.
Furthermore, it was demonstrated that advantageously: the adhesive phase formed by the adhesive between substrate and metal plate with a thickness of 5 μm To 25 μm.As a result, realizing substrate and the particularly good of metal plate is thermally coupled.
Furthermore, it was demonstrated that advantageously: the first main side of substrate and/or the first main side of metal plate have greater than 1 μm, especially It is greater than 10 μm of mean roughness depth.As a result, adhesive can be especially glued fast on corresponding main side.
Furthermore, it was demonstrated that advantageously: the first main side of substrate and/or the first main side of metal plate are taken turns with such surface It is wide, it may be assumed that the surface profile is formed by being introduced into corresponding main side and being respectively provided with the recess of geometry of restriction , wherein the geometry being recessed accordingly is formed in this way, it may be assumed that so that the cross section being recessed accordingly is by shape As rectangle, triangle, trapezoidal or oval section shape.As a result, realizing the connection of substrate and metal plate, this connection can be held By extra high mechanical load.
Furthermore, it was demonstrated that advantageously: the ratio between thickness of the thickness of metal plate and ceramic wafer is special in the range of 0.5 to 10 It is not in the range of 0.5 to 5, especially in the range of 0.5 to 2, because such words metal plate is relative to ceramic wafer quilt Formed so thin, so that in the case where ceramic wafer and metal plate heat, relatively easy due to ceramic wafer is being hung down Directly in the related capabilities gradually swelled on the direction of ceramic wafer, so big machinery will not be generated between ceramic wafer and metal plate Stress, as a result, greatly reducing the risk of ceramic wafer rupture.
Furthermore, it was demonstrated that advantageously: ceramic wafer with a thickness of 100 μm to 500 μm because in this case, ceramic wafer has Good mechanical stability.
Furthermore, it was demonstrated that advantageously: adhesive, which has, is greater than 1W/mK, the particularly greater than thermal conductivity of 2W/mK.As a result, real Substrate is showed and the good of metal plate is thermally coupled.
Furthermore, it was demonstrated that advantageously: metal plate is a part of the cooling radiator of liquid, wherein the cooling radiator of liquid With cavity, liquid can flow through the cavity, wherein and metal plate limits a part of cavity, because in this case, in function During rate semiconductor devices works, the heat of metal plate is directly emitted to flowing by cooling Jie of liquid of power semiconductor Matter, such as water.
In addition, in this background, it was demonstrated that advantageously: the cooling radiator of liquid has such main body, it may be assumed that the main body With such geometry, it may be assumed that so that the geometry defines a part of cavity, wherein metal plate connects in fluid-tight manner To main body, because in this case, radiator is formed in a particularly simple way.
In addition, in this background, it was demonstrated that advantageously: metal plate and main body are integrally formed, because in this case, metal Plate is connected to main body with the fluid tight manner with long-time stability, and metal plate can extremely efficiently give birth to together with main body It produces, such as the extrusion workpiece produced by extrusion method, and thus is easy to be mass produced.
Furthermore, it was demonstrated that advantageously: metal plate has the first main side from metal plate and/or the second main side from metal plate The Material weakening region in metal plate is extended to, second main side is arranged to opposite with the first main side of metal plate, wherein Material weakening region extends around substrate.Material weakening region improve ceramic wafer be easy on the direction perpendicular to ceramic wafer by The ability gradually swelled, so that ceramic wafer even can also swell under the action of the consumption of lesser power.
In this background, it was demonstrated that advantageously: Material weakening region is disposed in the region that metal plate is connected to main body In.As a result, further improving the ability for being easy gradually to swell by Material weakening region.
Furthermore, it was demonstrated that advantageously: Material weakening region extends directed along the edge of metal plate, or along metal plate Edge simultaneously extends with border a distance of metal plate.If Material weakening region is prolonged directed along the edge of metal plate It stretches, then Material weakening region is especially effective.If Material weakening region along metal plate edge and with the edge phase of metal plate Extend away from a distance, then metal plate can be connected in a manner of showing extra high mechanical load-bearing capacity in the edge of metal plate It is connected to any metallic object.
Furthermore, it was demonstrated that advantageously: Material weakening region is formed to be recessed, because in this case, Material weakening region It can produce in a particularly simple way.
In this background, it was demonstrated that advantageously: range of the ratio of recessed depth and plate thickness 0.1 to 0.5 It is interior, because in this case, on the one hand, metal plate even can also swell under the action of the consumption of very small power, on the other hand, Metal plate still has good mechanical stability.
Furthermore, it was demonstrated that advantageously: the recessed depth at the folding corner region of recessed extension route is than recessed extension Deep the 10% to 30% of other regions of route.As a result, power consumption needed for metal plate protuberance is further reduced.
Furthermore, it was demonstrated that advantageously: cooling pin or cooling fins extend out from the second main side of metal plate, and described Two main sides are arranged to opposite with the first main side of metal plate.As a result, realizing the particularly efficient cooling to metal plate.
Detailed description of the invention
Below with reference to the accompanying drawings exemplary embodiment of the present invention is explained, in the accompanying drawings:
Fig. 1 shows the sectional view of one embodiment of power semiconductor according to the present invention,
Fig. 2 shows the sectional view of another embodiment of power semiconductor according to the present invention,
Fig. 3 shows the detailed of Fig. 1 and Fig. 2 of the embodiment variant example about power semiconductor according to the present invention View,
Fig. 4 shows the metal plate of power semiconductor according to the present invention and the substrate of the power semiconductor The plan view associated with Fig. 1 and Fig. 2 of one embodiment, the substrate are arranged on a metal plate, and
Fig. 5 shows the metal plate of power semiconductor according to the present invention and the substrate of the power semiconductor The plan view of another embodiment, the substrate are arranged on a metal plate.
In the accompanying drawings, identical element appended drawing reference having the same.
Specific embodiment
Fig. 1 shows the sectional view of one embodiment of power semiconductor according to the present invention.Fig. 2 shows bases The sectional view of another embodiment of power semiconductor of the invention,
The substrate that corresponding power semiconductor 1 according to the present invention has metal plate 2 and is disposed on metal plate 2 3.Substrate 3 has ceramic wafer 3a, is coated on the first main side 3a ' away from metal plate 2 of ceramic wafer 3a and is configured to shape At the first metalization layer 3b of conductor rail 3b '.Conductor rail 3b ' is disposed in ceramics in mode spaced from each other On plate 3a.Conductor rail 3b' is disposed on ceramic wafer 3a in a manner of being electrically insulated from each other.For example, substrate 3 can be formed Direct copper substrate (DCB substrate) is formed active metal brazing substrate (AMB substrate).
It is disposed on conductor rail 3b ' and connects with conductor rail 3b ' conduction in addition, power semiconductor 1 has The power semiconductor assembly 4 connect.Power semiconductor assembly 4 is preferably (for example, by being disposed in such a way that material combines Welding or sintering layer between power semiconductor assembly 4 and strip conductor 3b') and it is electrically connected to conductor rail 3b', in order to clear Chu Qijian, the layer are not shown in fig. 1 and 2.Corresponding power semiconductor assembly 4 is preferably with power semiconductor switch Or the form of diode exists.In this case, corresponding power semiconductor switch 4 is preferably deposited in the form of transistor , such as, such as IGBT (insulated gate bipolar transistor), or with MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or The form of person's thyristor exists.Under the background of exemplary embodiment, power semiconductor assembly 4 for example passes through conductive film composite wood Material or combination wire (being not shown in Fig. 1 and Fig. 2) are electrically interconnected, such as to form at least one half-bridge circuit, the half-bridge circuit example It such as can be used in rectification or reversal voltage and electric current.
Power semiconductor 1 also has the adhesive 5 being disposed between metal plate 2 and substrate 3, and this adhesive exists With the first main side 3a " (referring to Fig. 1) or 3c ' (referring to fig. 2) of substrate 3 and metal plate 2 is all had in the case where difference The Mechanical Contact of one main side 2a, and formed to combine the adhesive that substrate 3 is connected to metal plate 2 with material combination and be connected It connects.
In the case where the conventional connection of substrate and bottom plate in the art, by welding or sintering layer, entire arrangement is held By compared with high heat load, and in the case where sinter layer, or even it is also in addition subjected to sizable pressure load, this may cause pottery Occurs crack in porcelain plate.In contrast, it can be generated in the case where the relatively high heat load and high voltage load of no arrangement It states adhesive and combines connection.
In the exemplary embodiment according to Fig. 1, the first main side of substrate 3 is by ceramic wafer 3 in face of the second of metal plate 2 Main side 3a " formation.In exemplary embodiment according to fig. 2, by comparing the exemplary embodiment according to Fig. 1, substrate 3 is in addition With the second metalization layer 3c, second metalization layer 3c is applied to the second main side 3a " towards metal plate 2 of ceramic wafer 3a On, and the main side that substrate 3 is formd towards the main side 3c' of metal plate 2 of second metalization layer 3c.Second metalization layer 3c It can be formed in a manner of unstructured, as in exemplary embodiment according to fig. 2, but also can be in a structured manner It is formed.Otherwise, exemplary embodiment according to fig. 2 is consistent with according to the exemplary embodiment of Fig. 1.According to the exemplary reality of Fig. 1 Applying example has the advantages that better than exemplary embodiment according to fig. 2, that is, firstly, the thermal resistance of the second metalization layer 3c is omitted, because And power semiconductor assembly 4 is coupled to metal plate 2 with low thermal resistance, and secondly, substrate 3 is more cost effective.According to fig. 2 Exemplary embodiment has the advantages that better than the exemplary embodiment according to Fig. 1, it may be assumed that is realized by means of the second metalization layer 3c Additional heat dissipation.
Metal plate 4 can be formed as being integrally formed in the exemplary embodiment, but also with more part ways. Metal plate 4 can be formed for example by copper, copper alloy, aluminum or aluminum alloy.In the case where forming metal plate 4 with more part ways, The connection metal plate (the connection metal plate can be such as made of copper or copper alloy) of metal plate 4 can be applied to metal plate 4 Bottom metal plate on (the bottom metal plate can be for example made of aluminum or aluminum alloy).In this case, adhesive 5 has and gold Belong to the Mechanical Contact of the connecting plate of plate 4.
The thickness d 3 of the adhesive phase 5' formed by the adhesive 5 between substrate 3 and metal plate 2 is preferably 5 μm to 25 μm, And thus thinly formed very much compared with normal welding in the prior art or sinter layer, substrate conventionally by the welding or Sinter layer and be connected to such as radiator.As a result, realizing the particularly preferred hot link of substrate 3 Yu metal plate 2.As a result, with The metal connection of material combination is compared, and the usual lower heating conduction of adhesive accesses compensation.Adhesive 5 is preferably With being greater than 1W/mK, the particularly greater than thermal conductivity of 2W/mK, and thus preferably there is relatively high thermal conductivity.Adhesive 5 can be formed such as epobond epoxyn, wherein the epoxy resin of epobond epoxyn is filled with heat-conducting metal Or ceramic particle.Adhesive 5 can be nonconducting or conductive.
The the first main side 3a " or 3c' of substrate 3 and/or the first main side 2a of metal plate 2 preferably have greater than 1 μm, especially It is greater than 10 μm of mean roughness depth Rz.As a result, adhesive 5 can especially be firmly bonded to corresponding main side 3a ", 3c' and/or 2a, so that adhesive shows extra high mechanical load-bearing capacity in conjunction with connection.First main side 3a " of substrate 3 or First main side 2a of 3c' and/or metal plate 2 preferably has 100 μm of maximum mean roughness depth Rz.It should be noted that Within the meaning of the present invention, mean roughness depth Rz should be understood to refer to according to the average thick of DIN EN ISO 4287 The definition of rugosity depth Rz.
As in Fig. 3 with illustrated by example, the first main side 3a " or 3c' of substrate 3 and/or the first main side of metal plate 2 2a can have such surface profile, it may be assumed that the surface profile is by being introduced into corresponding main side and being respectively provided with limit Recess 6a, 6b, 6c and/or 6d of fixed geometry and formed, wherein be recessed 6a accordingly, 6b, and 6c and/or 6d's is several What shape is formed in this way, it may be assumed that so that the cross section of be recessed accordingly 6a, 6b, 6c and/or 6d are formed rectangle 6a, triangle 6b, trapezoidal 6c or oval section shape 6d.In this case, corresponding recess for example can be in the form of such It is formed: the channel away formed with corresponding geometry, or in the form of the blind hole that corresponding geometry is formed.Blind hole energy Enough it is arranged to such as matrix form.The substrate 3 of extra high mechanical load-bearing capacity is shown to metal plate 2 as a result, realizing Connection.
The ratio between thickness d 1 and the thickness d 2 of ceramic wafer 3a of metal plate 2 are preferably in the range of 0.5 to 10, especially In the range of 0.5 to 5, especially in the range of 0.5 to 2.The thickness d 2 of ceramic wafer 3a is preferably 100 μm to 500 μm.Cause And metal plate 2 is formed thinly, so that metal plate 2 is swelled required power relatively on the direction N perpendicular to ceramic wafer 3a It is low.During power semiconductor 1 operates, ceramic wafer 3a and metal plate 2 are greatly heated by power semiconductor assembly 4, by In the different thermal expansion coefficients of ceramic wafer 3a and metal plate 2, this heating causes these to be bonded to each other between the element of combination Mechanical stress it is very big.As a result, especially crack can be generated in ceramic wafer 3a in the case where big temperature fluctuation.Such as Fruit metal plate 2 forms relatively thin, then it can be swelled when heated, and thus can mechanically follow ceramics by its protuberance The expansion of plate 3a as a result, will not generate very big mechanical stress between ceramic wafer 3a and metal plate 2, thus substantially reduces The risk in crack is generated in the ceramic wafer 3a.The thickness d 2 of ceramic wafer 3a is bigger, then the mechanical load that ceramic wafer 3a is born It is bigger, and thus the thickness d 1 of metal plate 2 can be bigger.However, the thickness d 2 with ceramic wafer 3a increases, ceramic wafer 3a's Thermal resistance (it is intended that as small as possible) also increases.If the ratio of the thickness d 2 of the thickness d 1 of metal plate 2 and ceramic wafer 3a 0.5 to In the range of 10, especially in the range of 0.5 to 5, especially in the range of 0.5 to 2, then metal plate 2 is relative to ceramics Plate 3a is formed so thin, so that in the case where heating ceramic plate 3a and metal plate 2, opposite due to ceramic wafer 3a is held The related capabilities easily swelled on the direction N perpendicular to ceramic wafer 3a, so will not be generated between ceramic wafer 3a and metal plate 2 Very big mechanical stress, as a result, greatly reduce and occur the risk in crack in ceramic wafer 3a.
Metal plate 2 can be a part of the cooling radiator 7 of liquid, wherein the cooling radiator 7 of liquid has cavity 8, liquid Body can flow through cavity 8, wherein metal plate 2 defines a part of cavity 8.The cooling radiator 7 of liquid preferably has master Body 9, main body 9 have such geometry, it may be assumed that so that the geometry defines a part of cavity 8, wherein metal plate 2 is with liquid Close mode is connected to main body 9.In this case, metal plate 2 can be for example, by being soldered to main body 9 or being screwed to master It is connected to main body 9 in fluid-tight manner on body 9, is mechanically inserted between metal plate 2 and main body 9 wherein sealing.
However, being extremely advantageous that: metal plate 2 is connected to main body 9 and being integrally formed with main body 9 in fluid-tight manner, As in exemplary embodiment.If metal plate 2 and main body 9 are integrally formed, can be ensured with extreme high reliability Metal plate 2 is connected to main body 9 in fluid-tight manner and has long-time stability.As a result, by by way of designing control, from one Start to avoid sufficiently to implement weld seam or the tightness problems due to caused by seal aging due to no.In addition, metal The integrally formed major advantage having of plate 2 and main body 9 is that metal plate 2 can be extremely efficiently produced with main body 9 together Come, for example, as the extrusion workpiece produced by extrusion method, and thus be easy to be mass produced.Therefore, to pass through design The mode of control, it is entirely avoided for generating the technical complicated and easy error of the close connection of liquid of metal plate 2 and main body 9 Welding procedure or screw-coupling process.Importantly, in practice, producing this very favorable power semiconductor 1 (wherein metal plate 2 is integrally formed with main body 9) only be only in this case it is technical and/or economically possible, That is: such as the case where in the present invention, substrate 3 adhesive in conjunction with connection and by material combination in a manner of be integrated to metal Plate 2.It include the cooling radiator 7 of relatively bulky liquid if using welded connecting rather than adhesive combines connection Entire power semiconductor must long-time heating, the weldering being disposed between substrate 3 and metal plate 2 with fusing in furnace Material, firstly, this is very time-consuming and energy-intensive, secondly, power semiconductor assembly 4 may be due to length relevant to heating Phase heat effect and be damaged.If using sintering connection rather than adhesive combines connection, in order to generate sintering connection, include The entire power semiconductor of the cooling radiator 7 of relatively bulky liquid must be disposed in sintering press, and be burnt Very high pressure must be applied on metal plate 2 by knot pressure machine on the direction towards main body 9, and this pressure will at least result in The severe bends on the direction of main body 9 of metal plate 2, and will therefore result in and occur crack in ceramic wafer.In addition, welding or burning In the case where knot connection, must there must be the second metalization layer 3c.
Metal plate 2 preferably has to be extended to from the first main side 2a of metal plate 2 and/or the second main side 2b of metal plate 2 Material weakening region 10 in metal plate 2, second main side be arranged to it is opposite with the first main side 2a of metal plate 2, wherein Material weakening region 10 extends around substrate 3.Metal plate 2 is mechanically weakened in Material weakening region 10.Such as exemplary Situation in embodiment is such, it is preferred that and Material weakening region 10 is formed to be recessed, and is especially formed as groove, but Be also can for example be formed metal plate 2 by being heat-treated and/or being chemically treated the region mechanically weakened 10.Fig. 4 shows The plan view associated with Fig. 1 and Fig. 2 of substrate 3 for having gone out metal plate 2 and being disposed on metal plate 2, wherein substrate 3 with The mode shown by a dotted line is only highly schematically shown.Material weakening region 10, i.e. in the exemplary embodiment recessed 10 directed along the metal plate 2 in Fig. 4 edge 2c extend.The base that Fig. 5 shows metal plate 2 and is disposed on metal plate 2 The plan view of another embodiment of plate 3, wherein, Material weakening region 10 different from according to the embodiment of metal plate 2 of Fig. 4, It is herein recessed 10 along the edge 2c of metal plate 2 and extends a distance away with the edge 2c of metal plate 2.
Material weakening region 10 increases the ability that ceramic wafer 3a is easy to swell on the direction N perpendicular to ceramic wafer 3a, Ceramic wafer 3a even can also be swelled under the action of the consumption of lesser power, so that in heating ceramic plate 3a and metal In the case where plate 2, the mechanical stress acted on ceramic wafer 3a is further decreased.
The Material weakening region 10 of metal plate 2 is to be recessed 10 to prolong in a manner of closed around substrate 3 herein It stretches, as shown in example, or recessed 10 have at least one interruption in Fig. 4 and Fig. 5.
Material weakening region 10 is recessed 10 herein, is preferably disposed in metal plate 2 and is connected to main body 9 In region 11.
If the ratio of the thickness d 1 of recessed 10 depth t1 and metal plate 2 is in the range of 0.1 to 0.5, one side, Metal plate 2 can swell under the action of the consumption of very small power, and on the other hand, metal plate 2 still has good Mechanical stability.
Recessed 10 depth t1 at the folding corner region 10a of recessed extension route is preferably than recessed extension route The depth of other region 10b deep 10% to 30%.It is further reduced as a result, metal plate 2 is made to swell required power consumption.
As shown in example, cooling pin 12 or cooling fins 12 can be from the second of metal plate 2 in Fig. 1 and Fig. 2 Main side 2b rises and extends out, and second main side is arranged to opposite with the first main side 2a of metal plate 2.It is alternatively gold The arrangement on radiator can be also arranged for by belonging to plate 2, wherein heat-conducting cream or solder or sinter layer can be disposed in metal Between plate 2 and radiator.
It should be noted that certainly, without departing from the scope of the invention, different exemplary embodiments of the invention Feature, if these features do not have to be mutually exclusive, these features can be combined with each other in any desired way.

Claims (18)

1. a kind of power semiconductor: including metal plate (2), including being disposed on the metal plate (2) and having The substrate (3) of ceramic wafer (3a), in being coated on first main side (3a ') of the metal plate (2) for the ceramic wafer (3a) Have the first metalization layer (3b), first metalization layer (3b) is configured to form conductor rail (3b ')；Including being arranged Power semiconductor assembly (4) that is on the conductor rail (3b ') and being conductively connected with the conductor rail (3b ')；And And the adhesive (5) including being disposed between the metal plate (2) and the substrate (3), described adhesive (5) have and institute The corresponding Mechanical Contact of the first main side (3a ", 3c ') of substrate (3) and the first main side (2a) of the metal plate (2) is stated, and And it is formed and the adhesive that the substrate (3) is connected to the metal plate (2) is combined in conjunction in a manner of by connection by material.
2. power semiconductor according to claim 1, which is characterized in that first main side of the substrate (3) It is formed by the second main side (3a ") towards the metal plate (2) of the ceramic wafer (3).
3. power semiconductor according to claim 1, which is characterized in that the second metalization layer (3c) is applied to institute State on the second main side (3a ") towards the metal plate (2) of ceramic wafer (3a), second metalization layer (3c) towards institute The main side (3c ') for stating metal plate (2) forms first main side of the substrate (3).
4. power semiconductor described in any one of -3 according to claim 1, which is characterized in that by the substrate (3) The thickness (d3) for the adhesive phase (5 ') that described adhesive (5) between the metal plate (2) is formed is 5 μm to 25 μm.
5. power semiconductor described in any one of -3 according to claim 1, which is characterized in that the substrate (3) First main side (3a ", 3c ') and/or first main side (2a) of the metal plate (2), which have, is greater than 1 μm, especially greatly In 10 μm of mean roughness depth (Rz).
6. power semiconductor described in any one of -3 according to claim 1, which is characterized in that the substrate (3) First main side (3a ", 3c ') and/or first main side (2a) of the metal plate (2) have such surface profile, That is: the described surface profile is by geometry that is being introduced into the corresponding main side (2a, 3a ", 3c ') and being respectively provided with restriction The recess (6a, 6b, 6c, 6d) of shape and formed, wherein the geometry of the corresponding recess (6a, 6b, 6c, 6d) with Such mode is formed, it may be assumed that so that the cross section of the corresponding recess (6a, 6b, 6c, 6d) be formed rectangle (6a), Triangle (6b), trapezoidal (6c) or oval section shape (6d).
7. power semiconductor described in any one of -3 according to claim 1, which is characterized in that the metal plate (2) Thickness (d1) and the ceramic wafer (3a) the ratio between thickness (d2) in the range of 0.5 to 10, especially 0.5 to 5 model In enclosing, especially in the range of 0.5 to 2.
8. power semiconductor described in any one of -3 according to claim 1, which is characterized in that the ceramic wafer (3a) The thickness (d2) be 100 μm to 500 μm.
9. power semiconductor described in any one of -3 according to claim 1, which is characterized in that the metal plate (2) It is a part of liquid cooling radiator (7), wherein the liquid cooling radiator (7) has cavity (8), and liquid can flow It is dynamic to pass through the cavity (8), wherein the metal plate (2) defines a part of the cavity (8).
10. power semiconductor according to claim 9, which is characterized in that the liquid cooling radiator (7) has Main body (9), the main body (9) have such geometry, it may be assumed that so that the geometry defines a part of cavity (8), wherein the metal plate (2) is connected to the main body (9) in fluid-tight manner.
11. power semiconductor according to claim 10, which is characterized in that the metal plate (2) and the main body (9) it is integrally formed.
12. power semiconductor described in any one of -3 according to claim 1, which is characterized in that the metal plate (2) It is extended to first main side (2a) from the metal plate (2) and/or from the second main side (2b) of the metal plate (2) Material weakening region (10) in the metal plate (2), second main side (2b) are arranged to the institute with the metal plate (2) It is opposite to state the first main side (2a), wherein the Material weakening region (10) extends around the substrate (3).
13. according to power semiconductor described in the claim 12 of reference claim 10 or 11, which is characterized in that described Material weakening region (10) is disposed in the metal plate (2) and is connected in the region (11) of the main body (9).
14. power semiconductor according to claim 12, which is characterized in that the Material weakening region (10) is direct Along the metal plate (2) edge (2c) extend, or along the metal plate (2) the edge (2c) and with the gold The edge (2c) for belonging to plate (2) extends a distance away.
15. power semiconductor according to claim 12, which is characterized in that the Material weakening region (10) is by shape As recessed.
16. power semiconductor according to claim 15, which is characterized in that the depth (t1) of recessed (10) with The ratio of the thickness (d1) of the metal plate (2) is in the range of 0.1 to 0.5.
17. power semiconductor according to claim 15 or 16, which is characterized in that the extension road of recessed (10) Other regions of the depth of recessed (10) at the folding corner region (10a) of line than the extension route of recessed (10) Deep 10% to 30% at (10b).
18. power semiconductor described in any one of -3 according to claim 1, which is characterized in that cooling pin (12) or Cooling fins (12) extends out from the second main side (2b) of the metal plate (2), and second main side (2b) is arranged to It is opposite with first main side (2a) of the metal plate (2).
CN201910179118.8A 2018-03-16 2019-03-11 Power semiconductor including metal plate and the substrate being arranged on the metal plate Pending CN110277360A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5291065A (en) * 1991-12-16 1994-03-01 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of fabricating semiconductor device
JP2012160642A (en) * 2011-02-02 2012-08-23 Mitsubishi Materials Corp Substrate for power module with heat sink, and manufacturing method of substrate for power module with heat sink, and power module

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04162756A (en) * 1990-10-26 1992-06-08 Toshiba Corp Semiconductor module
JP3946018B2 (en) * 2001-09-18 2007-07-18 株式会社日立製作所 Liquid-cooled circuit device
DE102009000541B4 (en) * 2009-02-02 2014-07-24 Infineon Technologies Ag Method for reducing the surface roughness of a metallic surface and method for producing a power semiconductor module
US9812377B2 (en) * 2013-09-04 2017-11-07 Mitsubishi Electric Corporation Semiconductor module and inverter device
DE102014111786A1 (en) * 2014-08-19 2016-02-25 Infineon Technologies Ag Cooling plate, component comprising a cooling plate, and method of manufacturing a cooling plate
DE102015104518B3 (en) * 2015-03-25 2016-03-10 Infineon Technologies Ag A method of making a circuit carrier assembly having a support having a surface formed by an aluminum-silicon carbide-metal matrix composite
DE102015111667A1 (en) * 2015-07-17 2017-01-19 Rogers Germany Gmbh Substrate for electrical circuits and method for producing such a substrate
DE102016104283B4 (en) 2016-03-09 2019-05-16 Semikron Elektronik Gmbh & Co. Kg Power semiconductor device with a power semiconductor module with a housing
DE102016205178A1 (en) 2016-03-30 2017-10-05 Siemens Aktiengesellschaft Adhesive for connecting a power electronic assembly with a heat sink and composite thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5291065A (en) * 1991-12-16 1994-03-01 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of fabricating semiconductor device
JP2012160642A (en) * 2011-02-02 2012-08-23 Mitsubishi Materials Corp Substrate for power module with heat sink, and manufacturing method of substrate for power module with heat sink, and power module

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