CN110262190B - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN110262190B CN110262190B CN201910532707.XA CN201910532707A CN110262190B CN 110262190 B CN110262190 B CN 110262190B CN 201910532707 A CN201910532707 A CN 201910532707A CN 110262190 B CN110262190 B CN 110262190B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 113
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 44
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 121
- 239000000758 substrate Substances 0.000 claims abstract description 119
- 238000005530 etching Methods 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims description 54
- 238000000059 patterning Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 abstract description 7
- 239000000463 material Substances 0.000 description 16
- 230000000903 blocking effect Effects 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 7
- 238000000151 deposition Methods 0.000 description 6
- 229910052732 germanium Inorganic materials 0.000 description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 6
- 239000012212 insulator Substances 0.000 description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000001154 acute effect Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000001311 chemical methods and process Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/16—Coating processes; Apparatus therefor
- G03F7/162—Coating on a rotating support, e.g. using a whirler or a spinner
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- General Physics & Mathematics (AREA)
- Element Separation (AREA)
- Weting (AREA)
Abstract
The invention provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises the following components: a substrate, wherein a groove is formed on the substrate, and a retaining wall is formed on the substrate on at least one side of the groove; and the semiconductor pattern is positioned on the substrate, the retaining wall is arranged between the semiconductor pattern and the groove, when photoresist is coated, the photoresist is dripped on the substrate, the photoresist is covered on the whole substrate through rotation, and the retaining wall can prevent the photoresist in the groove from overflowing outwards, so that the uniformity of the photoresist in the effective area of the chip is improved, the uniformity of subsequent etching is improved, and finally the performance of the semiconductor device is improved; meanwhile, the surface deposition and surface planarization cost can be saved, so that the production cost is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a manufacturing method thereof, which are used for relieving photoresist streaks.
Background
Semiconductor fabrication techniques require a variety of different physical and chemical processes to be performed on a semiconductor substrate, and photolithography is one of the most important processes of semiconductor fabrication techniques. The photolithography process is a main process of removing a specific portion of a thin film on a wafer surface through a series of production steps, and a thin film with a micro pattern structure can be formed on the wafer surface through photolithography and etching.
The use of photoresist is necessarily involved in the photolithography process. When the photoresist is coated, the photoresist is dropped at the center of the wafer, and the photoresist is fully covered on the whole wafer by a rotary centrifugal force mode to form a photoetching pattern.
Because of the complex chip manufacturing process, multiple photolithography and etching processes are required to be performed on the wafer surface to realize the circuit connection and other structures. However, the surface topography of the wafer becomes uneven due to the increasing front-layer process. Particularly, after the deep trench is etched, the photoresist flowing into the deep trench flows onto the wafer again along with the rotation of the wafer, so that photoresist streaks appear on the surface of the wafer, and the uniformity of the photoresist thickness in the effective area of the chip is deteriorated, thereby affecting the uniformity of the critical dimension (CD uniformity).
Disclosure of Invention
Based on the above-mentioned problems, an object of the present invention is to provide a semiconductor structure and a method for manufacturing the same, so as to alleviate photoresist streaks and improve photoresist uniformity, thereby improving the performance of semiconductor devices.
To achieve the above object, the present invention provides a semiconductor structure comprising:
a substrate, wherein a groove is formed on the substrate, and a retaining wall is formed on the substrate on at least one side of the groove; the method comprises the steps of,
and the semiconductor pattern is positioned on the substrate, and the retaining wall is arranged between the semiconductor pattern and the groove.
Optionally, in the semiconductor structure, the material of the retaining wall includes a dielectric layer or/and a photoresist.
Correspondingly, the invention also provides a manufacturing method of the semiconductor structure, which comprises the following steps:
providing a substrate, and forming a dielectric layer on the substrate; the method comprises the steps of,
and forming a dielectric layer pattern, a groove and a retaining wall, wherein the groove is positioned in the substrate, the retaining wall is formed on the substrate on at least one side of the groove, and the retaining wall is arranged between the dielectric layer pattern and the groove.
Optionally, in the method for manufacturing a semiconductor structure, the step of forming the dielectric layer pattern, the recess and the retaining wall includes:
etching the dielectric layer to form a dielectric layer pattern and a retaining wall; the method comprises the steps of,
the substrate is etched to form a recess.
Optionally, in the method for manufacturing a semiconductor structure, after forming the dielectric layer pattern and the retaining wall, before forming the groove, or after forming the groove, the method further includes: and forming a semiconductor pattern on the dielectric layer pattern.
Optionally, in the method for manufacturing a semiconductor structure, after forming the dielectric layer pattern and the retaining wall, before forming the groove, the method further includes: etching the retaining wall to enable one side of the retaining wall, which is close to the groove, to be an inclined surface, and enabling one side, which is far away from the substrate, of the inclined surface to be inclined towards the groove.
Optionally, in the method for manufacturing a semiconductor structure, the method for forming the dielectric layer and the retaining wall includes:
forming a patterned first photoresist layer on the dielectric layer;
etching the dielectric layer by taking the patterned first photoresist layer as a mask until the substrate is exposed, so as to form the dielectric layer pattern and the retaining wall; the method comprises the steps of,
and removing the patterned first photoresist layer.
Optionally, in the method for manufacturing a semiconductor structure, the method for forming the groove includes:
forming a patterned second photoresist layer on the substrate, wherein the patterned second photoresist layer covers the substrate, the dielectric layer pattern and the retaining wall;
etching the substrate by taking the patterned second photoresist layer as a mask to form the groove; the method comprises the steps of,
and removing the patterned second photoresist layer.
Optionally, in the method for manufacturing a semiconductor structure, the step of forming the dielectric layer pattern, the recess and the retaining wall includes:
etching the dielectric layer to form a dielectric layer pattern;
etching the substrate to form a groove; the method comprises the steps of,
forming a photoresist layer and patterning to form a retaining wall.
Optionally, in the method for manufacturing a semiconductor structure, the retaining wall is a structure with a wide top and a narrow bottom.
Compared with the prior art, in the semiconductor structure and the manufacturing method thereof, the retaining wall is formed on the substrate at least at one side of the groove, the retaining wall is arranged between the semiconductor pattern and the groove, when the photoresist is coated, the photoresist is dripped on the substrate, the photoresist is covered on the whole substrate through rotation, and the retaining wall can prevent the photoresist in the groove from overflowing outwards, so that the uniformity of the photoresist in the effective area of the chip is improved, the uniformity of subsequent etching is improved, and finally the performance of a semiconductor device is improved; meanwhile, the surface deposition and surface planarization cost can be saved, so that the production cost is reduced.
Drawings
Fig. 1 is a schematic diagram of a semiconductor structure according to an embodiment of the invention.
Fig. 2 is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present invention.
Fig. 3 to 8 are schematic views illustrating steps of a method for fabricating a semiconductor structure according to a first embodiment of the present invention.
Fig. 9 to 15 are schematic views illustrating the steps of a method for fabricating a semiconductor structure according to a second embodiment of the present invention.
Detailed Description
Based on the above problems, the present invention provides a semiconductor structure, comprising: a substrate, wherein a groove is formed on the substrate, and a retaining wall is formed on the substrate on at least one side of the groove; and a semiconductor pattern on the substrate, wherein the retaining wall is arranged between the semiconductor pattern and the groove.
Correspondingly, the invention also provides a manufacturing method of the semiconductor structure, which comprises the following steps: providing a substrate, and forming a dielectric layer on the substrate; and forming a dielectric layer pattern, a groove and a retaining wall, wherein the groove is positioned in the substrate, the retaining wall is formed on the substrate on at least one side of the groove, and the retaining wall is arranged between the dielectric layer pattern and the groove.
In the semiconductor structure and the manufacturing method thereof provided by the invention, the retaining wall is formed on the substrate on at least one side of the groove, the retaining wall is arranged between the semiconductor pattern and the groove, when the photoresist is coated, the photoresist is dripped on the substrate, the photoresist is covered on the whole substrate through rotation, and the retaining wall can prevent the photoresist in the groove from overflowing outwards, so that the uniformity of the photoresist in the effective area of the chip is improved, the uniformity of subsequent etching is improved, and finally the performance of a semiconductor device is improved; meanwhile, the surface deposition and surface planarization cost can be saved, so that the production cost is reduced.
In order to make the contents of the present invention more clear and understandable, the contents of the present invention will be further described with reference to the accompanying drawings. Of course, the invention is not limited to this particular embodiment, and common alternatives known to those skilled in the art are also encompassed within the scope of the invention.
It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. In the following description, the present invention will be described in detail with reference to the drawings, which are not to be construed as limiting the invention, for the purpose of illustration and not as an actual scale.
Fig. 1 is a schematic diagram of a semiconductor structure according to an embodiment of the invention. As shown in fig. 1, the present invention provides a semiconductor structure for alleviating photoresist streaks, the semiconductor structure comprising: a substrate 10, a groove 11 is formed on the substrate 10, a retaining wall 12 is formed on the substrate 10 on at least one side of the groove 11, and a semiconductor pattern 13 is located on the substrate 10, and the retaining wall 12 is disposed between the semiconductor pattern 13 and the groove 11.
The substrate 10 may be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi) or silicon carbide (SiC), or may be Silicon On Insulator (SOI), germanium On Insulator (GOI); or may be other materials such as III-V compounds such as gallium arsenide. In this embodiment, the material of the substrate 10 is preferably monocrystalline silicon. The surface of the substrate 10 may further be formed with a semiconductor device layer (not shown), in which a plurality of semiconductor devices such as a MOS field effect transistor, a diode, or a resistor are formed, for example.
In this embodiment, the recess 11 is formed in the substrate 10, and in other embodiments, the recess 11 may be formed in various semiconductor devices or dielectric layers, insulating layers on the substrate 10. The grooves 11 are preferably deep grooves. The material of the retaining wall 11 includes a dielectric layer and/or a photoresist, i.e., the material of the retaining wall 11 includes a dielectric layer, a photoresist, or a combination of a dielectric layer and a photoresist. A retaining wall 12 is formed on the substrate 10 on at least one side of the groove 11, where the retaining wall 12 is used to block the photoresist in the groove 11 from flowing out of the groove 11 again, so as to avoid photoresist streaks on the surface of the substrate, therefore, the retaining wall 12 may be disposed around the groove 11, or the retaining wall 12 may be formed on any desired side of the groove 11, i.e. a photoresist streak appears on a certain side of the groove 11, and affects the semiconductor device, and then the retaining wall 12 may be formed to block the photoresist.
The semiconductor pattern 13 may be any desired semiconductor pattern, and the recess 11 may be any desired recess. That is, as long as the semiconductor device is formed with a groove and a photoresist streak caused by the groove exists, a retaining wall 12 can be formed on at least one side of the groove to prevent the photoresist in the groove from overflowing outwards, thereby improving the uniformity of the photoresist, improving the uniformity of subsequent etching, and finally improving the performance of the semiconductor device
In this embodiment, the distance from the retaining wall 12 to the sidewall of the groove 11 is between 0 μm and 1000 μm, for example, may be 0 μm, 10 μm, 100 μm, 1000 μm, etc., where 0 μm means that the retaining wall 12 is disposed adjacent to the groove 11. The distance between the retaining wall 12 and the sidewall of the groove 11 may be set according to practical conditions, when the semiconductor devices around the groove 11 are sparse, the distance may be appropriately increased, and when the semiconductor devices around the groove 11 are compact, the distance may be appropriately decreased, which needs to be determined according to the practical device distribution.
In the semiconductor structure provided by the invention, the retaining wall is formed on the substrate on at least one side of the groove, the retaining wall is arranged between the semiconductor pattern and the groove, when the photoresist is coated, the photoresist is dripped on the substrate, the photoresist is covered on the whole substrate through rotation, the retaining wall can prevent the photoresist in the groove from overflowing outwards, the uniformity of the photoresist in the effective area of the chip is improved, the uniformity of subsequent etching is improved, and finally the performance of a semiconductor device is improved; meanwhile, the surface deposition and surface planarization cost can be saved, so that the production cost is reduced.
Correspondingly, the invention also provides a method for manufacturing a semiconductor structure, and fig. 2 is a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the invention, as shown in fig. 2, where the method includes:
step S100: providing a substrate, and forming a dielectric layer on the substrate;
step S200: and forming a dielectric layer pattern, a groove and a retaining wall, wherein the groove is positioned in the substrate, the retaining wall is formed on the substrate on at least one side of the groove, and the retaining wall is arranged between the dielectric layer pattern and the groove.
The forming methods and the forming sequence of the dielectric layer patterns, the grooves and the retaining walls can be different, the invention is not limited to the forming methods and the forming sequence, and two methods are described in the following two embodiments.
[ embodiment one ]
Fig. 3 to 8 are schematic views illustrating steps of a method for fabricating a semiconductor structure according to a first embodiment of the present invention. The following describes the steps of the method for manufacturing a semiconductor structure according to this embodiment in detail with reference to fig. 2 and fig. 3 to 8.
In step S100, referring to fig. 2 and 3, a substrate 100 is provided, and a dielectric layer 110 is formed on the substrate 100.
The material of the substrate 100 may be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi) or silicon carbide (SiC), or may be Silicon On Insulator (SOI), germanium On Insulator (GOI); or may be other materials such as III-V compounds such as gallium arsenide. In this embodiment, the material of the substrate 100 is preferably monocrystalline silicon. The surface of the substrate 100 may further be formed with a semiconductor device layer (not shown), in which a plurality of semiconductor devices such as a MOS field effect transistor, a diode, or a resistor are formed, for example, which is not limited in the present invention.
In this embodiment, the dielectric layer 110 may be formed by a chemical vapor deposition method, and the material of the dielectric layer 110 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or the like, and in this embodiment, the material of the dielectric layer 110 is preferably silicon oxide.
In step S200, referring to fig. 2 and fig. 4 to 8, a dielectric layer pattern 130, a groove 160 and a retaining wall 140' are formed, the groove 160 is located in the substrate 100, the retaining wall 140' is formed on the substrate on at least one side of the groove 160, and the retaining wall 140' is disposed between the dielectric layer pattern 130 and the groove 160.
Specifically, in step S201, referring to fig. 4 and fig. 5, the dielectric layer 110 is etched to form a dielectric layer pattern 130 and a retaining wall 140.
Referring to fig. 4, first, a patterned first photoresist layer 120 is formed on the dielectric layer 110. Specifically, a first photoresist layer (not shown) is formed on the dielectric layer 110, and then the first photoresist layer is exposed and developed to form a patterned first photoresist layer 120. Then, the dielectric layer 110 is etched using the patterned first photoresist layer 120 as a mask until the substrate 100 is exposed, so as to form the dielectric layer pattern 130 and the barrier wall 140. The dielectric layer pattern 130 is an arbitrary pattern required for the semiconductor device, and the barrier wall 140 is formed on the substrate 100 on at least one side of the predetermined recess region for blocking the subsequent photoresist. The retaining wall 140 and the dielectric layer pattern 130 are formed in the same process step, and the production cost is not increased. In other embodiments, the retaining wall 140 may be formed during the process of forming the pattern of other materials, which is not limited to the dielectric layer, and may be determined according to the actual manufacturing steps of the semiconductor device. Finally, the patterned first photoresist layer 120 is removed, and the structure shown in fig. 5 is formed.
In this embodiment, after forming the dielectric layer pattern 130 and the retaining wall 140, the method further includes: etching the retaining wall 140, so that a side of the retaining wall 140' close to the groove after etching presents an inclined surface, and a side of the inclined surface away from the substrate 100 inclines toward the groove, as shown in fig. 6. The side of the inclined surface away from the substrate 100 is close to the recess (formed in step S300, specifically, the region where the recess is formed is predetermined), and the side of the inclined surface close to the substrate 100 is far away from the recess, i.e., the side of the retaining wall 140' close to the recess forms an acute angle with the substrate 100, so as to better block the subsequent photoresist.
In step S202, referring to fig. 7 and 8, the substrate 100 is etched to form a recess 160, the retaining wall 140 'is formed on the substrate 100 on at least one side of the recess 160, and the retaining wall 140' is disposed between the dielectric layer pattern 130 and the recess 160.
First, as shown in fig. 7, a patterned second photoresist layer 150 is formed on the substrate 100, and the patterned second photoresist layer 150 covers the substrate 100, the dielectric layer pattern 130 and the barrier wall 140'. Specifically, a second photoresist layer (not shown) is formed on the substrate 100, the second photoresist layer covers the substrate 100, the dielectric layer pattern 130 and the barrier wall 140', and then the second photoresist layer is exposed and developed to form a patterned second photoresist layer 150. The substrate 100 is then etched using the patterned second photoresist layer 150 as a mask to form the recess 160 in the substrate 100. Finally, the patterned second photoresist layer 150 is removed, forming the structure shown in fig. 8.
It should be noted that, after forming the dielectric layer pattern 130 and the retaining wall 140', before forming the groove 160, or after forming the groove 160, the method further includes: a semiconductor pattern 170 is formed on the dielectric layer pattern 130. The semiconductor pattern 170 is an arbitrary pattern required for a semiconductor device, and the barrier wall 140' is provided between the semiconductor pattern 170 and the groove 160 in order to prevent formation of a photoresist streak on the substrate 100 between the semiconductor pattern 170 and the groove 160, which affects the performance of the final semiconductor device. The retaining walls 140' may be disposed around the grooves 160, or the retaining walls 140' may be formed on any desired side of the grooves 160, i.e., a photoresist streak appears on a certain side of the grooves 160 and affects the semiconductor device, so that the retaining walls 140' may be formed to block the photoresist.
In this embodiment, after the blocking wall 140' performs the function of blocking light, the blocking wall may be removed or may remain. If the retaining wall 140 'does not affect the subsequent process and the final semiconductor device, the retaining wall 140' may not be removed, and if the effect is caused, the retaining wall 140 'needs to be removed, and whether to remove the retaining wall 140' is determined according to the actual situation, which is not limited in the present invention.
According to the manufacturing method of the semiconductor structure, the retaining wall is formed on the substrate on at least one side of the groove, the retaining wall is arranged between the semiconductor pattern and the groove, when the photoresist is coated, the photoresist is dripped on the substrate, the photoresist is covered on the whole substrate through rotation, the retaining wall can prevent the photoresist in the groove from overflowing outwards, the uniformity of the photoresist in the effective area of the chip is improved, the uniformity of subsequent etching is improved, and finally the performance of the semiconductor device is improved; meanwhile, the surface deposition and surface planarization cost can be saved, so that the production cost is reduced.
[ example two ]
Fig. 9 to 15 are schematic views illustrating the steps of a method for fabricating a semiconductor structure according to a second embodiment of the present invention. The following describes the steps of the method for manufacturing a semiconductor structure in this embodiment in detail with reference to fig. 2 and fig. 9 to 15.
In step S100, referring to fig. 2 and 9, a substrate 200 is provided, and a dielectric layer 210 is formed on the substrate 200.
The material of the substrate 200 may be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi) or silicon carbide (SiC), or may be Silicon On Insulator (SOI), germanium On Insulator (GOI); or may be other materials such as III-V compounds such as gallium arsenide. In this embodiment, the material of the substrate 200 is preferably monocrystalline silicon. The surface of the substrate 200 may further be formed with a semiconductor device layer (not shown), in which a plurality of semiconductor devices such as a MOS field effect transistor, a diode, or a resistor are formed, for example, which is not limited in the present invention.
In this embodiment, the dielectric layer 210 may be formed by a chemical vapor deposition method, and the material of the dielectric layer 210 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or the like, and in this embodiment, the material of the dielectric layer 210 is preferably silicon oxide.
In step S200, referring to fig. 2 and fig. 10 to fig. 15, a dielectric layer pattern 230, a groove 250 and a retaining wall 260 are formed, the groove 250 is located in the substrate 100, the retaining wall 260 is formed on the substrate on at least one side of the groove 250, and the retaining wall 260 is disposed between the dielectric layer pattern 230 and the groove 250.
Specifically, in step S201, referring to fig. 10 and 11, the dielectric layer 210 is etched to form a dielectric layer pattern 230.
Referring to fig. 10, first, a patterned first photoresist layer 220 is formed on the dielectric layer 210. Specifically, a first photoresist layer (not shown) is formed on the dielectric layer 210, and then the first photoresist layer is exposed and developed to form a patterned first photoresist layer 220. The dielectric layer 210 is then etched using the patterned first photoresist layer 220 as a mask until the substrate 200 is exposed, thereby forming the dielectric layer pattern 230. The dielectric layer pattern 230 is any pattern required for the semiconductor device, and finally, the patterned first photoresist layer 220 is removed to form the structure shown in fig. 11.
In step S202, referring to fig. 12 and 13, the substrate 200 is etched to form a recess 250.
Referring to fig. 12, first, a patterned second photoresist layer 240 is formed on the dielectric layer 210, and the second photoresist layer 240 covers the substrate 200 and the dielectric layer pattern 230. Specifically, a second photoresist layer (not shown) is formed on the dielectric layer 210, and then the second photoresist layer is exposed and developed to form a patterned second photoresist layer 240. Then, the patterned second photoresist layer 240 is used as a mask to etch the substrate 200 to form a recess 250, wherein the recess 250 is also any recess required for the semiconductor device, and finally, the patterned second photoresist layer 240 is removed to form the structure shown in fig. 13.
In step S203, referring to fig. 14, a photoresist layer is formed, a retaining wall 260 is patterned, the retaining wall 260 is formed on the substrate 200 on at least one side of the groove 250, and the retaining wall 260 is disposed between the dielectric layer pattern 230 and the groove 250.
First, a third photoresist layer (not shown) is formed on the substrate 200, wherein the third photoresist layer covers the substrate 200 and the dielectric layer pattern 230 and fills the recess 250. Then, the third photoresist layer is patterned, i.e. exposed and developed, to form the barrier 260. The retaining wall 260 has a structure with a wide top and a narrow bottom, so as to better block the subsequent photoresist.
It should be noted that, after forming the retaining wall 260, the method further includes: a semiconductor pattern 270 is formed on the dielectric layer pattern 230 as shown in fig. 15. The semiconductor pattern 270 is an arbitrary pattern required for a semiconductor device, and the barrier wall 260 is provided between the semiconductor pattern 270 and the groove 250 in order to prevent formation of a photoresist streak on the substrate 200 between the semiconductor pattern 270 and the groove 250, which may affect the performance of the final semiconductor device. The retaining walls 260 may be disposed around the grooves 250, or the retaining walls 260 may be formed on any desired side of the grooves 250, that is, a photoresist streak may occur on a certain side of the grooves 250 and affect the semiconductor device, so that the retaining walls 260 may be formed to block the photoresist.
In this embodiment, after the blocking wall 260 performs the light blocking function, the blocking wall 260 may be removed, for example, the blocking wall 260 may be removed at the same time as the semiconductor pattern 270 is formed.
According to the manufacturing method of the semiconductor structure, the retaining wall is formed on the substrate on at least one side of the groove, the retaining wall is arranged between the semiconductor pattern and the groove, when the photoresist is coated, the photoresist is dripped on the substrate, the photoresist is covered on the whole substrate through rotation, the retaining wall can prevent the photoresist in the groove from overflowing outwards, the uniformity of the photoresist in the effective area of the chip is improved, the uniformity of subsequent etching is improved, and finally the performance of the semiconductor device is improved; meanwhile, the surface deposition and surface planarization cost can be saved, so that the production cost is reduced.
In the above embodiments, the grooves are formed in the substrate, and in other embodiments, the grooves may also be formed in various semiconductor devices or dielectric layers, insulating layers on the substrate. Namely, as long as the grooves are formed and photoresist streaks caused by the grooves exist, retaining walls can be formed on at least one side of the grooves so as to prevent the photoresist in the grooves from overflowing outwards, thereby improving the uniformity of the photoresist, improving the uniformity of subsequent etching and finally improving the performance of the semiconductor device.
In summary, in the semiconductor structure and the manufacturing method thereof provided by the invention, the retaining wall is formed on the substrate on at least one side of the groove, the retaining wall is arranged between the semiconductor pattern and the groove, when the photoresist is coated, the photoresist is dripped on the substrate, the photoresist is covered on the whole substrate by rotating, the retaining wall can prevent the photoresist in the groove from overflowing outwards, the uniformity of the photoresist in the effective area of the chip is improved, the uniformity of subsequent etching is improved, and finally the performance of the semiconductor device is improved; meanwhile, the surface deposition and surface planarization cost can be saved, so that the production cost is reduced.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (9)
1. A semiconductor structure, comprising:
a substrate, wherein a groove is formed on the substrate, and a retaining wall is formed on the substrate on at least one side of the groove; the method comprises the steps of,
the semiconductor pattern is positioned on the substrate, the retaining wall is arranged between the semiconductor pattern and the groove, the retaining wall can prevent photoresist in the groove from overflowing outwards, and the retaining wall is used for preventing photoresist streaks from being formed on the substrate between the semiconductor pattern and the groove; and the retaining wall is of a structure with a wide upper part and a narrow lower part.
2. The semiconductor structure of claim 1, wherein the retaining wall comprises a dielectric layer and/or a photoresist.
3. A method of fabricating a semiconductor structure, comprising:
providing a substrate, and forming a dielectric layer on the substrate; the method comprises the steps of,
forming a dielectric layer pattern, a groove and a retaining wall, wherein the groove is positioned in the substrate, the retaining wall is formed on the substrate on at least one side of the groove, the retaining wall is arranged between the dielectric layer pattern and the groove, the retaining wall can prevent photoresist positioned in the groove from overflowing outwards, and the retaining wall is used for preventing photoresist streaks from being formed on the substrate between the dielectric layer pattern and the groove; and the retaining wall is of a structure with a wide upper part and a narrow lower part.
4. The method of fabricating a semiconductor structure of claim 3, wherein the step of forming the dielectric layer pattern, the recess, and the retaining wall comprises:
etching the dielectric layer to form a dielectric layer pattern and a retaining wall; the method comprises the steps of,
the substrate is etched to form a recess.
5. The method of manufacturing a semiconductor structure according to claim 4, wherein after forming the dielectric layer pattern and the retaining wall, before forming the recess, or after forming the recess, further comprising: and forming a semiconductor pattern on the dielectric layer pattern.
6. The method of manufacturing a semiconductor structure according to claim 4, further comprising, after forming the dielectric layer pattern and the retaining wall, before forming the recess: etching the retaining wall to enable one side of the retaining wall, which is close to the groove, to be an inclined surface, and enabling one side, which is far away from the substrate, of the inclined surface to be inclined towards the groove.
7. The method of fabricating a semiconductor structure of claim 4, wherein forming the dielectric layer and the retaining wall comprises:
forming a patterned first photoresist layer on the dielectric layer;
etching the dielectric layer by taking the patterned first photoresist layer as a mask until the substrate is exposed, so as to form the dielectric layer pattern and the retaining wall; the method comprises the steps of,
and removing the patterned first photoresist layer.
8. The method of fabricating a semiconductor structure of claim 7, wherein the method of forming the recess comprises:
forming a patterned second photoresist layer on the substrate, wherein the patterned second photoresist layer covers the substrate, the dielectric layer pattern and the retaining wall;
etching the substrate by taking the patterned second photoresist layer as a mask to form the groove; the method comprises the steps of,
and removing the patterned second photoresist layer.
9. The method of fabricating a semiconductor structure of claim 3, wherein the step of forming the dielectric layer pattern, the recess, and the retaining wall comprises:
etching the dielectric layer to form a dielectric layer pattern;
etching the substrate to form a groove; the method comprises the steps of,
forming a photoresist layer and patterning to form a retaining wall.
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