CN110246453B - Display device and display driving circuit thereof - Google Patents
Display device and display driving circuit thereof Download PDFInfo
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- CN110246453B CN110246453B CN201910513927.8A CN201910513927A CN110246453B CN 110246453 B CN110246453 B CN 110246453B CN 201910513927 A CN201910513927 A CN 201910513927A CN 110246453 B CN110246453 B CN 110246453B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3275—Details of drivers for data electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
- G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/06—Adjustment of display parameters
- G09G2320/0673—Adjustment of display parameters for control of gamma adjustment, e.g. selecting another gamma curve
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- Engineering & Computer Science (AREA)
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Abstract
The invention provides a display device and a display driving circuit thereof. The display device includes a display panel and a display driving circuit. The display panel comprises a plurality of power supply wires and a plurality of pixel units. The pixel units are respectively coupled to a power voltage of the display panel through the power traces. The display driving circuit is coupled to the display panel and used for generating a plurality of data driving voltages to drive the pixel units respectively. The display driving circuit comprises a gamma voltage generating circuit and a data line driving circuit. The gamma voltage generating circuit is coupled to the power voltage for generating a plurality of compensated gamma voltages according to the variation of the power voltage and the reference voltage set. The data line driving circuit is coupled with the gamma voltage generating circuit to receive the compensated gamma voltages and generate and adjust the data driving voltages according to the compensated gamma voltages and the gray scale image data.
Description
Technical Field
The present invention relates to a display technology, and more particularly, to a display device and a display driving circuit thereof capable of compensating a display screen in real time according to a change in a power supply voltage.
Background
With the development of the semiconductor industry and the optoelectronic industry, Light Emitting Diodes (LEDs) are widely used not only for illumination purposes but also in the field of displays. Among them, an Organic-light emitting diode (OLED) display is considered as one of the mainstream displays because of its characteristics of thin thickness, high efficiency, high contrast, no viewing angle limitation, and fast response speed.
In the oled display, a power management integrated circuit is usually disposed, wherein the power management integrated circuit can be coupled to the oled display panel through a power trace of the interposer and the flexible printed circuit board to provide a power voltage required by the oled display panel to display a picture. However, the power traces of the interposer and the flexible printed circuit board usually have parasitic resistances, and a voltage drop is generated when the current flows through the parasitic resistances, so that a voltage difference exists between the power voltage received by the oled display panel and the power voltage provided by the power management ic. In addition, the parasitic resistances of the power supply wires of different adapter plates and flexible printed circuit boards are different. Therefore, under the condition of matching different adapter plates and flexible printed circuit boards, the brightness of the display picture of the organic light-emitting diode display panel is different.
In addition, the oled display panel itself usually has parasitic coupling capacitance between the power voltage trace and the data trace. When the driving voltage on the data wire changes, the voltage on the power voltage wire changes along with the driving voltage through the coupling capacitor, thereby affecting the color accuracy of the display picture.
In order to solve the above problem, the variation of the power voltage may be converted into digital data by analog-to-digital conversion, and the gray scale image data provided to the display driving circuit is adjusted according to the converted digital data, so that the display driving circuit adjusts the brightness and color of the display image according to the adjusted gray scale image data. However, the digital data after analog-to-digital conversion usually has an error in resolution, so that the adjusted brightness and color of the display screen are still not accurate enough. In addition, the compensation method for adjusting the gray scale image data according to the digital data can only compensate the image of the next pixel row or the image of the next display image in sequence, and cannot achieve the effect of compensating the display image in real time.
Disclosure of Invention
In view of the above, the present invention provides a display device and a display driving circuit thereof, which can compensate a display image in real time according to a change of a power voltage, thereby improving the accuracy of the brightness and color of the display image.
The display device of the invention comprises a display panel and a display driving circuit. The display panel comprises a plurality of power supply wires and a plurality of pixel units. The pixel units are respectively coupled to a power voltage of the display panel through the power traces. The display driving circuit is coupled to the display panel and used for generating a plurality of data driving voltages to drive the pixel units respectively. The display driving circuit comprises a gamma voltage generating circuit and a data line driving circuit. The gamma voltage generating circuit is coupled to the power voltage for generating a plurality of compensated gamma voltages according to the variation of the power voltage and the reference voltage set. The data line driving circuit is coupled with the gamma voltage generating circuit to receive the compensated gamma voltages and generate and adjust the data driving voltages according to the compensated gamma voltages and the gray scale image data.
The display driving circuit of the invention is used for generating a plurality of data driving voltages to drive the display panel. The display driving circuit comprises a gamma voltage generating circuit and a data line driving circuit. The gamma voltage generating circuit is used for receiving the power supply voltage of the display panel and generating a plurality of compensated gamma voltages according to the variable quantity of the power supply voltage and the reference voltage group. The data line driving circuit is coupled with the gamma voltage generating circuit to receive the compensated gamma voltages and generate and adjust the data driving voltages according to the compensated gamma voltages and the gray scale image data.
In an embodiment of the invention, the variation of the power voltage includes a fixed dc voltage drop difference generated by a parasitic resistance of a power trace between the power circuit and the display panel, and a dynamic ac voltage difference generated by a coupling effect of a parasitic capacitance between the power trace and the data trace in the display panel.
In view of the above, in the display device and the display driving circuit thereof provided by the present invention, the gamma voltage generating circuit can dynamically generate the compensated gamma voltage according to the received power voltage variation and the reference voltage set, and the data line driving circuit can generate and adjust the data driving voltage according to the compensated gamma voltage, so that the display driving circuit adjusts the data driving voltage by using the gamma voltage compensation method (i.e., analog method) based on the power voltage variation, thereby compensating the display frame in real time. In addition, the data driving voltage is adjusted by an analog mode, so that errors caused by digitalization of the voltage can be avoided, and the accuracy of the brightness and the color of a display picture can be effectively improved.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a block diagram of a display device according to an embodiment of the present invention;
FIG. 2 is a block diagram of a display driver circuit according to an embodiment of the present invention;
FIG. 3 is a block diagram of a gamma voltage generating circuit according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of a reference voltage compensation circuit according to an embodiment of the present invention;
FIG. 5 is a signal timing diagram illustrating the reference voltage compensation circuit of FIG. 4 according to an embodiment of the present invention;
FIG. 6 is a circuit diagram of a pixel cell according to an embodiment of the invention;
FIG. 7 is a circuit diagram of a reference voltage compensation circuit according to another embodiment of the present invention;
FIG. 8 is a signal timing diagram of the reference voltage compensation circuit of FIG. 7 according to an embodiment of the present invention.
Description of the reference numerals
100: display device
120: display panel
140: display driving circuit
190: power supply circuit
242: gamma voltage generating circuit
244: data line driving circuit
246: detection circuit
3422: reference voltage compensation circuit
3424: gamma voltage output circuit
400. 700: reference voltage compensation circuit
410: first compensation circuit
420: second compensation circuit
710: first adder-subtractor
720: second adder-subtractor
C1, C2: capacitor with a capacitor element
CX: storage capacitor
DL: data line
EL: power supply wiring
ELVDD: original voltage
ELVDD': supply voltage
ELVSS: reference voltage
EM: control signal
Id: electric current
LD: organic light emitting diode
ND 1: first node
ND 2: second node
PA: pixel array
PDATA: gray scale picture data
PH1, PH 2: time interval
PL: power supply wiring
PX: pixel unit
R _ VG: compensation voltage group
R _ VGH: first compensated voltage
R _ VGL: second compensated voltage
SL: scanning line
SW 1-SW 4: switch with a switch body
T1-T7: transistor with a metal gate electrode
VDATA: data driving voltage
VDF: voltage difference
VG _1 to VG _ N: post-compensation gamma voltage
VINIT: reset voltage
VOS _ H, VR _ H: a first reference voltage
VOS _ L, VR _ L: second reference voltage
VR: reference voltage set
VSCAN, VSCAN [ n ], VSCAN [ n-1 ]: scanning driving voltage
VSET: set voltage
Detailed Description
In order that the present disclosure may be more readily understood, the following specific examples are given as illustrative of the invention which may be practiced in various ways. Further, wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Fig. 1 is a block diagram of a display device according to an embodiment of the invention. Please refer to fig. 1. The display device 100 includes a display panel 120 and a display driving circuit 140, but the invention is not limited thereto. In other embodiments of the present invention, the display device 100 may further include a power circuit 190.
The power circuit 190 is coupled to the display panel 120 through the power trace EL for generating the original voltage ELVDD, wherein the original voltage ELVDD is transmitted to the display panel 120 through the power trace EL to provide the power voltage ELVDD'. The power supply line EL has a parasitic resistance. Therefore, when the output current of the power circuit 190 flows through the power trace EL, a voltage drop is generated across the power trace EL, so that the power voltage ELVDD' at the end of the display panel 120 is smaller than the original voltage ELVDD generated by the power circuit 190.
The display panel 120 may be, for example, an organic light emitting diode display panel, but the present invention is not limited thereto. The display panel 120 includes a plurality of scan lines SL, a plurality of data lines DL, a plurality of power lines PL, and a pixel array PA. The pixel array PA includes a plurality of pixel units PX arranged in an array. The power source terminal of each pixel unit PX is coupled to the power source voltage ELVDD' through the corresponding power trace PL. Each pixel unit PX is coupled to a corresponding scan line SL and a corresponding data line DL.
The display driving circuit 140 is disposed in the non-display region of the display panel 120. The display driving circuit 140 is coupled to the scan lines SL, the data lines DL and the power voltage ELVDD' of the display panel 120. The display driving circuit 140 can generate a plurality of scan driving voltages VSCAN to the scan lines SL of the display panel 120, and can generate a plurality of data driving voltages VDATA to the data lines DL to respectively drive the pixel units PX in the pixel array PA.
FIG. 2 is a block diagram of a display driving circuit according to an embodiment of the invention. Please refer to fig. 1 and fig. 2. The display driving circuit 140 may include a gamma voltage generating circuit 242 and a data line driving circuit 244, but the invention is not limited thereto. The gamma voltage generating circuit 242 is coupled to the power voltage ELVDD 'and is configured to generate a plurality of compensated gamma voltages VG _1 through VG _ N according to the variation of the power voltage ELVDD' and the reference voltage group VR. The data line driving circuit 244 is coupled to the gamma voltage generating circuit 242 for receiving the compensated gamma voltages VG _1 to VG _ N, and generating and adjusting the data driving voltage VDATA according to the compensated gamma voltages VG _1 to VG _ N and the gray scale image data PDATA.
Since the gamma voltage generating circuit 242 dynamically generates the compensated gamma voltages VG _ 1-VG _ N according to the variation of the power voltage ELVDD ' and the reference voltage group VR, and the data line driving circuit 244 generates and adjusts the data driving voltage VDATA according to the compensated gamma voltages VG _ 1-VG _ N, the display driving circuit 140 adjusts the data driving voltage VDATA in a gamma voltage compensation manner (i.e., an analog manner) based on the variation of the power voltage ELVDD ', so that the data driving voltage VDATA varies with the power voltage ELVDD ', thereby compensating the display frame in real time. In addition, the data driving voltage VDATA is adjusted in an analog manner, so that errors caused by digitalization of the voltage can be avoided, and the accuracy of the brightness and the color of a display picture can be effectively improved.
In an embodiment of the invention, the variation of the power supply voltage ELVDD' mentioned in the present invention may include a fixed variation and a dynamic variation, wherein the fixed variation may be, for example, a fixed dc voltage drop difference generated by a parasitic resistance of the power trace EL between the power circuit 190 and the display panel 120, and the dynamic variation may be, for example, a dynamic ac voltage difference generated by a coupling effect of a parasitic capacitance between the power trace PL and the data line DL in the display panel 120, but the present invention is not limited thereto.
In an embodiment of the invention, a feedback control mechanism is provided between the display driving circuit 140 and the power supply circuit 190 of fig. 1, and the display driving circuit 140 can feed back the detected variation of the power supply voltage ELVDD 'to the power supply circuit 190, so that the power supply circuit 190 adjusts the original voltage ELVDD, thereby compensating the power supply voltage ELVDD' of the display panel 120 in real time.
In an embodiment of the invention, the variation of the power supply voltage ELVDD 'fed back to the power supply circuit 190 may be, for example, a fixed dc voltage drop difference between the power supply voltage ELVDD' and the original voltage ELVDD (i.e., the above-mentioned fixed variation), but the invention is not limited thereto.
In an embodiment of the invention, the display driving circuit 140 may further include a detection circuit 246. The detection circuit 246 is coupled to the power voltage ELVDD' and a set voltage VSET, wherein the set voltage VSET is equal to the original voltage ELVDD before the adjustment. The detection circuit 246 can detect a voltage difference VDF (i.e., the above-mentioned fixed variation) between the power voltage ELVDD' and the set voltage VSET. The detection circuit 246 can feed back the voltage difference VDF to the power circuit 190, so that the power circuit 190 adjusts the original voltage ELVDD accordingly, so that the power voltage ELVDD' at the display panel 120 is equal to the set voltage VSET (i.e., the original voltage ELVDD before adjustment). In another embodiment, the detection circuit 246 may be part of the power supply circuit 190.
In an embodiment of the present invention, the data line driving circuit 244 can be implemented by a conventional data line driver, and the implementation details and related operations thereof are well known to those skilled in the art, and therefore, are not described herein again.
In another embodiment of the present invention, the display driving circuit 140 may further include a timing control circuit and a scan line driving circuit, but the present invention is not limited thereto. The timing control circuit and the scan line driving circuit can be implemented by using a conventional timing controller and a conventional scan line driver, respectively, and the implementation details and related operations thereof are well known to those skilled in the art, and thus are not described herein again.
Fig. 3 is a block diagram of a gamma voltage generating circuit according to an embodiment of the invention. Please refer to fig. 1-3. The gamma voltage generating circuit 242 may include a reference voltage compensation circuit 3422 and a gamma voltage output circuit 3424. The reference voltage compensation circuit 3422 is coupled to the power supply voltage ELVDD ', and is configured to track a dynamic variation of the power supply voltage ELVDD ' and generate a compensation voltage set R _ VG according to the dynamic variation of the power supply voltage ELVDD ' and the reference voltage set VR. The gamma voltage output circuit 3424 is coupled to the reference voltage compensation circuit 3422 for receiving the compensation voltage set R _ VG and dividing the compensation voltage set R _ VG to generate a plurality of compensated gamma voltages VG _ 1-VG _ N.
In an embodiment of the invention, the gamma voltage output circuit 3424 can be implemented by a voltage divider circuit, such as a resistive voltage divider circuit or other voltage divider circuits, but the invention is not limited thereto.
FIG. 4 is a circuit diagram of a reference voltage compensation circuit according to an embodiment of the invention. Please refer to fig. 3 and fig. 4. In this embodiment, the reference voltage group VR includes a first reference voltage VR _ H and a second reference voltage VR _ L, and the compensation voltage group R _ VG includes a first compensated voltage R _ VGH and a second compensated voltage R _ VGL. The reference voltage compensation circuit 400 includes a first compensation circuit 410 and a second compensation circuit 420.
The first compensation circuit 410 includes switches SW 1-SW 2 and a capacitor C1. A first terminal of the switch SW1 receives the first reference voltage VR _ H. The second terminal of the switch SW1 is coupled to the first node ND 1. A first terminal of the switch SW2 receives the power supply voltage ELVDD'. The capacitor C1 is coupled between the first node ND1 and the second terminal of the switch SW 2. The first node ND1 outputs a first compensated voltage R _ VGH.
The second compensation circuit 420 includes switches SW 3-SW 4 and a capacitor C2. A first terminal of the switch SW3 receives the second reference voltage VR _ L. A second terminal of the switch SW3 is coupled to the second node ND 2. A first terminal of the switch SW4 receives the power supply voltage ELVDD'. The capacitor C2 is coupled between the second node ND2 and the second terminal of the switch SW 4. The second node ND2 outputs a second compensated voltage R _ VGL.
FIG. 5 is a signal timing diagram illustrating the reference voltage compensation circuit of FIG. 4 according to an embodiment of the present invention. Please refer to fig. 4 and 5. During the time interval PH1, the switches SW1 and SW2 are turned on, so the capacitor C1 is charged, and the voltage at the first node ND1 is the first reference voltage VR _ H. Similarly, during the time interval PH1, the switches SW3 and SW4 are turned on, so the capacitor C2 is charged, and the voltage at the second node ND2 is the second reference voltage VR _ L.
Then, during the time interval PH2, the switch SW1 is turned off and the switch SW2 is turned on, so that the dynamic variation of the power voltage ELVDD 'can be coupled to the first node ND1 through the capacitor C1, such that the voltage at the first node ND1 is the sum of the first reference voltage VR _ H and the dynamic variation of the power voltage ELVDD' and serves as the first compensated voltage R _ VGH. In other words, the dynamic variation of the power supply voltage ELVDD' may be reflected in the first compensated voltage R _ VGH in real time.
Similarly, during the time interval PH2, the switch SW3 is turned off and the switch SW4 is turned on, so that the dynamic variation of the power voltage ELVDD 'can be coupled to the second node ND2 through the capacitor C2, such that the voltage at the second node ND2 is the sum of the dynamic variation of the power voltage ELVDD' and the second reference voltage VR _ L, and is used as the second compensated voltage R _ VGL. In other words, the dynamic variation of the power supply voltage ELVDD' may be reflected in the second compensated voltage R _ VGL immediately.
It is understood that the dynamic variation of the power voltage ELVDD ' is a voltage difference between the power voltage ELVDD ' of the time interval PH2 and the power voltage ELVDD ' of the time interval PH 1. Since the dynamic variation of the power voltage ELVDD 'can be immediately reflected in the first compensated voltage R _ VGH and the second compensated voltage R _ VGL, and the gamma voltage output circuit 3424 of fig. 3 divides the first compensated voltage R _ VGH and the second compensated voltage R _ VGL to generate the compensated gamma voltages VG _1 to VG _ N, and the data line driving circuit 244 of fig. 2 generates the data driving voltage VDATA according to the compensated gamma voltages VG _1 to VG _ N, the dynamic variation of the power voltage ELVDD' can be immediately reflected in the compensated gamma voltages VG _1 to VG _ N and the data driving voltage VDATA.
In an embodiment of the invention, the time Interval PH1 shown in fig. 5 may be, for example, a blank Interval (Blanking Interval) time Interval, and the time Interval PH2 may be, for example, a Display Interval (Display Interval) time Interval, but the invention is not limited thereto, wherein the time Interval PH1 may be, for example, a Vertical Blanking Interval (Vertical Blanking Interval) or a Horizontal Blanking Interval (Horizontal Blanking Interval). In this way, the reference voltage compensation circuit 400 can provide the first reference voltage VR _ H and the second reference voltage VR _ L to the first node ND1 and the second node ND2 respectively during the blank time interval, and instantly reflect the dynamic variation of the power voltage ELVDD' to the first node ND1 and the second node ND2 during the frame display time interval to serve as the first compensated voltage R _ VGH and the second compensated voltage R _ VGL respectively. In this way, in the frame display time interval, the dynamic variation of the power voltage ELVDD' can be immediately reflected in the compensated gamma voltages VG _ 1-VG _ N and the data driving voltage VDATA of fig. 2, so as to compensate the display frame in real time.
Fig. 6 is a circuit diagram of a pixel unit according to an embodiment of the invention. Please refer to fig. 6. The pixel unit PX includes transistors T1-T7, a storage capacitor CX, and an organic light emitting diode LD, i.e., the pixel unit PX has a circuit structure of 7T1C, but the invention is not limited thereto. In other embodiments of the present invention, the pixel unit PX may also be implemented by using a known circuit architecture such as 2T1C, 5T2C, or 6T 1C. The first terminal of the storage capacitor CX receives the power supply voltage ELVDD'. The first terminal of the transistor T1 is coupled to the second terminal of the storage capacitor CX. The second terminal of the transistor T1 is coupled to the reset voltage VINIT. The control terminal of the transistor T1 receives the scan driving voltage VSCAN n-1. A first terminal of the transistor T2 is coupled to a first terminal of the storage capacitor CX. The control terminal of the transistor T2 receives the control signal EM. The first terminal of the transistor T3 is coupled to the second terminal of the storage capacitor CX. The control terminal of the transistor T3 receives the scan driving voltage VSCAN [ n ]. The first terminal of the transistor T4 is coupled to the second terminal of the transistor T2. The second terminal of the transistor T4 is coupled to the second terminal of the transistor T3. The control terminal of the transistor T4 is coupled to the second terminal of the storage capacitor CX. The first terminal of the transistor T5 is coupled to the second terminal of the transistor T4. The control terminal of the transistor T5 receives the control signal EM. The second terminal of the transistor T5 is coupled to the anode terminal of the organic light emitting diode LD. A first terminal of the transistor T6 is coupled to a first terminal of the transistor T4. The second terminal of the transistor T6 receives the data driving voltage VDATA. The control terminal of the transistor T6 receives the scan driving voltage VSCAN [ n ]. A first terminal of the transistor T7 is coupled to the reset voltage VINIT. The second terminal of the transistor T7 is coupled to the anode terminal of the organic light emitting diode LD. The control terminal of the transistor T7 receives the scan driving voltage VSCAN n-1. The cathode terminal of the organic light emitting diode LD is coupled to a reference voltage ELVSS.
In a driving period of the pixel unit PX, the transistors T1 and T7 may be turned on first to reset the control terminal of the transistor T4, the second terminal of the storage capacitor CX, and the organic light emitting diode LD. Then, the transistors T1 and T7 may be turned off and the transistors T3 and T6 may be turned on, so that the data driving voltage VDATA is transmitted to the control terminal of the transistor T4 and the second terminal of the storage capacitor CX through the transistors T6, T4 and T3. Thereafter, the transistors T3 and T6 may be turned off and the transistors T2 and T5 may be turned on to transmit the power supply voltage ELVDD' to the first terminal of the transistor T4.
According to the characteristics of the transistor, the current Id of the transistor T4 (i.e. the current flowing into the organic light emitting diode LD) is proportional to the following formula (1), where VTH is the threshold voltage of the transistor T4. In addition, the luminance of the organic light emitting diode LD is proportional to the current Id. Therefore, when the power voltage ELVDD 'changes, the compensated gamma voltage is generated according to the change of the power voltage ELVDD' to correspondingly adjust the data driving voltage VDATA, so as to adjust the brightness of the organic light emitting diode LD to the correct brightness.
(ELVDD'-VDATA-VTH)2Formula (1)
FIG. 7 is a circuit diagram of a reference voltage compensation circuit according to another embodiment of the present invention, and FIG. 8 is a signal timing diagram of the reference voltage compensation circuit of FIG. 7 according to an embodiment of the present invention. Please refer to fig. 3, fig. 7 and fig. 8. In the embodiment, the reference voltage set VR includes a first reference voltage VOS _ H and a second reference voltage VOS _ L, and the compensation voltage set R _ VG includes a first compensated voltage R _ VGH and a second compensated voltage R _ VGL, wherein the first reference voltage VOS _ H and the second reference voltage VOS _ L can be set according to practical applications or design requirements.
The reference voltage compensation circuit 700 includes a first adder-subtractor 710 and a second adder-subtractor 720. A first input terminal of the first adder-subtractor 710 receives the power supply voltage ELVDD'. A second input terminal of the first adder-subtractor 710 receives the first reference voltage VOS _ H. The output terminal of the first adder-subtractor 710 outputs a first compensated voltage R _ VGH. A first input terminal of the second adder-subtractor 720 receives the power supply voltage ELVDD'. A second input terminal of the second adder-subtractor 720 receives a second reference voltage VOS _ L. The output terminal of the second adder-subtractor 720 outputs a second compensated voltage R _ VGL.
It is noted that the voltage level of the first compensated voltage R _ VGH may be higher or lower than the voltage level of the power supply voltage ELVDD ', and the voltage level of the second compensated voltage R _ VGL may be higher or lower than the voltage level of the power supply voltage ELVDD'. In detail, when the voltage level of the required first compensated voltage R _ VGH is higher than the voltage level of the power voltage ELVDD', the first adder-subtractor 710 performs an addition operation and outputs the first compensated voltage R _ VGH. On the contrary, when the voltage level of the required first compensated voltage R _ VGH is lower than the voltage level of the power voltage ELVDD', the first adder-subtractor 710 performs a subtraction operation and outputs the first compensated voltage R _ VGH. Similarly, when the voltage level of the required second compensated voltage R _ VGL is higher than the voltage level of the power supply voltage ELVDD', the second adder-subtractor 720 performs an addition operation and outputs the second compensated voltage R _ VGL. On the contrary, when the voltage level of the required second compensated voltage R _ VGL is lower than the voltage level of the power voltage ELVDD', the second adder-subtractor 720 performs a subtraction operation and outputs the second compensated voltage R _ VGL, but the invention is not limited thereto.
It is understood that when the power voltage ELVDD' rises or falls, the first compensated voltage R _ VGH and the second compensated voltage R _ VGL will also rise or fall accordingly. Therefore, the dynamic variation of the power voltage ELVDD' can be reflected in the first compensated voltage R _ VGH and the second compensated voltage R _ VGL in real time. In addition, the first reference voltage VOS _ H may be set to the voltage difference VDF of fig. 2 (i.e., the fixed amount of change of the power supply voltage ELVDD') plus the first specific voltage, and the second reference voltage VOS _ L may be set to the voltage difference VDF of fig. 2 plus the second specific voltage. In this way, the fixed variation of the power voltage ELVDD' is also reflected in the first compensated voltage R _ VGH and the second compensated voltage R _ VGL.
Since the variation (including dynamic variation and fixed variation) of the power voltage ELVDD 'can be instantly reflected in the first compensated voltage R _ VGH and the second compensated voltage R _ VGL, and the gamma voltage output circuit 3424 of fig. 3 divides the first compensated voltage R _ VGH and the second compensated voltage R _ VGL to generate the compensated gamma voltages VG _1 to VG _ N, and the data line driving circuit 244 of fig. 2 generates the data driving voltage VDATA according to the compensated gamma voltages VG _1 to VG _ N, the variation of the power voltage ELVDD' can be instantly reflected in the compensated gamma voltages VG _1 to VG _ N and the data driving voltage VDATA, thereby instantly compensating the display image.
In summary, in the display device and the display driving circuit thereof according to the embodiments of the invention, the gamma voltage generating circuit can dynamically generate the compensated gamma voltage according to the variation of the received power voltage and the reference voltage set, and the data line driving circuit can generate and adjust the data driving voltage according to the compensated gamma voltage, so that the display driving circuit adjusts the data driving voltage in a gamma voltage compensation manner (i.e., an analog manner) based on the variation of the power voltage, so that the data driving voltage VDATA is changed along with the change of the power voltage ELVDD', and the display frame can be compensated in real time. In addition, the data driving voltage is adjusted by an analog mode, so that errors caused by digitalization of the voltage can be avoided, and the accuracy of the brightness and the color of a display picture can be effectively improved. The embodiments of the present invention can also be used in combination with each other, and those skilled in the art can set the embodiments according to the actual application or design requirements.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (6)
1. A display device, comprising:
the display panel comprises a plurality of first power supply wires and a plurality of pixel units, wherein the plurality of pixel units are respectively coupled with the power supply voltage of the display panel through the plurality of first power supply wires; and
a display driving circuit, coupled to the display panel, for generating a plurality of data driving voltages to drive the plurality of pixel units, respectively, wherein the display driving circuit comprises:
the gamma voltage generating circuit is coupled with the power supply voltage and used for generating a plurality of compensated gamma voltages according to the variable quantity of the power supply voltage and a reference voltage group, wherein the reference voltage group comprises a first reference voltage and a second reference voltage; and
a data line driving circuit coupled to the gamma voltage generating circuit for receiving the compensated gamma voltages and generating and adjusting the data driving voltages according to the compensated gamma voltages and the gray scale image data,
wherein, the Gamma voltage generation circuit comprises:
a reference voltage compensation circuit coupled to the power supply voltage for tracking the variation of the power supply voltage and generating a compensation voltage set according to the variation of the power supply voltage and the reference voltage set, the compensation voltage set including a first compensated voltage and a second compensated voltage, the reference voltage compensation circuit comprising:
a first compensation circuit comprising:
a first switch, a first terminal of which receives the first reference voltage and a second terminal of which is coupled to a first node;
a second switch, a first terminal of the second switch receiving the supply voltage; and
a first capacitor coupled between the first node and a second terminal of the second switch, wherein the first node is configured to output the first compensated voltage; and
a second compensation circuit comprising:
a third switch, a first end of the third switch receiving the second reference voltage, and a second end of the third switch coupled to a second node;
a fourth switch, a first terminal of the fourth switch receiving the supply voltage; and
a second capacitor coupled between the second node and a second terminal of the fourth switch, wherein the second node is configured to output the second compensated voltage; and
and the gamma voltage output circuit is coupled with the reference voltage compensation circuit to receive the compensation voltage group and divide the compensation voltage group to generate the compensated gamma voltages.
2. The display device according to claim 1, wherein:
in a blank time interval, the first switch, the second switch, the third switch and the fourth switch are in a conducting state; and
in a frame display time interval, the second switch and the fourth switch are in an on state, and the first switch and the third switch are in an off state.
3. The display device as claimed in claim 1, wherein at least one of the compensated gamma voltages varies with the power voltage.
4. The display device according to claim 1, further comprising:
a power circuit coupled to the display panel through a second power trace and configured to generate a primitive voltage, wherein the primitive voltage is transmitted to the display panel through the second power trace to provide the power voltage,
wherein the display driving circuit feeds back at least a part of the variation of the power supply voltage to the power supply circuit, so that the power supply circuit adjusts the original voltage according to the at least a part of the variation.
5. A display driving circuit for generating a plurality of data driving voltages to drive a display panel, the display driving circuit comprising:
the gamma voltage generating circuit is used for receiving the power supply voltage of the display panel and generating a plurality of compensated gamma voltages according to the variable quantity of the power supply voltage and a reference voltage group, wherein the reference voltage group comprises a first reference voltage and a second reference voltage; and
a data line driving circuit coupled to the gamma voltage generating circuit for receiving the compensated gamma voltages and generating and adjusting the data driving voltages according to the compensated gamma voltages and the gray scale image data,
wherein the Gamma voltage generation circuit comprises:
a reference voltage compensation circuit coupled to the power supply voltage for tracking the variation of the power supply voltage and generating a compensation voltage set according to the variation of the power supply voltage and the reference voltage set, the compensation voltage set including a first compensated voltage and a second compensated voltage, the reference voltage compensation circuit comprising:
a first compensation circuit comprising:
a first switch, a first terminal of which receives the first reference voltage and a second terminal of which is coupled to a first node;
a second switch, a first terminal of the second switch receiving the supply voltage; and
a first capacitor coupled between the first node and a second terminal of the second switch, wherein the first node is configured to output the first compensated voltage; and
a second compensation circuit comprising:
a third switch, a first end of the third switch receiving the second reference voltage, and a second end of the third switch coupled to a second node;
a fourth switch, a first terminal of the fourth switch receiving the supply voltage; and
a second capacitor coupled between the second node and a second terminal of the fourth switch, wherein the second node is configured to output the second compensated voltage; and
and the gamma voltage output circuit is coupled with the reference voltage compensation circuit to receive the compensation voltage group and divide the compensation voltage group to generate the compensated gamma voltages.
6. A display device, comprising:
the display panel comprises a plurality of first power supply wires and a plurality of pixel units, wherein the plurality of pixel units are respectively coupled with the power supply voltage of the display panel through the plurality of first power supply wires; and
a display driving circuit, coupled to the display panel, for generating a plurality of data driving voltages to drive the plurality of pixel units, respectively, wherein the display driving circuit comprises:
the gamma voltage generating circuit is coupled with the power supply voltage and used for generating a plurality of compensated gamma voltages according to the variable quantity of the power supply voltage and a reference voltage group, wherein the reference voltage group comprises a first reference voltage and a second reference voltage; and
a data line driving circuit coupled to the gamma voltage generating circuit for receiving the compensated gamma voltages and generating and adjusting the data driving voltages according to the compensated gamma voltages and the gray scale image data,
wherein the Gamma voltage generation circuit comprises:
a reference voltage compensation circuit coupled to the power supply voltage for tracking the variation of the power supply voltage and generating a compensation voltage set according to the variation of the power supply voltage and the reference voltage set, the compensation voltage set including a first compensated voltage and a second compensated voltage, the reference voltage compensation circuit comprising:
a first input terminal of the first adder-subtractor receives the power supply voltage, a second input terminal of the first adder-subtractor receives the first reference voltage, and an output terminal of the first adder-subtractor outputs the first compensated voltage; and
a second adder-subtractor, a first input end of which receives the power supply voltage, a second input end of which receives the second reference voltage, and an output end of which outputs the second compensated voltage; and
and the gamma voltage output circuit is coupled with the reference voltage compensation circuit to receive the compensation voltage group and divide the compensation voltage group to generate the compensated gamma voltages.
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| TW108112708A TWI691948B (en) | 2019-04-11 | 2019-04-11 | Display apparatus and display driving circuit thereof |
| TW108112708 | 2019-04-11 |
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| CN110827757A (en) * | 2019-10-28 | 2020-02-21 | 福建华佳彩有限公司 | OLED circuit compensation method |
| WO2023092453A1 (en) * | 2021-11-26 | 2023-06-01 | 京东方科技集团股份有限公司 | Driving circuit and driving method for display panel, and display apparatus |
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| CN110246453A (en) | 2019-09-17 |
| TW202038207A (en) | 2020-10-16 |
| TWI691948B (en) | 2020-04-21 |
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