CN110244590A

CN110244590A - Multifunctional timer

Info

Publication number: CN110244590A
Application number: CN201810195580.2A
Authority: CN
Inventors: 魏寿强
Original assignee: Huada Semiconductor (chengdu) Co Ltd; Huada Semiconductor Co Ltd
Current assignee: Xiaohua Semiconductor Co ltd
Priority date: 2018-03-09
Filing date: 2018-03-09
Publication date: 2019-09-17
Anticipated expiration: 2038-03-09
Also published as: CN110244590B

Abstract

The present invention relates to a kind of Multifunctional timers, for motor control, including counter and the first trigger being connected with counter, wherein the counter includes multiple sub-count devices and multiple sub-count device multiplexers, first trigger includes that multiple PWM compare generation module, and the output of the multiple sub-count device multiplexer is respectively connected to each PWM and compares generation module.Hereby it is achieved that IO selection face is wide, PCB layout is more flexible.

Description

Multifunctional timer

Technical field

The present invention relates to Multifunctional timer (MFT), are mainly used for three-phase motor high-accuracy stable control module.Especially relate to And Multifunctional timer, by combining A/D converter (ADC) module, it is possible to provide the motor control schemes of various different applications. It can be used for occurring in emergency circumstances to stop motor driven in addition, the motor control of Multifunctional timer promptly inputs (EMI), by This realizes the protection to motor, such as overcurrent protection.

Background technique

Currently, the function of the timer of mainstream is more single on the market, for example, the work of existing timer having a single function To count with timing or for generating pulse-width signal (pwm signal).But in this field, there are a variety of demands, for example (,) it is right Counter precision also can be there are many demand, and precision prescribed is lower in some applications, and precision prescribed is higher in some applications.Therefore, User may need that low required precision can be matched, and can also match the circuit of high-precision requirement.The electricity needed due to these differences The matched I/O interface of road institute also will be different, can be with the circuit compatibility of a variety of demands by providing Multifunctional timer.

Summary of the invention

Exemplary embodiment of the present invention aim to overcome that it is in the prior art above-mentioned and/or other the problem of. The counter module of variable amount of bits can be provided in simple structure, output accuracy can be selected.

According to an aspect of the present invention, a kind of Multifunctional timer is provided, be used for motor control, including counter and with meter The first trigger that number device is connected, which is characterized in that the counter includes that multiple sub-count devices and multiple sub-count devices are more Path multiplexer, first trigger include that multiple PWM compare generation module, the multiple sub-count device multiplexer it is defeated It is respectively connected to each PWM out and compares generation module.

According to another aspect of the present invention, a kind of side that the variable amount of bits for realizing Multifunctional timer counts is provided Method is used for motor control, which includes counter and the first trigger being connected with counter, the counting Device includes counter controller, decoder, multiple sub-count devices and multiple sub-count device multiplexers, first trigger Compare generation module including multiple PWM, this method comprises the following steps: from the counter controller to the multiple sub-count Device, decoder output control signal；By the decoder according to the control signal, decoded signal is generated to determine the son of work The quantity of counter；And it is selected to be inputted according to the signal from the decoder by the sub-count device multiplexer Sub-count device output.

According to a further aspect of the present invention, a kind of storage medium is provided, be stored with execute on the computing device so as to Realize the instruction of method of the invention.

Detailed description of the invention

Fig. 1 is the schematic block diagram of Multifunctional timer according to an embodiment of the present invention.

Fig. 2 is that PWM according to an embodiment of the present invention compares the schematic block diagram that module occurs.

Fig. 3 is the schematic block diagram of ADC starting trigger module according to an embodiment of the present invention.

Fig. 4 is the situation of the counter that module linkage occurs compared with the first PWM according to an embodiment of the present invention Schematic diagram.

Fig. 5 is the situation of the counter that module linkage occurs compared with the 2nd PWM according to an embodiment of the present invention Schematic diagram.

Fig. 6 is the feelings that the counter that module links occurs compared with NPWM according to an embodiment of the present invention Shape schematic diagram.

Fig. 7 is the schematic diagram of sawtooth wave count mode according to an embodiment of the present invention.

Fig. 8 is the schematic diagram of triangular wave count mode according to an embodiment of the present invention.

Fig. 9 is the schematic block diagram of comparison output module according to an embodiment of the present invention.

Figure 10 is the output waveform example under PWM direct mode operation according to an embodiment of the present invention.

Figure 11 is the example of dead zone Timer modes waveform according to an embodiment of the present invention.

Figure 12 is the example of the dead zone Timer modes waveform of another embodiment according to the present invention.

Figure 13 is the example of dead zone timer filter patterns waveform according to an embodiment of the present invention.

Figure 14 is the example of the dead zone timer filter patterns waveform of another embodiment according to the present invention.

Specific embodiment

A specific embodiment of the invention explained below, it should be pointed out that in the specific descriptions of these embodiments In the process, in order to carry out brief and concise description, this specification can not all features to actual embodiment make in detail Most description.It is to be understood that during the actual implementation of any one embodiment, as in any one work During journey project or design object, in order to realize the objectives of developer, in order to meet, system is relevant or quotient The relevant limitation of industry can usually make various specific decisions, and this can also be implemented from a kind of embodiment to another kind It changes between mode.Moreover, it is to be understood that although effort made in this development process may be complicated And it is interminable, however for those skilled in the art relevant to present disclosure, in the disclosure The some designs carried out on the basis of the technology contents of exposure, the changes such as manufacture or production are conventional technology, no It should be understood as that content of this disclosure is insufficient.

Unless otherwise defined, technical term or scientific term used in claims and specification should be this hair The ordinary meaning that personage in bright technical field with general technical ability is understood.Present patent application specification and power " first ", " second " used in sharp claim and similar word are not offered as any sequence, quantity or importance, and It is used only to distinguish different component parts.The similar word such as "one" or " one " is not offered as quantity limitation, but indicates There are at least one.The similar word such as " comprising " or "comprising" means to appear in the element before " comprising " or "comprising" Either object covers the element for appearing in " comprising " or "comprising" presented hereinafter or object and its equivalent element, it is not excluded that Other elements or object." connection " either the similar word such as " connected " is not limited to physics or mechanical connection, It is also not necessarily limited to direct or indirect connection.

Fig. 1 is the schematic block diagram of the timer of an embodiment according to the present invention.The signal of timer shown in Fig. 1 In property block diagram, timer 1 include the counter 2 being connected with APB bus, the first trigger 11 being connect with the counter 2 and Second trigger 12.Specifically, input has signal and external timing signal EXT_CLK from APB bus in counter 2.

In addition, the first trigger 11 includes that N number of PWM compares generation module, i.e. the first PWM in timer shown in Fig. 1 Compare occur module, the 2nd PWM compare occur module ... and NPWM compares generation module.First trigger 11 Output signal be PWM1, PWM2 ..., PWMN.N represents arbitrary natural number, can be 2,3,4.....9 etc..To N's There is no particular limitation for quantity, as long as meeting the quantity of concrete application demand.

In timer shown in FIG. 1, the second trigger 12 starts trigger module and a triggering multichannel by multiple ADC Multiplexer tmux is constituted.Multiple ADC starting trigger modules are expressed as the first ADC starting trigger module, the 2nd ADC starting touching Send out module ..., NADC starting trigger module etc..Their output signal is respectively ADC_TRG.In addition, the triggering is more The output signal of path multiplexer tmux is VTRG.N represents arbitrary natural number, can be 2,3,4.....9 etc..To the number of N There is no particular limitation for amount, as long as meeting the quantity of concrete application demand.In addition, those skilled in the art will appreciate that When timer is only used as counter, it is not necessary that second trigger (i.e. ADC starts trigger module) is additionally arranged, meter can be used Cooperation between number device 2 and the first trigger (PWM, which compares, occurs module) 11 is to realize the high tally function of flexibility.

Fig. 2 is that PWM according to an embodiment of the present invention compares the schematic block diagram that module occurs.It is shown in FIG. 2 First PWM compares generation module, but those skilled in the art will appreciate that the block diagram is only schematical, and not It is only limitted to the first PWM and compares generation module.First PWM compares generation module, the 2nd PWM compares generation module, NPWM compares Module, which occurs, can have identical structure, can also have different structure, not have special restriction to their structure and relationship.

It is connected as shown in Fig. 2, PWM compares generation module with bus, and input has the output cntdata0 of counter.Tool Body, the first PWM compares generation module and includes comparison controller, reference value register, counter register and compare Output module.The output of comparison controller is separately input into the reference value register, counter register and compares output Module.In addition, the input for comparing output module is OCR0 from reference value register and OCR1, from comparison controller PCR:WMD and cntdata0 from counter register.Finally, by comparing output module output pulse width modulated signal PWM0、PWM1。

It will be appreciated by the skilled addressee that the 2nd PWM compare occur module output be PWM2, PWM3, such as it is such It pushes away, the output that NPWM compares generation module is PWM2 (N-1), PWM2N-1.

Then, referring to Fig. 3, ADC starting trigger module is illustrated.Fig. 3 is the signal of the first ADC starting trigger module Property block diagram.It will be appreciated by the skilled addressee that multiple ADC starting trigger modules can have identical structure, there is no need to one The structure of one explanation, other ADC starting trigger modules can be found in the structure of the first ADC starting trigger module.Certainly, multiple ADC Starting trigger module can also have different structure, but not do particular determination to this herein.

In fig. 3 it is shown that the first ADC starting trigger module includes: the ADC starting triggering control being connected with bus Device, multiplexer 1 (mux1), multiplexer 2 (mux2), multiplexer 3 (mux3), trigger comparator, flip-flop number Device and equivalent comparator etc..It is more that mux1, mux2, mux3 are also known as the first multiplexer, the second multiplexer and third Path multiplexer.ADC start trigger controller (ADCT register) setting setting value (AVR), first choice value (ATR.OCS), Second selective value (ATR.TRGMD), comparison control signal (compare control singal), counting controling signal (count control singal).Bus signals, ZIC [3:0] be input to ADC starting trigger controller, ADC start trigger controller to Trigger comparator exports AVR and comparison control signal, exports counting controling signal to flip-flop number, to the first multiplexing Device exports the second selective value (ATR.TRGMD), exports first choice value (ATR.OCS) to the second multiplexer, more to third Path multiplexer exports setting value (AVR).Second multiplexer starts triggering control according to benchmark value OCR0, OCR1 and ADC The first choice value (ATR.OCS) of device processed, exports the value-OCRX chosen.Equivalent comparator is according to OCRX and enumeration data Cntdata0 exports the e1 of high level, low level e1 is exported when unequal when the two is equal.Third multiplexer according to 0, AVR and e1, exports m3, and flip-flop number exports c2 in cntdata1=AVR according to counting controling signal and m3.More than first Path multiplexer input has c1, c2 and the second selective value ATR.TRGMD, according to these input and output ADC_TRG signal.

Fig. 4-6 be according to an embodiment of the present invention shown in counter schematic block diagram.It is right referring to these attached drawings Counter 2 is further detailed.Wherein, Fig. 4 be according to an embodiment of the present invention shown in compared with the first PWM send out The situation schematic diagram of the counter of raw module linkage, Fig. 5 be according to an embodiment of the present invention shown in compared with the 2nd PWM Occur module linkage counter situation schematic diagram, Fig. 6 be according to an embodiment of the present invention shown in NPWM ratio Compared with the situation schematic diagram that the counter that module links occurs.

The structure of the schematic block diagram of Fig. 4-6 is substantially similar, therefore, using Fig. 4 as representative, says to the circuit structure It is bright.

Counter 2 is connected with APB bus, specifically includes following module: counter controller, sub-count device 1, sub-count device 2 ..., sub-count device n, decoder and multiplexer (also referred to as sub-count device multiplexer).In figure, sub- control The output of device be expressed as CNTDATA11, CNTDATA2 ..., CNTDATAn, the output of decoder is set as bsel=1 ~n, i.e. bsel can be 1,2 ... or n.Finally, multiplexer exports C1, and module connection occurs compared with the first PWM It is dynamic.

Specifically, Fig. 4-6 is that there is a situation where the block diagrams of the counter of module linkage compared with, wherein 1~n is a, each Sub-count device can work independently, and joint that can also be as shown in the figure is the counter of multidigit, counter controller and APB bus Connection, counter controller setting counter control signal, CNRn.STOP, CNRn.BSEL, CNRn.CLEAR, CNRn.DCLK, CNRn.BUFEN, CNRn.CNTMD, CNRn.ECKEN, CMRn.PIM, CMRn.ZIM, CMRn.PIC, CMRn.ZIC, CNRn.ICLR, CNRn.IRQZF, CNRn.ICLREN, CNRn.IRQZEN set periodic quantity PSRn.

CNRn.BSEL by decoder can choose sub-count device work number and periodic quantity combination digit, such as when When bsel=1, a counter works, periodic quantity 8bit, as bsel=2, two sub- counter works, periodic quantity is 16bit, first sub- counter cycle are the first 8bit, and second sub- counter is the 2nd 8bit, and cntdata value (is counted Numerical value) it exports and gives oco and adct module, and so on.In addition, when the periodic quantity of word counter work is n bit, and When bsel=x, the periodic quantity of counter becomes n × x bit.User can be as needed, selects the quantity of the word counter of work.

The count value that sub-count device 1 works independently is CNTDATA11, and the count value that sub-count device 2 works independently is CNTDATA21, and so on, the count value that sub-count device n works independently is CNTDATAn1；When two counter works of selection When, it can choose the work of sub-count device 1,2, count value CNTDATA2；When selecting three counter works, son can choose Counter 1,2,3 works, count value CNTDATA3；And so on, when selecting n counter works, it can choose sub- meter Number device 1,2 ... n work, count value CNTDATAn.

The corresponding sub- counter of each multiplexer MUX works independently, and MUX1 receives the counting of sub-count device 1 Value CNTDATA11, MUX2 receive the count value CNTDATA21 of sub-count device 2, and so on, MUXn receives the meter of sub-count device n Numerical value CNTDATAn1.All MUX receive the count value of multiple sub-count devices, i.e. MUX1,2 ..., n receives CNTDATA2、CNTDATA3、…CNTDATAn。

MUX1 count value CNTDATA11, CNTDATA2, CNTDATA3 ... selected in CNTDATAn one as output C1；MUX2 count value CNTDATA21, CNTDATA2, CNTDATA3 ... selected in CNTDATAn one as output C2；With This analogizes, MUXn count value CNTDATAn1, CNTDATA2, CNTDATA3 ... selected in CNTDATAn one as output Cn。

Each output, which can correspond to, to be sent to a pwm and compares generation module, for example, output C1 is sent to the first PWM Comparing generation module, output C2 is sent to the 2nd PWM and compares generation module, and so on, output Cn is sent to N PWM and compares Module occurs.It is of course also possible to which an output correspondence is sent to multiple PWM and compares generation module.Further, it is also possible to directly will meter Numerical value CNTDATA11, CNTDATA21 ..., CNTDATAn1 be sent respectively to a PWM and compare generation module, can also will count Numerical value CNTDATA2, CNTDATA3 ... CNTDATAn is sent to PWM and compares generation module.Can also multiple output C1, C2 ... Cn, count value CNTDATA11, CNTDATA21 ..., CNTDATAn1, count value CNTDATA2, CNTDATA3 ... Several PWM that are sent to arbitrarily are selected to compare generation module in CNTDATAn.

Each output, which can correspond to, is sent to an ADC starting trigger module, for example, output C1 is sent to the first ADC Starting trigger module, output C2 is sent to the 2nd ADC starting trigger module, and so on, output Cn is sent to N ADC starting Trigger module.It is of course also possible to which an output is corresponding to be sent to multiple ADC starting trigger modules.Further, it is also possible to directly will meter Numerical value CNTDATA11, CNTDATA21 ..., CNTDATAn1 be sent respectively to ADC starting trigger module, can also will count Numerical value CNTDATA2, CNTDATA3 ... CNTDATAn is sent to ADC starting trigger module.Can also multiple output C1, C2 ... Cn, count value CNTDATA11, CNTDATA21 ..., CNTDATAn1, count value CNTDATA2, CNTDATA3 ... Several ADC that are sent to arbitrarily are selected to start trigger module in CNTDATAn.

By the way that multiple sub-count devices, decoder and sub-count device multiplexer are arranged in counter 2, it can be achieved that PWM More stable and high-precision output.In addition, above structure makes IO selection face wide, PCB layout is more flexible.

Next, discussing the operation of Multifunctional timer of the invention.It is more as involved in embodiments of the present invention Function timer have following main modular, i.e., counter, compare output module.

(1) counter (Counter)

Movement reference count unit of the counter (CNT) as the functional module of timer output MFT4.1 three-phase motor Control unit includes 1 counter unit.

(2) compare output module (Output Compare&Output)

Comparing output module (OCO) is to generate the functional module of output pwm signal on the basis of the count value of counter, The signal that output is compared generates the signal waveform of motor control.1 three-phase motor control unit includes that 3 comparison outputs are single Member.

(3) motor control promptly inputs (Emergency stop input)

Motor control promptly inputs (EMI) for occurring in emergency circumstances to stop motor driven.

In the following, being divided into counter module and comparing output module, the operation for each module is specifically described respectively.

1. the operation of counter

Firstly, discussing the operation of counter.In general, including counter control register in counter.

Counter initialization (frequency dividing ratio, count mode) need to be configured when counter stops, and can start counting later Device operates (CNR.STOP=0).

The count value and count status of counter are as the input for comparing output module (OCO).The operation of OCO and counter It is synchronous, such as register buffers operation.The operation of OCO is hereinafter described in detail.

When the count value of counter is 0x0000, zero passage detection mark (CNR.IRQZF) position set；Work as counter counts When counting to peak value when (=PSR), peak detection mark (CNR.ICLR) position set.It can set and whether lead to the interrupt signal Know CPU.The interruption (CNR.IRQZF) exported and (CNR.ICLR) conventional number can will be wished by configuring interruption masking counter It reduces.

Following table introduces the control register functions and setting timing of counter:

1 counter control register of table

Next, the count mode to counter is illustrated.Approximately, the count mode of counter can be divided into sawtooth Wave mode and triangle wave mode.Under represent the different count modes of counter.

Table 2: the count mode of counter

Sawtooth wave (incremental count) mode or triangular wave (incremental countdown) mode may be selected in count mode.Specifically Bright above-mentioned 2 kinds of count modes.

1) sawtooth wave (incremental count) mode

Fig. 7 example works as the operation under sawtooth wave (incremental count) mode setting.

Sawtooth wave counting operation and control flow are as follows:

Setting pattern CNR.CNTMD=0.

Counts peaks PSR register is set.

CNR.STOP=0 and CNR.CLEAR=1 is written, counter (CIR) is initialized to 0x0000 and starts Counting operation.

Counter Value is started counting up from 0x0000, and when reaching peak value (=PSR), count value returns 0x0000, successively weighs This multiple operation.

Count period=(PSR+1) × counted clock cycle.

In counting process, count value can be initialised to 0x0000 simultaneously by write-in CNR.STOP=0 and CNR.CLEAR=1 Continue counting operation.

Count value can be initialised to 0x0000 and stop counting behaviour by write-in CNR.STOP=1 and CNR.CLEAR=1 Make.

2) triangular wave (incremental countdown) mode

Fig. 8 example works as the operation under triangular wave (incremental countdown) mode setting.

Triangular wave counting operation and control flow are as follows:

Setting pattern CNR.CNTMD=1.

Counts peaks PSR register is set.

Counter Value does incremental count counting since 0x0000, does incremental count before reaching counts peaks；When reaching When to peak value (=PSR), counter starts to do countdown, until count value returns 0x0000；Incremental count is re-started later Operation, is repeated in this operation.

Count period=(PSR) × 2 × counted clock cycle.

In counting process, count value can be initialised to 0x0000 simultaneously by write-in CNR.STOP=0 and CNR.CLEAR=1 Incremental count operation is re-started, later repeatedly aforesaid operations.

Next, discussing another important module, that is, compare the operation of output module.

2. comparing the operation of output

The comparison of another main component as timer exports, this compares the input of output (OCO) module and counter Output be connected, next, with continued reference to Fig. 9, detailed description compares output module structurally and operationally, and Fig. 9 is more defeated The block diagram of module out.

Comparing output module includes to compare output module control register.In addition, comparing output module further includes that dead zone is posted Storage etc..Specific connection structure can be as shown in Figure 9.

Comparing output module initialization need to be configured when relatively output module stops (OCE1=OCE0=0), later It can start and compare output module.

The operation of OCO is synchronous with the counting operation of counter (CNT), if register buffers operate, exports M signal OP0/OP1 and output interrupt identification OCF1/OCF0 etc. when the value of counter is matched with the value of output comparator.

The control register functions and setting timing of output module (OCO) are compared in following table introduction:

Table 3 compares output control register

Then, discuss that exporting the channel for comparing Ch.0, Ch.1 is independently arranged condition.The output signal of channel C h.0 be OP0, The output signal of channel C h.1 is OP1.Following table 4 and 5 is the configuration contrast table of example 1-8.

Ch.0 configuration example table is compared in the output of table 4

Then, discuss that output compares the channel Ch.1 and is independently arranged condition.The following table 5 is the configuration example 5- that Ch.1 is compared in output 8。

Identical 12 place value is written to the bit [31:20] and bit [15:4] of (1) register OMR, while by OMR (1) " 0x0000 " is written in [19:16], at this time the change condition of channel C OP1 signal h.1 and OCF1 configuration is upper and OCR (0) and OCR (1) is consistent.Therefore it is unrelated with OCR (0) configuration to may be regarded as the operation of channel C h.1, this mode is called channel independent operation Mode ----channel C h (0) is determined that channel C h (1) determines configuration by OCR (1) by OCR (0).If not being able to satisfy the condition, lead to The variation of road Ch.1 will be related to OCR (0), call it as channel link operation mode.

Ch.1 configuration example table is compared in the output of table 5

Next, further, discussing channel link operation mode.

Under linked operation mode, two fiducial value OCR (0) and OCR (1) are for controlling the internal signal OP1 of Ch.1 Output.The OP0 control that Ch.0 is read under linked operation mode is invalid.

Channel C can be respectively set h.0 with the buffer register transmission time of Ch.1, for example count value can be set and be OCR (0) value of Ch.0 is transmitted when 0x0000, and OCR (1) value of Ch.1 is transmitted when counter is peak value (=PSR).

When OCR (0) is matched with Counter Value, the OCF1 interrupt identification of Ch.1 will not be generated.If you need to generate OCR (0) with Counter Value matches the OPF0 interrupt identification of lower Ch.0, and it is enabled mode of operation (OCE0=1) that channel C, which need to be arranged, h.0.If only The output for needing to generate OP1, without OP0 and OCF0, then channel C need not be arranged h.0 is enabled mode of operation (OCE0= 1).Details are referring to table 6.

Ch.0 and ch.1 linked operation pattern configurations sample table is compared in the output of table 6

Below, direct mode operation is discussed, that is, directly export the mode of OP (0) and OP (1).Specifically, pwm signal includes OP (0) and OP (1), under direct mode operation, directly to node A or B output OP (0) and OP (1).

It is as described below that PWM exports direct mode operation (PCR:WMD [1:0]=00) operation:

Under direct mode operation, OP (0) is by the way that outside PWM0 pin output chip, OP (1) is output to outside chip by PWM1 pin.

Figure 10 shows output waveform of the PWM10 under direct mode operation.In figure, OP0 and OP1 are relatively more internal respectively as output Signal is directly output to outside chip without processing.

Then, dead zone Timer modes are discussed, dead zone Timer modes are the modes without filtering, in dead zone timing Under device mode, digital filter is used as just counter.

It is as described below that PWM exports dead zone Timer modes (PCR:WMD [1:0]=01) operation:

Under the Timer modes of dead zone, dead time is set separately according to prime OP (1) signal and by register PDA and PDB, Generate not overlapping PWM (1) and PWM (0) output signal.

It is high internal signal OP (1) that Timer modes agreement in dead zone, which compares output to generate significant level,.Under this mode, if Set PFR register and OP (0) invalidating signal.

When setting mode as dead zone Timer modes by rewriting PCR:WMD [1:0] register, output signal PWM (0) Polarity it is identical as OP1, the polarity of output signal PWM (1) is opposite with OP1.

If detecting signal OP (1) rising edge, PWM (1) output becomes low level；Dead zone counter loads PDB deposit The setting value of device simultaneously starts countdown, and when count value becomes 0x0000, counter stops and PWM (0) is made to export high level.

If detecting signal OP (1) failing edge, PWM (0) output becomes low level；Dead zone counter loads PDA deposit The setting value of device simultaneously starts countdown, and when count value becomes 0x0000, counter stops and PWM (1) is made to export high level.

By the way that dead time register PDA and PDB is arranged, the dead time of output raising and lowering variation can accordingly be set It is fixed.

Figure 11 is the dead zone Timer modes waveform example 1 of output channel Ch10.

Figure 12 is the dead zone Timer modes waveform example 2 of output channel Ch10.

When the high-level pulse width of signal OP1 is less than the dead time of PDB setting, only PWM (1) output becomes low electricity It is flat.PWM (1) output level become high condition be pass through after OP1 failing edge PDA register setting dead time it Afterwards.In the case, output PWM (0) will remain continuously low level.

When the low level pulse width of signal OP1 is less than the dead time of PDA setting, only PWM (0) output becomes low electricity It is flat.PWM (0) output level become high condition be pass through after OP1 rising edge PDB register setting dead time it Afterwards.In the case, output PWM (1) will remain continuously low level.

Followed by discussion dead zone timer filter patterns, this is a kind of filter patterns, in this mode, digital filter Pwm signal is filtered.

Dead zone timer filter patterns (filter patterns, digital filter are filtered PWM)

It is as described below that PWM exports dead zone timer filter patterns (PCR:WMD [1:0]=10) operation:

First with digital filter, which is less than filtered width for pulse width and (is set by register PFR (making it not influences last PWM output) is fallen in OP (1) signal phagocytosis calmly).

When the pulse width of OP1 is greater than the time of register PFR setting, digital filter sets OP1 signal postponement PFR It is exported after the fixed time, then goes to generate PWM (1) and PWM (0) output by mode described in the Timer modes of front dead zone. It is high internal signal OP (1) that this mode agreement, which compares output to generate significant level,.

If detecting signal OP (1) rising edge, digital filter load PFR register value simultaneously starts metering signal OP1 High level width, when the high-level pulse width of OP1 be greater than register PFR setting time when, by fixing time set by PFR Later, PWM (1) output becomes low level；The setting value of dead zone counter load PDB register simultaneously starts countdown, works as meter When numerical value becomes 0x0000, counter stops and PWM (0) is made to export high level.

If detecting signal OP (1) failing edge, digital filter load PFR register value simultaneously starts metering signal OP1 Low level width, when the low level pulse width of OP1 be greater than register PFR setting time when, by fixing time set by PFR Later, PWM (0) output becomes low level；The setting value of dead zone counter load PDA register simultaneously starts countdown, works as meter When numerical value becomes 0x0000, counter stops and PWM (1) is made to export high level.

When the level pulse widths of OP1 are less than the time of register PFR setting, exporting PWM (0) and PWM (1) will be kept It is constant.

Figure 12 is output dead zone timer filter patterns waveform example 1.

Figure 13 is output dead zone timer filter patterns waveform example 2.

When the pulse width of OP1 be less than PFR setting time when, OP1 signal is filtered, output signal PWM (0) and PWM (1) does not change.When meeting condition PFR10 >=PDA10 and PFR10 >=PDB10, output signal PWM (0) and PWM (1) can change according to shown in Figure 13.

Next, the situation of output polarity overturning is discussed.

The polarity that PCR.LVLS [1:0] exports for changing PWM0/PWM1.

When the polarity of PCR.LVLS [1:0]=00, PWM0 and PWM1 is constant；

When the polarity of PCR.LVLS [1:0]=01, PWM0 and PWM1 is all overturn

When PCR.LVLS [1:0]=10, PWM0 polarity upset, the polarity of PWM1 is constant.

When PCR.LVLS [1:0]=11, PWM1 polarity upset, the polarity of PWM0 is constant.

By applying Multifunctional timer of the invention, not only the output of PWM can be made more stable, PWM also can be improved Precision, and realize emergency brake signal stabilization reduce serious forgiveness.The present invention cannot be only used for the control of three-phase motor, not do In the case where material alteration, it is possibly used for the motor control of other modes, is not necessarily limited to three-phase motor.

As described above, multiple word meters of the present invention by addition sub-count device and matched work in counter module Number device multiplexers, it can be achieved that PWM more stable and high-precision output.In addition, above structure makes IO selection face wide, PCB layout is more flexible.

Those skilled in the art will appreciate that application of the invention is not limited to 6 phase motors.In addition it is also possible to only use logical One of road linked operation mode, direct mode operation, dead zone Timer modes dead zone timer filter patterns are a variety of.It should manage It solves, the specific embodiment provided in description above and attached drawing is explanation time, and non-limiting.

Some exemplary embodiments are described above.It should be understood, however, that various modifications may be made.Example Such as, if described technology is executed in different order and/or if in described system, framework, equipment or circuit Component is combined and/or substituted or supplemented by other component or its equivalent in different ways, then may be implemented suitably to tie Fruit.Correspondingly, other embodiments are also fallen into scope of protection of the claims.

Claims

1. a kind of Multifunctional timer, it is used for motor control, including counter and the first trigger being connected with counter, It is characterized in that,

The counter includes multiple sub-count devices and multiple sub-count device multiplexers,

First trigger includes that multiple PWM compare generation module,

The output of the multiple sub-count device multiplexer is respectively connected to each PWM and compares generation module.

2. Multifunctional timer as described in claim 1, which is characterized in that the counter further include counter controller and Decoder, from the counter controller to each sub-count device and the decoder and each sub-count device multiplexer Output control signal, each sub-count device multiplexer export signal corresponding with the control signal.

3. Multifunctional timer as claimed in claim 2, which is characterized in that signal when each sub-count device works independently, with And signal of multiple sub-count devices when working together is input to corresponding sub-count device multiplexer, by the corresponding sub- meter Number device multiplexer selects signal corresponding with the output of the counter controller, the decoder.

4. Multifunctional timer as claimed in claim 2, which is characterized in that according to the signal exported by the decoder, come Decision needs the quantity of the sub-count device of work.

5. Multifunctional timer as claimed in claim 4, which is characterized in that the period of each sub-count device is x bit, if work Sub-count device number be n, then the periodic quantity of counter become x × n bit.

6. Multifunctional timer as described in claim 1, which is characterized in that the sub-count device, the sub-count device multichannel The quantity that multiplexer, the PWM compare generation module is different；Or, the sub-count device, the sub-count device multiplex The quantity that device, the PWM compare in generation module any 2 is identical.

7. Multifunctional timer as described in claim 1, which is characterized in that according to the output signal of the comparison controller, The timer switches between multiple modes.

8. Multifunctional timer as claimed in claim 8, which is characterized in that the multiple mode includes that channel link operates mould At least one of formula, direct mode operation, dead zone timer filter patterns and dead zone Timer modes.

9. Multifunctional timer as described in claim 1, which is characterized in that it also include the second trigger, second triggering Device includes multiple ADC starting trigger modules and triggering multiplexer, the output point of the multiple sub-count device multiplexer It is not connected to each ADC starting trigger module；The ADC starting trigger module includes ADC starting trigger controller, triggers and compare Device, flip-flop number, equivalent comparator and multiple multiplexers, the ADC starting trigger controller setting setting value, the One selective value, the second selective value, comparison control signal and counting controling signal are controlled by ADC starting trigger controller System, so that the Multifunctional timer switches between multiple modes；The multiple mode include comparison pattern and Delayed mode.

10. a kind of method that the variable amount of bits for realizing Multifunctional timer counts, is used for motor control, the Multifunction timed Device includes counter and the first trigger being connected with counter, and the counter includes counter controller, decoder, more A sub- counter and multiple sub-count device multiplexers, first trigger include that multiple PWM compare generation module, the party Method includes the following steps:

Signal is controlled from the counter controller to the multiple sub-count device, decoder output；

By the decoder according to the control signal, decoded signal is generated to determine the quantity of the sub-count device of work；

Inputted sub-count device is selected according to the signal from the decoder by the sub-count device multiplexer Output.

11. method as claimed in claim 10, which is characterized in that the period of each sub-count device is x bit, if the son meter of work Number device number is n, then the periodic quantity of counter becomes x × n bit.

12. method as claimed in claim 10, which is characterized in that signal when each sub-count device works independently and multiple Signal when sub-count device works together is input to corresponding sub-count device multiplexer, more by the corresponding sub-count device Path multiplexer selects signal corresponding with the output of the counter controller, the decoder.

13. method as claimed in claim 10, which is characterized in that the sub-count device, the sub-count device multiplexer, The quantity that the PWM compares generation module is different；Or, the sub-count device, the sub-count device multiplexer, described The quantity that PWM compares in generation module any 2 is identical.

14. method as claimed in claim 10, which is characterized in that described fixed by the output signal of the comparison controller When device switched between multiple modes.

15. method as claimed in claim 10, which is characterized in that the multiple mode includes channel link operation mode, straight At least one of logical mode, dead zone timer filter patterns and dead zone Timer modes.

16. method as claimed in claim 10, which is characterized in that the Multifunctional timer also includes the second trigger, institute Stating the second trigger includes multiple ADC starting trigger modules and triggering multiplexer, the multiple sub-count device multiplexing The output of device is respectively connected to each ADC starting trigger module；ADC starting trigger module include ADC starting trigger controller, Trigger comparator, flip-flop number, equivalent comparator and multiple multiplexers, the ADC starting trigger controller setting Setting value, first choice value, the second selective value, comparison control signal and counting controling signal start triggering control by the ADC Device is controlled, so that the Multifunctional timer switches between multiple modes；The multiple mode include than Compared with mode and delayed mode.

17. a kind of storage medium is stored with and is executed on the computing device to realize described in any one of claim 10-16 Method instruction.