CN110213513B - High-speed digital correlation double-sampling circuit structure based on monoclinic ADC - Google Patents
High-speed digital correlation double-sampling circuit structure based on monoclinic ADC Download PDFInfo
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- CN110213513B CN110213513B CN201910376826.0A CN201910376826A CN110213513B CN 110213513 B CN110213513 B CN 110213513B CN 201910376826 A CN201910376826 A CN 201910376826A CN 110213513 B CN110213513 B CN 110213513B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/67—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
Abstract
The invention discloses a high-speed digital phase based on a monoclinic ADCA double-sampling-off circuit structure including a comparator U1, a comparator U2 for performing an a/D conversion operation; the comparator U1 is used for comparing reset signal V output from pixel unitrstA ramp signal V formed with a ramp generatorrampThe comparator U2 is used for comparing the exposure signal V output from the pixel unit after the exposure is finishedsigAnd the ramp signal V formed by the ramp generatorrampHolding capacitors C are respectively arranged between the comparator U1, the comparator U2 and the pixel unitH1And a holding capacitor CH2Respectively for storing reset signals V output by the pixel unitsrstAnd an exposure signal Vsig. The invention can reduce the fixed mode noise and improve the working frequency of the circuit.
Description
Technical Field
The invention relates to the technical field of CMOS image sensors, in particular to a high-speed digital correlation double-sampling circuit structure based on a single-slope ADC (analog-to-digital converter).
Background
In the CMOS image sensor, due to factors such as process and temperature, there is a certain degree of mismatch between transistors in each column of pixel units, such as variations in threshold voltage of a source follower, fluctuations in MOS transistor size, and the like. Under the same lighting conditions, the mismatch of these transistors can cause the output value of the pixel cell to deviate, and this deviation value forms Fixed Pattern Noise (FPN) in the pixel cell. Fixed pattern noise is one of the main factors that cause degradation in image quality.
The Correlated Double Sampling (CDS) technique can eliminate fixed pattern noise in a pixel, i.e., a reset signal VrstAnd an exposure signal VsigThe difference is made to reduce the FPN. The analog correlated double sampling technique transfers an analog value obtained by subtracting the exposure signal voltage from the pixel reset voltage to the ADC, and analog CDS can eliminate FPN but requires a large capacitance to improve accuracy, which requires a large capacitance size. Therefore, digital CDS is commonly employed in a single-slope ADC to reduce settlingPattern noise, in digital CDS, typically eliminates FPN by comparing a reset signal and an exposure signal with each other through two ramp signals. This results in more ramps being required for the monoclinic ADC in the digital CDS, which makes the a/D conversion time of the digital CDS much longer than the analog CDS. Although digital CDS helps to obtain high quality images, it is much slower than analog CDS, which limits the application of digital CDS.
Disclosure of Invention
The invention aims to provide a high-speed digital correlation double sampling circuit structure based on a single-slope ADC, which can reduce fixed mode noise and improve the running speed of a circuit at the same time aiming at the technical defects in the prior art.
The technical scheme adopted for realizing the purpose of the invention is as follows:
a high-speed digital correlation double sampling circuit structure based on a single-slope ADC comprises:
a comparator U1, a comparator U2 for performing a/D conversion operation; the comparator U1 is used for comparing reset signal V output from pixel unitrstA ramp signal V formed with a ramp generatorrampThe comparator U2 is used for comparing the exposure signal V output from the pixel unit after the exposure is finishedsigAnd the ramp signal V formed by the ramp generatorrampHolding capacitors C are respectively arranged between the comparator U1, the comparator U2 and the pixel unitH1And a holding capacitor CH2Respectively for storing reset signals V output by the pixel unitsrstAnd an exposure signal Vsig。
Further, the comparator U1, the comparator U2 and the holding capacitor CH1And a holding capacitor CH2Between which a DC blocking capacitor C is respectively arranged1Dc blocking capacitor C2。
Preferably, the comparator U1The positive input end of the comparator U2 and the negative input end of the comparator U2 are respectively connected through a DC blocking capacitor C1DC blocking capacitor C2And a switch S1Switch S2The holding capacitor C is connected with the pixel unitH1And a holding capacitor CH2Are respectively connected with a DC blocking capacitor C1And switch S1A DC blocking capacitor C2And a switch S2To (c) to (d); the positive input end of the comparator U1 and the negative input end of the comparator U2 are respectively connected with the switch S3Switch S4The output ends of the comparator U1 and the comparator U2 are connected, and the output ends of the comparator U1 and the comparator U2 are respectively connected through a switch S5Switch S6And a capacitor C3Capacitor C4And then connected with a trigger counting circuit unit.
Preferably, the signal output end of the ramp generator is connected to the negative input end and the positive input end of the comparator U1 and the comparator U2, respectively.
Wherein the holding capacitance CH1And a holding capacitor CH2And the other end of the same is grounded.
The trigger counting circuit unit comprises a trigger, a counter and a register which are connected in sequence, wherein the trigger and the capacitor C3Capacitor C4And the trigger is used for triggering according to a level flip signal output by the comparator U1 or the comparator U2 at a corresponding moment to generate a trigger pulse signal so as to store the digital code value of the counter at the moment into the register.
Compared with the prior art, the invention has the beneficial effects that:
the present invention reduces fixed pattern noise through digital CDS, and at the same time, only one ramp signal is required in digital CDS to sufficiently obtain a digital code since a reset signal and a pixel signal are separately stored through the operation of CDS, increasing the operating speed of a circuit.
In addition, the invention can calculate the digital code corresponding to the difference between the reset signal and the pixel signal by using the comparator and the simple counter, thereby completing the A/D conversion and being beneficial to reducing the chip area of the digital module.
Drawings
Fig. 1 is a circuit diagram of a digital CDS circuit based on a single-ramp ADC.
Fig. 2 is a timing diagram of digital CDS based on a single-ramp ADC.
FIG. 3 shows a reset signal VrstExposure signal VsigAnd a ramp signal VrampAnd voltage change schematic diagram.
Fig. 4 is a schematic diagram of digital codes obtained when fluctuations occur in the reset signal and the pixel signal.
Detailed Description
The invention is described in further detail below with reference to the figures and specific examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
As shown in fig. 1, the high-speed digital correlated double sampling circuit structure based on the single-slope ADC of the present invention includes:
two comparators U1, U2 for performing a/D conversion operations; the comparator U1 is used for comparing the reset signal VrstAnd a ramp signal VrampThe comparator U2 is used for comparing the exposure signal VsigAnd a ramp signal Vramp
Also comprises a holding capacitor CH1，CH2And a DC blocking capacitor C1，C2Wherein, the positive input terminal of the comparator U1 and the negative input terminal of the comparator U2 pass through the blocking capacitor C respectively1，C2And a switch S1、S2A holding capacitor C connected to the pixel unitH1，CH2Are respectively connected with a DC blocking capacitor C1And switch S1And a DC blocking capacitor C2And a switch S2To (c) to (d); the positive input terminal of the comparator U1 and the negative input terminal of the comparator U2 are respectively connected with the switch S3，S4Connected with the output ends of the comparators U1 and U2, and the output ends of the comparators U1 and U2 are respectively connected with the output ends of the comparators U1 and U2 through the switches S5，S6And a capacitor C3，C4After being connected, the trigger counting circuit unit is connected.
The invention is achieved by using a holding capacitor C at the nodeH1，CH2And a DC blocking capacitor C1，C2Can effectively separateReset signal VrstAnd an exposure signal Vsig。
FIG. 2 is a timing diagram of digital CDS based on a single-ramp ADC, and FIG. 3 is a reset signal VrstExposure signal VsigAnd a ramp signal VrampAnd voltage change schematic diagram. Since the reset signal and the exposure signal are separately stored in C by the operation of CDSH1And CH2Therefore, even if there is only one ramp signal VrampIt is sufficient to obtain the desired digital code value. The working process of the circuit in the invention can be divided into four stages:
stage A, firstly, the pixel unit in FIG. 1 is reset and outputs a reset signal VrstSwitch S1And S3Is turned on, switch S2And S4When the pixel unit is turned off, the reset signal output by the pixel unit is stored in the holding capacitor CH1(ii) a Then exposing the pixel unit, and outputting an exposure signal V after the exposure is finishedsigSwitch S2And S4Is turned on, switch S1And S3The exposure signal output by the pixel unit is stored in the holding capacitor C after being disconnectedH2The above.
Phase B, the ramp signal starts to fall, switch S in FIG. 11、S2、S3And S4Are all disconnected and stored in a holding capacitor CH1And CH2The reset signal and the exposure signal in (1) remain unchanged. At the same time, switch S is closed5Opening switch S6And the comparator U1 is connected into the circuit to complete the comparison between the reset signal and the ramp signal, and the comparator U2 is not connected into the circuit.
At t1Before time, VrampGreater than VrstThe comparator U1 outputs a low level; t is t1Thereafter, the comparator U1 outputs a high level; at t1At the moment, the ramp signal is the same as the reset signal, the output of the comparator U1 is inverted, and the level-inverted signal output by the comparator U1 triggers the flip-flop to generate a trigger pulse signal. This pulse signal saves the code value of the counter at this time into the register.
Stage C, the ramp signal continues to fall, at which time the switch S6Closed, switch S5DisconnectAnd the comparator U2 is connected into a circuit to complete the comparison of the ramp signal and the exposure signal. At t1Before time, VrampGreater than VsigThe comparator U2 outputs a high level; t is t2Thereafter, the comparator U2 outputs a low level; at t2At the moment, the ramp signal is the same as the exposure signal, the output of the comparator U2 is inverted, and the level-inverted signal output by the comparator U2 triggers the flip-flop to generate a trigger pulse signal. This pulse signal saves the digital code value of the counter at that time into the register. A digital code corresponding to the difference between the reset signal and the pixel signal can be calculated from the two digital code values stored in the registers.
And stage D, all the switches are disconnected, and the circuit returns to the initial state.
Fixed Pattern Noise (FPN) affects the output of the pixel unit, for example, fig. 4 is a schematic diagram of a digital code obtained when the reset signal and the pixel signal fluctuate, and the reset signal is V due to the FPNrst1Down to Vrst2Exposure signal is represented by Vsig1Down to Vsig2. Since the same set of reset signal and exposure signal is from the same pixel unit, the FPN has the same effect on the reset signal and exposure signal, i.e., the fluctuation Δ V of the reset signalrst＝Vrst1-Vrst2Equal to the fluctuation DeltaV of the exposure signalsig＝Vsig1-Vsig2. Therefore, the digital Code durations corresponding to the two sets of signals are the same, i.e., Code1 is Code2, and the proposed CDS structure can achieve the purpose of eliminating the fixed pattern noise.
In the invention, at the end of the stage B, the ramp signal is the same as the reset signal, the output of the comparator is inverted, and the code value of the counter at the moment is stored in the register; at the end of stage C, the ramp signal and the exposure signal are the same, the output of the comparator is inverted, and the code value of the counter at this time is saved in the register. A digital code corresponding to the difference between the reset signal and the pixel signal can be calculated from the two digital code values stored in the register. Separately storing a reset signal and an exposure signal in a holding capacitance C by the operation of CDSH1And CH2Thus even a single ramp signal is sufficient to obtain the desired digital code value.
From the above analysis, it can be seen that, compared with the conventional two-ramp scheme, the CDS technique proposed by the present invention compares the reset signal and the pixel signal by using one ramp signal, so that the present invention can increase the operating frequency of the circuit while reducing the fixed pattern noise.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (6)
1. A high-speed digital correlated double sampling circuit structure based on a single-slope ADC (analog to digital converter), which is characterized by comprising: a comparator U1, a comparator U2 for performing a/D conversion operation; the comparator U1 is used for comparing reset signal V output from pixel unitrstA ramp signal V formed with a ramp generatorrampThe comparator U2 is used for comparing the exposure signal V output from the pixel unit after the exposure is finishedsigAnd the ramp signal V formed by the ramp generatorramp，Holding capacitors C are respectively arranged between the comparator U1, the comparator U2 and the pixel unitH1And a holding capacitor CH2Respectively for storing reset signals V output by the pixel unitsrstAnd an exposure signal Vsig。
2. The high-speed digital correlated double sampling circuit structure based on single-slope ADC of claim 1, wherein said comparator U1, comparator U2 and holding capacitor CH1And a holding capacitor CH2Between which a DC blocking capacitor C is respectively arranged1Dc blocking capacitor C2。
3. The high-speed digital correlated double sampling circuit structure based on single-slope ADC of claim 1, wherein the positive input of said comparator U1The negative input end of the end and the comparator U2 pass through a DC blocking capacitor C respectively1DC blocking capacitor C2，And a switch S1Switch S2The holding capacitor C is connected with the pixel unitH1And a holding capacitor CH2Are respectively connected with a DC blocking capacitor C1And switch S1And a DC blocking capacitor C2And a switch S2To (c) to (d); the positive input end of the comparator U1 passes through a switch S3Is connected with the output end of a comparator U1, and the negative input end of the comparator U2 is connected with the output end of the comparator U1 through a switch S4The output end of the comparator U2, the output ends of the comparator U1 and the comparator U2 are respectively connected with the switch S5Switch S6And a capacitor C3Capacitor C4And then connected with a trigger counting circuit unit.
4. The high-speed digital correlated double sampling circuit structure based on the single-slope ADC of claim 1, wherein the signal output terminal of the ramp generator is connected with the negative input terminal and the positive input terminal of the comparator U1 and the comparator U2 respectively.
5. A high speed digital correlated double sampling circuit structure based on single-slope ADC as claimed in claim 1, wherein said holding capacitor CH1And a holding capacitor CH2And the other end of the same is grounded.
6. The high-speed digital correlated double sampling circuit structure based on the monoclinic ADC of claim 3, wherein the trigger counting circuit unit comprises a trigger, a counter and a register which are connected in sequence, and the trigger is connected with a capacitor C3Capacitor C4And the trigger is used for triggering according to a level flip signal output by the comparator U1 or the comparator U2 at a corresponding moment to generate a trigger pulse signal so as to store the digital code value of the counter at the moment into the register.
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| CN112825548B (en) * | 2019-11-21 | 2024-03-01 | 格科微电子（上海）有限公司 | Implementation method for reducing crosstalk of image sensor circuit |
| CN111405195B (en) * | 2020-03-23 | 2021-06-22 | 西安微电子技术研究所 | Data conversion device and method of double-exposure CMOS image sensor |
| CN113411523B (en) * | 2021-06-08 | 2022-09-16 | 天津大学 | Column shared pseudo-correlation multi-sampling readout circuit for CMOS image sensor |
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| KR100826513B1 (en) * | 2006-09-08 | 2008-05-02 | 삼성전자주식회사 | Correlated Double Sampling and Analogue to Digital Converting Apparatus using multiple sampling in CMOS image Sensor |
| KR100878304B1 (en) * | 2006-11-03 | 2009-01-14 | 삼성전자주식회사 | Correlated double sampling circuit for performing correlated double sampling and cyclic analog digital convertor device having thereof |
| JP2011259305A (en) * | 2010-06-10 | 2011-12-22 | Toshiba Corp | Solid state imaging device |
| JP5801665B2 (en) * | 2011-09-15 | 2015-10-28 | キヤノン株式会社 | Solid-state imaging device, A / D converter and control method thereof |
| KR101356049B1 (en) * | 2012-03-16 | 2014-01-29 | 한국과학기술원 | ADC for A/D conversion using complementary ramp signal and image sensing device using the same |
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