CN110189679B

CN110189679B - Display device

Info

Publication number: CN110189679B
Application number: CN201910549797.3A
Authority: CN
Inventors: 李明贤; 张哲嘉
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2018-08-10
Filing date: 2019-06-24
Publication date: 2022-07-01
Anticipated expiration: 2039-06-24
Also published as: CN110189679A

Abstract

The invention provides a display device. The display device includes a plurality of partitions, each of which includes a plurality of display pixels, control lines, and switches. The switch is electrically connected between the display pixels and the control lines of the partitions and is controlled by the partition enabling signal of the gate line in the partition to be switched on or off.

Description

Display device

Technical Field

The present invention relates to a display device, and more particularly, to a display device for updating a display screen in a partitioned manner.

Background

Due to the development of large-scale, high-frequency, and high-resolution display devices, the power consumption of displays has rapidly increased. Therefore, a technique for updating a display screen in a divided manner has been developed, in which video data is refreshed only in a local divided region at a normal frequency, and is refreshed in most other divided regions at a reduced frequency, thereby effectively reducing the power consumption of the display device.

However, in the display device for updating the display screen by the partitions in the prior art, the partition control lines are shared with the partitions in the same row, and when the display screen is updated by the partitions, the interaction effect between the partitions is generated. When a display screen is updated in a divisional manner, a leakage phenomenon occurs differently between the divisional areas due to a difference in ON (ON) or OFF (OFF) states of Thin-Film transistors (TFTs) in each display pixel of the different divisional areas. The leakage phenomenon may cause different optical expressions of the display pixels between different sub-regions, and may cause cross-talk (crosstalk) to occur in the entire display frame of the display, thereby reducing the display quality.

Disclosure of Invention

The invention provides a display device for updating a display picture in a partition mode, which can effectively reduce the power consumption of the display device and improve the display quality.

The display device of the present invention includes a plurality of partitions. Each partition includes a plurality of display pixels, control lines, and switches. The control lines are used for transmitting partition control signals. The switch is electrically connected between the display pixels and the control lines and is controlled by a partition enabling signal of the gate lines in the partitions to be switched on or off.

In view of the above, the present invention provides a display device for updating a display screen in a partition, in which a switch is provided in a partition, and a data refresh frequency of the partition is determined by turning on or off the switch. The on-off of the switch is controlled by the grid line of the subarea, so that the influence of other subareas during data refreshing can be avoided, the problem of picture crosstalk among different subareas can be improved, and the display device can maintain good display quality when the subareas update the display picture.

Drawings

Fig. 1 is a schematic diagram of a display device according to a first embodiment of the invention including a plurality of partitions.

FIG. 2 is a schematic diagram of one of a plurality of partitions of the first embodiment of the invention.

Fig. 3 is a schematic diagram of the leakage difference between different partitions of the display device for updating the display screen according to the present invention and the conventional partition.

Fig. 4 is a schematic diagram of a circuit architecture of the first embodiment of the present invention.

FIG. 5 is a schematic diagram of one of a plurality of partitions of a second embodiment of the invention.

Wherein the reference numerals are:

20: multiplexer circuit 30: gate driver

40: the source driver 100: display device

400: display devices CL1 to CL 3: control wire

CLC: pixel capacitance CLP: wiring

GL 1-GLM: gate lines PX 11-PXMN: display pixel

SL1 to SLN: data transmission lines SW1, SW 2: switch with a switch body

T1, T2, TSW: transistors Z11-Z33: partitioning

Detailed Description

Referring to fig. 1, fig. 1 is a schematic view of a display device according to a first embodiment of the invention. The display device 100 is provided with a plurality of partitions Z11-Z33 which are arranged in an array, wherein the partitions Z11-Z31 form a first display line; partitions Z12-Z32 form a second display row; the partitions Z13-Z33 form a third display row. In the embodiment, each of the partitions Z11 through Z33 of the display device 100 is electrically connected to the gate lines GL1 through GLM and the data transmission lines SL1 through SLN, respectively, and the display device 100 is electrically connected to the control lines CL1 through CL 3. The control lines CL1 to CL3 are respectively disposed adjacent to the data transmission lines SL1 to SLN of each partition, and the control lines CL1 to CL3 are respectively corresponding to different display rows. In the present embodiment, only 9 partitions Z11-Z33 are taken as an example, and the number of partitions in other embodiments of the present invention is not limited thereto and can be arbitrarily adjusted.

Please refer to fig. 1 and fig. 2 synchronously, wherein fig. 2 is a schematic diagram of one partition of a plurality of partitions according to a first embodiment of the present invention. In the embodiment, taking the partition Z11 as an example, the partition Z11 includes a plurality of display pixels PX11 to PXMN and a switch SW 1. In detail, the display pixels PX 11-PX 1N are connected to the control terminal of the switch SW1 through the gate line GL1, the display pixels PX 1N-PXMN are electrically connected to the first terminal of the switch SW1 through the routing CLP, and the second terminal of the switch SW1 is electrically connected to the control line CL 1.

It should be noted that the control terminal of the switch SW1 is electrically connected to the gate line GL1 of the partition Z11, and controls the switch SW1 to be turned on or off according to the partition enabling signal on the gate line GL1, so as to introduce the partition control signal of the control line CL1 into the partition Z11.

In terms of the architecture of the display pixels PX11 to PXMN, taking the display pixel PX1N as a fanciful, the display pixel PX1N includes transistors T1 and T2 and a pixel capacitor CLC. The control terminal of the transistor T1 is electrically connected to the second terminal of the switch SW1, the first terminal of the transistor T1 is electrically connected to the second terminal of the transistor T2, the control terminal of the transistor T2 is electrically connected to the corresponding gate line GL1, the first terminal of the transistor T2 is electrically connected to the corresponding data transmission line SLN, and the pixel capacitor CLC is connected in series between the second terminal of the transistor T1 and the ground reference terminal.

In the operation details, when the operation of updating the display screen by the partition is performed, the display screen update is performed only for the partition Z11 as an example. In the data update mode of the partition Z11, the gate lines GL1 to GLM corresponding to the partition Z11 perform a gate scan operation according to a first refresh frequency, the data lines SL1 to SLN corresponding to the partition Z11 also perform a data transmission operation according to the first refresh frequency, and the control line CL1 provides a partition control signal according to the first refresh frequency, so as to perform the display screen refresh of the partition Z11 according to the first refresh frequency. On the other hand, the other partitions Z12 to Z33 other than the partition Z11 operate in the data retention mode, and perform display screen refresh of the other partitions Z12 to Z33 at a relatively low second refresh frequency. In an embodiment of the present invention, the first refresh rate may be 60 hertz (Hz), and the second refresh rate may be 1 Hz.

To be more specific, when the partition Z11 is in the data update mode, the switch SW1 can be turned on or off according to the partition enable signal on the gate line GL 1. When the switch SW1 is turned on according to the partition enabling signal on the gate line GL1, the partition control signal on the control line CL1 can be transmitted to the display pixels PX11 to PX1N through the turned-on switch SW1, for example, transmitted to the control terminal of the transistor T1 in the display pixel PX1N through the wiring CLP, and the display pixels PX11 to PX1N perform the data refresh operation by controlling the on operation of the transistor T1. In the data update mode, the partition control signals on the control line CL1 perform the data refresh operations of the display pixels PX 11-PX 1N according to a relatively high first refresh frequency.

In contrast, when the partition Z11 is in the data retention mode, the partition control signal on the control line CL1 is activated according to the relatively low second refresh frequency, and when the switch SW1 is turned on according to the partition enabling signal on the gate line GL1, the partition control signal on the control line CL1 can be transmitted to the display pixels PX11 to PX1N through the turned-on switch SW1, for example, transmitted to the control terminal of the transistor T1 in the display pixel PX1N through the trace CLP, and by controlling the turning-on of the transistor T1, the display pixels PX11 to PX1N perform the data refresh operation. In the data retention mode, the partition control signals on the control line CL1 may perform the data refresh operations for the display pixels PX 11-PX 1N at a relatively low second refresh frequency.

As can be seen from the above description, by providing the switch SW1 in each of the partitions Z11 to Z33, the display screen refresh operation is performed at the first refresh frequency only for one or more of the partitions, for example, Z11, and the display screen refresh operation is performed at the second refresh frequency lower than the first refresh frequency for the other partitions, for example, Z12 to Z33, so that the power consumption of the display device can be reduced.

By setting the switch SW1 of the partition Z11, even if one control line CL1 is shared by a plurality of partitions Z11, Z21, and Z31 on the same row, when the partition Z11 operates in the data maintenance mode, the switch SW1 is controlled by the gate line GL1 corresponding to the second refresh frequency, so that the partition Z11 does not affect the display screen refresh operation of the other partitions Z21 and Z31 at the first refresh frequency, and the data refresh operation of each of the display pixels PX11 to PXMN is performed at the second refresh frequency. That is, by setting the switch SW1, the interaction between the partition Z11 and the other partitions Z21 and Z31 sharing one control line CL1 due to the difference in refresh frequency can be avoided.

The switch SW1 of the display device 100 of the present invention can be constructed by a transistor TSW, a control terminal of which is electrically connected to the gate line GL1 and is used for receiving a partition enabling signal. The first terminal of the transistor TSW is electrically connected to the control line CL1, and the second terminal of the transistor TSW is electrically connected to the control terminals of the transistors (e.g., the transistor T1) in the plurality of display pixels PX 11-PXMN in the partition Z11. The transistor TSW and the transistors T1 and T2 may be the same type of transistor. Therefore, the switch SW1 of the display device 100 of the present invention can be manufactured simultaneously with a matrix substrate in the manufacturing process of the matrix substrate of the display device, without additional process cost or material consumption.

In the display device 100 of the present invention, when one of the partitions Z11 of the partitions Z11 to Z33 is operated in the data update mode, the partition Z11 is operated at a first refresh frequency (for example, 60Hz), and the switch SW1 corresponding to the first refresh frequency is turned on or off. When the other partitions Z12 to Z33 of the partitions Z11 to Z33 are operating in the data retention mode, the partitions Z12 to Z33 are operating at a second refresh frequency (e.g., 1 Hz). Since the first refresh rate is greater than the second refresh rate, only a part of the partitions (for example, the partition Z11) is subjected to the display screen refresh operation at the first refresh rate. The other partitions Z12 to Z33 are subjected to the display screen refresh operation at the second low refresh frequency to enter the power consumption saving state, so that the power consumption can be reduced.

In fig. 2, the control terminal of the switch SW1 is electrically connected to the gate line GL1 of the partition Z11, i.e. the partition enabling signal is provided by the gate line GL1 of the partition Z11, but the invention is not limited thereto. The control terminal of the switch SW1 can be electrically connected to any gate line of the partition Z11, that is, the partition enabling signal can be provided by any gate line of the gate lines GL 1-GLM in each partition Z11.

FIG. 3 is a schematic diagram illustrating the leakage difference between different partitions of the display device for updating the display screen according to the present invention and the prior art. Referring to fig. 2 and fig. 3 synchronously, only the partition Z22 of the partitions Z11 to Z33 of the display device 100 operates in the data update mode at the first refresh frequency (e.g., 60Hz), and the other partitions (e.g., Z12 and Z33) outside the display region Z22 operate in the data retention mode at the second refresh frequency (e.g., 1 Hz). In fig. 3, when the partition Z22 is in the data refresh mode and the partition Z22 performs display screen refresh at a first refresh frequency (for example, 60Hz), the control line CL2, the gate lines GL1 to GLM, and the data transmission lines SL1 to SLN connected to the partition Z22 are all operated at the first refresh frequency, that is, the pixel capacitors CLC of the display pixels PX11 to PXMN in the partition Z22 are refreshed at the first refresh frequency.

In fig. 3, when the partition Z12 is in the data retention mode and the partition Z12 performs display screen refresh at the second refresh frequency (for example, 1Hz), the gate lines GL1 to GLM and the data transmission lines SL1 to SLN connected to the partition Z12 operate at the second refresh frequency, but the control line CL2 is shared with the partition Z22 in the data update mode, and therefore the control line CL2 is at the first refresh frequency (for example, 60 Hz). Although the same control line CL2 is used for the partition Z12 and the partition Z22, the control terminal of the switch SW1 is electrically connected to the gate line GL1 of the partition Z12, and therefore the switch SW1 of the partition Z12 is also turned on or off according to the second refresh frequency. Therefore, partition Z12 is isolated by switch SW1 from the effects of the data update actions performed by partition Z22 according to the first refresh rate.

In this way, the difference in optical representation between the display images on the partition Z12 and the partitions Z22 and Z33 can be reduced, and no phenomenon such as screen crosstalk occurs. Therefore, the display device of the invention can still maintain good display quality when the display screen is updated in a subarea way.

In the present embodiment, each of the display pixels PX11 to PXMN includes 2 electric bodies T1 and T2, but the present invention is not limited thereto. That is, the present invention is also applicable to the display pixels PX11 to PXMN including 2 or more transistors.

Fig. 4 is a schematic diagram of a circuit architecture of the first embodiment of the present invention. As shown in fig. 4, the display device 400 for updating the display screen in the divided areas according to the present invention includes a multiplexer circuit 20, a gate driver 30, and a source driver 40. The output end of the multiplexer circuit 20 is electrically connected to the control lines CL 1-CL 3 and the data transmission lines SL 1-SLN. When one of the partitions Z11-Z33, for example, the partition Z11, is operating in the data update mode, the control line CL1 at the output terminal of the corresponding multiplexer circuit 20 operates according to the first refresh frequency. When the other partitions, e.g., Z12, Z13, are operating in the data retention mode, the control lines CL2, CL3 at the output of the corresponding multiplexer circuit 20 operate according to the second refresh frequency.

In addition, the above-mentioned embodiment is exemplified by one multiplexer circuit 20, however, the multiplexer circuit 20 may be arbitrarily adjusted corresponding to the number of partitions, or the multiplexer circuit 20 may be incorporated into a plurality of source drivers 40 without being separately provided.

On the other hand, the output terminals of the gate driver 30 are electrically connected to the gate lines GL 1-GLM, respectively, and when the partition Z11 operates in the data update mode, the output terminal of the gate driver 30 corresponding to the partition Z11 operates at the first refresh frequency, and when other partitions, for example, the partition Z21 and the partition Z31, operate in the data retention mode, the output terminal of the gate driver 30 corresponding to the partition Z21 and the partition Z31 operates at the second refresh frequency.

In addition, the output terminals of the source driver 40 are electrically connected to the data transmission lines SL 1-SLN, respectively, and when each partition Z11 operates in the data update mode, the output terminal of the source driver 40 corresponding to the partition Z11 operates at the first refresh frequency, and when other partitions, such as the partition Z12 and the partition Z13, operate in the data retention mode, the output terminal of the source driver 40 corresponding to the partition Z12 and the partition Z13 operates at the second refresh frequency.

The second refresh frequency described above is a frequency used in the data holding mode, and the embodiment exemplifies data holding using 1 Hz. However, the second refresh rate may be lower than the first refresh rate. For example, if the off characteristics of the transistor T1 or the transistor T2 of each of the display pixels PX11 to PXMN are not good and the leak is large, it is conceivable to increase the frequency used in the data holding mode from 1Hz to 5Hz or higher to ensure the display quality of the divisional update display screen.

FIG. 5 is a schematic view of one of the partitions Z11 of the plurality of partitions Z11-Z33 of the second embodiment of the invention. Unlike the embodiment of fig. 2, switches SW2 are provided in many sections Z11 to Z33. In the second embodiment, the same portions as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted, and points different from those in the first embodiment will be described.

As shown in fig. 5, in the second embodiment of the present invention, two switches, i.e., a switch SW1 and a switch SW2, are provided in each of the partitions Z11 to Z33. First ends of the switches SW1 and SW2 are electrically connected to a control line CL1 of the partition Z11, second ends of the switches SW1 and SW2 are electrically connected to control ends of transistors T1 of the display pixels PX 11-PXMN in the partition Z11, a control end of the switch SW1 is electrically connected to a gate line GL1 of the partition Z11, and a control end of the switch SW2 is electrically connected to a gate line GL2 of the partition Z11.

Therefore, in the second embodiment of the present invention, the control terminals of the transistors T1 of the display pixels PX11 to PXMN in the sub-area Z11 are driven by the two switches of the switch SW1 and the switch SW 2. When the gate line GL1 and the gate line GL2 of the partition Z11 are connected to turn on the switch SW1 and the switch SW2, the control terminal of the wire CLP in the partition Z11 and the control terminal of each transistor T1 of each display pixel PX11 to PXMN can be charged or discharged to the voltage level of the control line CL1 for a longer time. When the voltage level of the control terminal of each transistor T1 matches the voltage level of the control line CL1, it is ensured that each transistor T1 operates normally, and the image data of the pixel capacitor CLC can be updated more efficiently and completely.

In fig. 5, the control terminal of the switch SW1 is electrically connected to the first gate line GL1 of the partition Z11, and the control terminal of the switch SW2 is electrically connected to the second gate line GL2 of the partition Z11, but the invention is not limited thereto. The control terminals of the switches SW1 and SW2 can be electrically connected to any two gate lines in the partition Z11, respectively.

In the second embodiment of the present invention, the voltage levels of the routing CLP and the control terminal of each transistor T1 are ensured by the two switches SW1 and SW2, so as to ensure the normal operation of each transistor T1, and to more effectively and completely update the image data of each pixel capacitor CLC. The invention is not so limited. That is, the voltage level of the control terminal of each transistor T1 of each display pixel PX11 to PXMN in the partition Z11 can be brought closer to the voltage level of the control line CL1 by two or more switches.

In summary, the display device for updating the display screen in the sub-areas of the present invention ensures that there is no interaction effect between the sub-areas by additionally arranging a switch in each sub-area. If each of the sub-areas is in the data holding mode, each of the transistors in the sub-areas is in a state corresponding to the second refresh frequency, and thus the leakage of the pixel capacitance of each display pixel is small. Therefore, there is no difference in optical performance between the partitions in the data holding mode, that is, no phenomenon such as crosstalk occurs. Therefore, the display device of the embodiment of the invention can still maintain good display quality when the display screen is updated in a subarea way.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A display device, comprising:

a plurality of partitions corresponding to the plurality of gate lines, each of the partitions including:

the display pixels are arranged into a plurality of display rows and a plurality of display columns, the display rows are respectively and electrically connected to the gate lines, and the display columns are respectively and electrically connected to the data transmission lines; the display pixel includes: a first transistor having a first end electrically connected to the data transmission line, a second transistor having a first end electrically connected to a second end of the second transistor, and a control end electrically connected to each of the corresponding gate lines; and a pixel capacitor connected in series between the second terminal of the first transistor and a reference ground terminal;

a control line for transmitting a partition control signal; and

the switch is electrically connected between the display pixels and the control line and is controlled by a partition enabling signal of the gate line in the partition to be switched on or off, and the control end of the first transistor is electrically connected to the second end of the switch.

2. The display device of claim 1, wherein the segment enable signal is provided by one of the gate lines in each segment.

3. The display device according to claim 1, wherein the switch is a transistor, a first terminal of the transistor is electrically connected to the control line, a second terminal of the transistor is electrically connected to a control terminal of the first transistor, and the control terminal of the transistor receives the partition enable signal.

4. The display device according to claim 1, wherein when each of the partitions operates in a data update mode, the corresponding switch is turned on and each of the partitions operates at a first refresh frequency, and when each of the partitions operates in a data retention mode, the corresponding switch is turned off and each of the partitions operates at a second refresh frequency, wherein the first refresh frequency is greater than the second refresh frequency.

5. The display device of claim 4, further comprising:

a multiplexer circuit electrically connected to the control line.

6. The display apparatus according to claim 5, wherein the control line of the multiplexer circuit operates according to the first refresh frequency when each of the partitions operates in the data update mode, and wherein the control line operates according to the second refresh frequency when each of the partitions operates in the data retention mode.

7. The display device according to claim 4, wherein the first refresh rate is 60Hz and the second refresh rate is 1 Hz.

8. The display device of claim 1, further comprising:

a plurality of gate drivers, respectively electrically connected to the gate lines, for respectively providing a plurality of gate driving signals; and

and the source drivers are respectively and electrically connected to the data transmission lines and used for respectively providing a plurality of source driving signals.