CN110188052A - It is a kind of for improving the method and device of RGMII interface stability - Google Patents
It is a kind of for improving the method and device of RGMII interface stability Download PDFInfo
- Publication number
- CN110188052A CN110188052A CN201910403661.1A CN201910403661A CN110188052A CN 110188052 A CN110188052 A CN 110188052A CN 201910403661 A CN201910403661 A CN 201910403661A CN 110188052 A CN110188052 A CN 110188052A
- Authority
- CN
- China
- Prior art keywords
- interface
- clock signal
- improving
- value
- rgmii
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/102—Program control for peripheral devices where the programme performs an interfacing function, e.g. device driver
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Communication Control (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Information Transfer Systems (AREA)
Abstract
The present invention relates to high- speed network communication design and applied technical fields, more particularly to it is a kind of for improving the method and device of RGMII interface stability, including, step S1, the serial ports surplus of interface clock signal is received with raising to one first preset value by adjusting the delay value for receiving the corresponding register of interface clock signal.Beneficial effect is: not having to the problem of improving printed circuit board structure, being able to solve producing line, does not have to replacement chip, also it can solve bad problem, the workload of doing over again for saving producing line, can be that the bad chip of consistency can be used steadily, further save cost.
Description
Technical field
The present invention relates to high- speed network communication design and applied technical fields, more particularly to one kind to connect for improving RGMII
The method and device of mouth stability.
Background technique
Higher and higher now for the demand of network bandwidth, also more and more equipment need gigabit Ethernet.Gigabit with
Too the indispensable ring of Network Communication is exactly the interface section between physical chip and ethernet controller.Common interface shape
Formula has MII (Medium Independent Interface), GMII (Gigabit MII) and RGMII Reduced GMII
Deng.Wherein interface signal line number is reduced to 14 by RGMII interface, and TX (tranmitting data register interface) or RX (receiving clock interface) are counted
Become 4 according to width, in order to keep the transmission rate of 1000Mbps constant, rising edge and failing edge of the RGMII interface in clock
All sampled datas.
In existing production process, due to PCB (Printed Circuit Board, Chinese are printed circuit board,
Also known as printed wiring board) differences such as plate, device, the problem of will lead to fraction defective.In the production of gigabit Ethernet, reinforcement pair
The control of plate and device, even if in this way will be present nearly 2.3% it is bad, replace chip after can solve the problems, such as this.But
It is to carry out replacement chip processing, larger workload, and higher cost, while cannot protect for all undesirable printed circuit boards
Same problem is likely encountered in card subsequent yield chip.
Summary of the invention
For the above-mentioned problems in the prior art, a kind of method for improving RGMII interface stability is now provided
And device.
Specific technical solution is as follows:
A method of for improving RGMII interface stability, including:
Step S1, by adjusting receiving the delay value of the corresponding register of interface clock signal to one first preset value, with
Improve the serial ports surplus for receiving interface clock signal.
Preferably, the step S1 includes:
Step S10, the delay value for receiving the corresponding register of interface clock signal is adjusted to first preset value；
Step S11, the resistance value for being series at the resistance for receiving interface clock signal is adjusted to the from the second preset value
Three preset values.
Preferably, first preset value is 0.
Preferably, second preset value is 33 ohm.
Preferably, the third preset value is 0 ohm.
The invention also includes a kind of for improving the device of RGMII interface stability, including:
One adjustment unit receives the delay value of the corresponding register of interface clock signal to one first default for adjusting
Value, to improve the serial ports surplus for receiving interface clock signal.
Preferably, the adjustment unit includes:
One setup module, the setting delay value for receiving the corresponding register of interface clock signal to described first are preset
Value；
One adjustment module, connects the setup module, will be series at the resistance value of the resistance for receiving interface clock signal
Third preset value is adjusted to from the second preset value.
Preferably, first preset value is 0.
Preferably, second preset value is 33 ohm.
Preferably, the third preset value is 0 ohm.
Technical solution of the present invention beneficial effect is: provide a kind of method for improving RGMII interface stability and
Device does not have to the problem of improving printed circuit board structure, being able to solve producing line, does not have to replacement chip, can solve bad problem yet,
The workload of doing over again for saving producing line, can be that the bad chip of consistency can be used steadily, further save cost.
Detailed description of the invention
With reference to appended attached drawing, more fully to describe the embodiment of the present invention.However, appended attached drawing be merely to illustrate and
It illustrates, and is not meant to limit the scope of the invention.
Fig. 1 is the tranmitting data register interface clock of the method for improving RGMII interface stability of the embodiment of the present invention
The first waveform figure of signal；
Fig. 2 is the tranmitting data register interface clock of the method for improving RGMII interface stability of the embodiment of the present invention
Second waveform diagram of signal；
Fig. 3 is the reception clock interface clock of the method for improving RGMII interface stability of the embodiment of the present invention
The waveform diagram of signal；
Fig. 4 is the step flow chart of the method for improving RGMII interface stability of the embodiment of the present invention；
Fig. 5 is the step process of the step S1 of the method for improving RGMII interface stability of the embodiment of the present invention
Figure；
Fig. 6 is the functional block diagram of the device for improving RGMII interface stability of the embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art without creative labor it is obtained it is all its
His embodiment, shall fall within the protection scope of the present invention.
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
The present invention will be further explained below with reference to the attached drawings and specific examples, but not as the limitation of the invention.
In the prior art, good plate and bad plate are usually detected using following methods, (1) checks RGMII interface circuit
Schematic diagram and printed circuit board can only exclude RGMII interface circuit in problem present on hardware setting, discovery circuit cabling
It receives interface clock signal and does not wrap ground, may result in reception clock signal and be disturbed, but need to change printed circuit board
It can solve, so never to current producing line solution.
(2) handling capacity that RGMII interface circuit is tested by iperf testing tool, finds the receiving direction or hair of good plate
Send the handling capacity in direction in 900Mbps or more, but the phenomenon that bad plank is each different, therefore, can not pass through test
The handling capacity of RGMII interface circuit judges the stability of RGMII interface.For example, as shown in Table 1, No. 7 printed circuit board hairs
It send the packet loss of clock interface very high, it is very low to receive clock interface handling capacity；No. 2 printed circuit board tranmitting data register interfaces and reception
Clock interface only has 90mbps or so；No. 10 printed circuit board tranmitting data register interface packet-loss rates are not also small, receive clock interface
General 100Mbps or so；No. 429 printed circuit board tranmitting data register interface packet-loss rates are smaller, and receiving clock interface has 300mbps left
It is right.
Table one
(3) the RGMII signal of oscilloscope measurement gigabit Ethernet, discovery tranmitting data register signal and reception clock signal are used
Time all meets the requirement of RTL8211F gigabit Ethernet PHY, preferable in conjunction with second step tranmitting data register signal, but further problems go out
On receiving clock signal, so being tentatively judged as the problem of integrated chip is the reception clock signal of RGMII interface.For example,
As shown in Figure 1, its abscissa indicates time, unit t, ordinate indicates that voltage, unit mV, tranmitting data register interface are set
Setting the time is 1.64nS, meets the requirement of minimum 1.2nS；As shown in Fig. 2, its abscissa indicates the time, unit t is indulged and is sat
Mark indicates voltage, unit mV, and the retention time of tranmitting data register interface is 2.52nS, meets the requirement of minimum 1.2nS；Such as Fig. 3
Shown, abscissa indicates time, unit t, and ordinate indicates that voltage, unit mV receive the TskewT of clock interface
For -0.32nS, meets the needs of TskewT-0.5-+0.5nS.
(4) register of the RGMII interface of integrated chip received on clock interface is adjusted by serial port command, good plate
Window surplus has a 0-3, and bad plate window surplus is 0, i.e., the handling capacity that judgment criteria is received clock signal reach 900Mpbs with
On, it can be deduced that the consistent sex differernce of the RGMII interface of integrated chip, but lead to the RGMII interface of part integrated chip
Interface clock signal operation irregularity is received, the requirement for receiving clock signal is unable to satisfy.
By above four kinds of methods, it can not effectively ensure the window surplus between good plate and bad plate, RGMII can not be improved
The stability of interface solves the problems, such as current volume production also by correcting.
For above-mentioned the above-mentioned problems in the prior art, the present invention includes a kind of stable for improving RGMII interface
The method of property, including:
Step S1, by adjusting receiving the delay value of the corresponding register of interface clock signal to one first preset value, with
Improve the serial ports surplus for receiving interface clock signal.
By above-mentioned for improving the technical solution of the method for RGMII interface stability, as shown in figure 5, the technical solution
To analyze the difference of good plate and bad plate, and reception is adjusted using the adjusting for receiving interface clock signal for integrated circuit board
The delay value of the corresponding register of interface clock signal has ensuring gigabit Ethernet on good plate and bad plate enough remaining
Amount, it is ensured that the stability of gigabit Ethernet RGMII interface.
Further, the serial ports surplus for receiving interface clock signal is referred to receiving clock signal and be received between data-signal
The setting time and retention time surplus, only ensuring to be arranged time and retention time has enough surpluses, just can guarantee letter
Number stability.
Further, the problem of improving printed circuit board structure, being able to solve producing line is not had to using above-mentioned technical method, no
With replacement chip, it also can solve bad problem, save the workload of doing over again of producing line, can be that the bad chip of consistency can be steady
Surely it uses, further saves cost.
In a kind of preferably embodiment, as shown in fig. 6, step S1 includes:
Step S10, adjustment receives the delay value of the corresponding register of interface clock signal to the first preset value；
Step S11, it will be series at and receive the resistance value of the resistance of interface clock signal from the second preset value to be adjusted to third pre-
If value.
Specifically, receive interface clock signal input receive clock signal to integrated circuit board central processing unit it
Afterwards, it is adjusted, can be delayed for clock signal is received, being delayed and being arranged in receives the corresponding deposit of interface clock signal
Device is related, for example, the delay of each ladder is 200pF, when setting register is 0x5, delay will reach 1ns.Herein
The bit [19:16] of register controls and receives clock signal, sets the first preset value for the delay value of register, it is preferred that
First preset value is 0, and the corresponding ladder for receiving clock signal is 0, i.e. not any delay；Similarly, clock signal is received
Ladder when being 1, the value of practical corresponding register is 0x10000, i.e. setting position bit [19:16].
Further, interface clock signal one resistance of series connection is being received, the resistance value of resistance is the second preset value, it is preferred that
Second preset value is 33 ohm, at this point, receiving clock signal default setting is 0x0, since 33 ohm of resistance cause signal to be deposited
It is being delayed, the surplus of part integrated chip is insufficient, the resistance value of resistance is adjusted to third preset value from the second preset value, preferably
, third preset value is 0 ohm, i.e., the resistance value of resistance is adjusted to 0 ohm from 33 ohm, it is less relative to being delayed, it increases
The surplus for receiving clock signal, provides the stability of system.
The invention also includes a kind of for improving the device of RGMII interface stability, including:
One adjustment unit 1 receives the delay value of the corresponding register of interface clock signal to one first default for adjusting
Value, to improve the serial ports surplus for receiving interface clock signal.
By above-mentioned for improving the technical solution of the device of RGMII interface stability, as shown in fig. 6, the technical solution
To analyze the difference of good plate and bad plate, and reception is adjusted using the adjusting for receiving interface clock signal for integrated circuit board
The delay value of the corresponding register of interface clock signal has ensuring gigabit Ethernet on good plate and bad plate enough remaining
Amount, it is ensured that the stability of gigabit Ethernet RGMII interface.Further, do not have to improve printed circuit using above-mentioned technical method
Hardened structure, the problem of being able to solve producing line, do not have to replacement chip, can solve bad problem yet, save the workload of doing over again of producing line,
It can be that the bad chip of consistency can be used steadily, further save cost.
In a kind of preferably embodiment, adjustment unit 1 includes:
One setup module 10, the delay value of the corresponding register of setting reception interface clock signal are excellent to the first preset value
Choosing, the first preset value is 0；
One adjustment module 11, connects setup module 10, will be series at and receive the resistance value of the resistance of interface clock signal from the
Two preset values are adjusted to third preset value, it is preferred that the second preset value is 33 ohm, and third preset value is 0 ohm.
Further, the problem of improving printed circuit board structure, being able to solve producing line is not had to using above-mentioned technical method, no
With replacement chip, it also can solve bad problem, save the workload of doing over again of producing line, can be that the bad chip of consistency can be steady
Surely it uses, further saves cost.
The foregoing is merely preferred embodiments of the present invention, are not intended to limit embodiments of the present invention and protection model
It encloses, to those skilled in the art, should can appreciate that all with made by description of the invention and diagramatic content
Equivalent replacement and obviously change obtained scheme, should all be included within the scope of the present invention.
Claims (10)
1. a kind of method for improving RGMII interface stability characterized by comprising
Step S1, by adjusting the delay value of the corresponding register of reception interface clock signal to one first preset value, to improve
The serial ports surplus for receiving interface clock signal.
2. the method according to claim 1 for improving RGMII interface stability, which is characterized in that the step S1
Include:
Step S10, the delay value for receiving the corresponding register of interface clock signal is adjusted to first preset value；
Step S11, that the resistance value for being series at the resistance for receiving interface clock signal from the second preset value is adjusted to third is pre-
If value.
3. the method according to claim 1 for improving RGMII interface stability, which is characterized in that described first is pre-
If value is 0.
4. the method according to claim 2 for improving RGMII interface stability, which is characterized in that described second is pre-
If value is 33 ohm.
5. the method according to claim 2 for improving RGMII interface stability, which is characterized in that the third is pre-
If value is 0 ohm.
6. a kind of for improving the device of RGMII interface stability characterized by comprising
One adjustment unit receives the delay value of the corresponding register of interface clock signal to one first preset value for adjusting, with
Improve the serial ports surplus for receiving interface clock signal.
7. according to claim 6 for improving the device of RGMII interface stability, which is characterized in that the adjustment is single
Member includes:
The delay value for receiving the corresponding register of interface clock signal is arranged to first preset value in one setup module；
One adjustment module, connects the setup module, will be series at the resistance value of the resistance for receiving interface clock signal from the
Two preset values are adjusted to third preset value.
8. according to claim 6 for improving the device of RGMII interface stability, which is characterized in that described first is pre-
If value is 0.
9. according to claim 7 for improving the device of RGMII interface stability, which is characterized in that described second is pre-
If value is 33 ohm.
10. according to claim 7 for improving the device of RGMII interface stability, which is characterized in that the third is pre-
If value is 0 ohm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910403661.1A CN110188052B (en) | 2019-05-15 | 2019-05-15 | Method and device for improving stability of RGMII interface |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910403661.1A CN110188052B (en) | 2019-05-15 | 2019-05-15 | Method and device for improving stability of RGMII interface |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110188052A true CN110188052A (en) | 2019-08-30 |
| CN110188052B CN110188052B (en) | 2023-07-28 |
Family
ID=67716313
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910403661.1A Active CN110188052B (en) | 2019-05-15 | 2019-05-15 | Method and device for improving stability of RGMII interface |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110188052B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050030110A1 (en) * | 2003-08-07 | 2005-02-10 | Broadcom Corporation | System and method generating a delayed clock output |
| CN1988459A (en) * | 2006-12-29 | 2007-06-27 | 杭州华为三康技术有限公司 | Method and device for communication between processors in network device |
-
2019
- 2019-05-15 CN CN201910403661.1A patent/CN110188052B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050030110A1 (en) * | 2003-08-07 | 2005-02-10 | Broadcom Corporation | System and method generating a delayed clock output |
| CN1988459A (en) * | 2006-12-29 | 2007-06-27 | 杭州华为三康技术有限公司 | Method and device for communication between processors in network device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110188052B (en) | 2023-07-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8130786B2 (en) | Multi-rate backplane transceiver | |
| US9059816B1 (en) | Control loop management and differential delay correction for vector signaling code communications links | |
| CN100568208C (en) | The flexible interface that is used for universal bus test instrument | |
| US6904375B1 (en) | Method and circuits for testing high speed devices using low speed ATE testers | |
| US8939798B2 (en) | Local area networks for intelligent patching system controllers and related methods, controllers and communications interfaces | |
| US8175172B2 (en) | High speed digital galvanic isolator with integrated low-voltage differential signal interface | |
| US6600727B1 (en) | Distributed network repeater system | |
| DE102011082417B4 (en) | ANALOG FRONTEND PROTOCOL CONVERTER/ADAPTER FOR SLPI PROTOCOL | |
| US20030191883A1 (en) | Interface for upgrading serial backplane application from ethernet to gigabit ethernet | |
| EP1842327A2 (en) | Utilization of power delivered to powered device during detection and classification mode | |
| EP1842321A2 (en) | Power sourcing equipment having auto-zero circuit for determining and controlling output current | |
| EP2638673B1 (en) | Adjustable finite impulse response transmitter | |
| CN107168220B (en) | A kind of programmable logic controller (PLC) part and its high speed signal method of reseptance | |
| EP1303100A2 (en) | Interface apparatus | |
| DE102013206124A1 (en) | Differential interface for communication between devices in a battery management and battery protection system | |
| CN108430153A (en) | A kind of data transmission link plate, display module and electronic equipment | |
| CN110188052A (en) | It is a kind of for improving the method and device of RGMII interface stability | |
| CN207896980U (en) | Communication structure and communication system | |
| US8391321B2 (en) | Method and system for patch panel port identification and verification | |
| CN105045744A (en) | High-speed interface | |
| CN108984451B (en) | Signal driving method and communication device | |
| CN103441818B (en) | The detection method of a kind of data transmission fault and device | |
| DE102004046401A1 (en) | Communication system, distribution element and network device | |
| Kempainen | Low-voltage differential signaling (lvds) | |
| CN102684964A (en) | 10-gigabit Ethernet interface card and Ethernet organization method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |