CN1988459A - Method and device for communication between processors in network device - Google Patents
Method and device for communication between processors in network device Download PDFInfo
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- CN1988459A CN1988459A CN 200610156412 CN200610156412A CN1988459A CN 1988459 A CN1988459 A CN 1988459A CN 200610156412 CN200610156412 CN 200610156412 CN 200610156412 A CN200610156412 A CN 200610156412A CN 1988459 A CN1988459 A CN 1988459A
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Abstract
This invention discloses a communication device among processors in network devices including a first MAC controller connected with a first processor and a second MAC controller connected with a second processor, and the first and second MAC controllers have the same medium irrelevant interfaces and the data signal transmission ends of which are connected with the data signal receiving end of the opposite, which realizes that two MAC controllers are mutually connected directly via a medium irrelevant interface and omits the connection of the physical layer in the OSI 7 layer of network structure and two PHT chips.
Description
Technical field
The present invention relates to the network equipment of the computer and the communications field, relate in particular to the device of the communication means between processor in a kind of network equipment and this method of application.
Background technology
In order to adapt to the performance requirement of continuous lifting, in the hardware systems of the network equipment, on the different veneers or use the situation of a plurality of processors more and more in the same veneer, a certain generic task of each processor special disposal coordinates to finish the function of entire equipment mutually between the processor.Therefore, the communication between processor is the basis of hardware systems operation in the network equipment, and its communication speed also is the important step that guarantees this high-performance hardware system.
The integrated MAC that processor in the network equipment has (Media Access Control, medium access control system) controller own, the processor of integrated MAC can not connect mac controller easily yet.Make Ethernet connect like this, connect the method for comparing other as GE (Gigabit Ethemet, gigabit Ethernet), the dual port RAM of mailbox character (Random Access Memory for example, random access storage device), not only have performance advantage, and the sexual clorminance that is easy to get in addition.Therefore, the network connection that utilizes processor to expand realizes that the application mode of high-speed communication between processor is also more and more general.
Fig. 1 is the schematic diagram that communicates to connect between the processor in the prior art, processor 11,12 connect mac controller 21 and 22 by high-speed interface respectively, processor 11 and mac controller 21, high-speed interface between processor 12 and the mac controller 22 can adopt SPI4.2 (System PacketInterface Level 4 Phase 2, system's packet interface 4.2), PCI (Peripheral ComponentInterconnect, peripheral parts interconnected), PCI-X (enhancing pci bus), PCI-E various buses such as (PeripheralComponent Interconnect Express, quick peripheral assembly interconnectings).Mac controller 21,22 connects PHY (physical layer) chip 51 and 52 respectively, adopts the media independent interface between mac controller 21 and PHY chip 51, mac controller 22 and the PHY chip 52.Can adopt gigabit SerDes (Serial and De-Serial between the PHY chip 51 and 52, and string/deserializer) or Copper (copper) interface, because between these two PHY chips is the connection of device interior, do not need to omit the magnetic device and the network port by the external physical port.Like this, processor 11 and 12 can be by connection of the network between the PHY chip and opposite end communicate separately.
The processor of integrated mac controller can be regarded as the combination of processor and mac controller on function, therefore processor 11 and mac controller 21 among Fig. 1, processor 12 and mac controller 22 all can be with the processor replacements of integrated MAC, and the communication mode between two processors is same as described above.
As seen, each processor one end all must be connected with PHY chip two-stage by mac controller and could realize mutually intercommunication in the prior art.Adopt this communication means, the connection more complicated between the processor has not only increased the unreliability of circuit, has more increased the cost of circuit.
Summary of the invention
What the present invention will solve is the low and high problem of cost of the too complicated reliability that causes that communicates to connect between processor in the prior art.
Communicator in the network equipment of the present invention between processor comprises first mac controller that is connected with first processor and second mac controller that is connected with second processor, and first and second mac controllers have identical media independent interface; First mac controller and the data-signal transmitting terminal of second mac controller are connected the other side's data-signal receiving terminal respectively.
Alternatively, described first mac controller and the clock signal transmitting terminal of second mac controller are connected the other side's clock signal receiving terminal respectively.
Alternatively, described first mac controller connects the corresponding control signal receiving terminal of the other side respectively with the control signal transmitting terminal of second mac controller.
Alternatively, described media independent interface is for simplifying gigabit media independent interface RGMII; Described control signal transmitting terminal comprises that transmission enables TXEN, and corresponding control signal receiving terminal is for receiving the effective RXDV of data.
Alternatively, described media independent interface is for simplifying 10 interface RTBI.
Alternatively, the clock signal transmitting terminal of described first mac controller and second mac controller and the connecting line length between the side clock signal receiving terminal surpassed other signal connecting lines satisfies the requirement that data-signal is set up the retention time time of delay of opposite end so that clock signal arrives.
Alternatively, at least one has the clock signal delay module in first and second mac controller, is used for postponing the clock signal of an end in interconnective clock signal transmitting terminal and the receiving terminal, satisfies the requirement that data-signal is set up the retention time its time of delay.
Alternatively, described media independent interface is gigabit media independent interface GMII; Described control signal transmitting terminal comprises that transmission enables TX_EN and sends wrong indication TX_ER, and the control signal receiving terminal of correspondence is respectively and receives the effective RX_DV of data and receive the wrong RX_ER of indication.
Alternatively, described media independent interface is 10 interface TBI; Described clock signal transmitting terminal is tranmitting data register TBC, and described clock signal receiving terminal is receive clock RBC0.
Alternatively, described media independent interface is serial gigabit media independent interface SGMII; Described data-signal transmitting terminal be data-signal difference transmitting terminal TXD+/-, described data-signal receiving terminal be data-signal receiving terminal RXD+/-.
Alternatively, described communicator also comprises the level conversion unit that is connected between first and second mac controller, is used for the transmitting terminal level conversion of first and second mac controller receiving terminal level for the other side.
Preferably, described communicator also comprises the terminal impedance unit, source that is connected between first or second mac controller, the transmitting terminal source terminal impedance that is used for mating first or second mac controller.
Alternatively, described first mac controller is positioned on the different veneers with second mac controller, and connection therebetween is through the connector of described two mac controller place veneers.
Alternatively, the described first processor and first mac controller and/or second processor and second mac controller are integrated into processor chips.
The present invention also provides the communication means between processor in a kind of network equipment, and first mac controller that connects with first processor in the network equipment has identical media independent interface with second mac controller that is connected with second processor, and described method comprises:
First mac controller sends communication data from its data-signal transmitting terminal to the data-signal receiving terminal of second mac controller;
First mac controller is from the communication data of its data-signal receiving terminal reception from the second mac controller data-signal transmitting terminal.
Alternatively, described method also comprises:
First mac controller is from the clock signal receiving terminal tranmitting data register signal of clock signal transmitting terminal to second mac controller;
First mac controller is from the clock signal of clock signal receiving terminal reception from the second mac controller clock signal transmitting terminal.
Alternatively, described method also comprises:
First mac controller transmits control signal from the control signal receiving terminal of control signal transmitting terminal to the second mac controller correspondence;
First mac controller is from the control signal of control signal receiving terminal reception from the second mac controller control signal receiving terminal.
Alternatively, described method also comprises: the clock signal that first mac controller is sent and/or receives is delayed time, and meets the requirement that data-signal is set up the retention time time of delay.
Alternatively, described method also comprises: prolong the connecting line length of clock signal transmitting terminal and the clock signal receiving terminal and second mac controller of first mac controller, make and satisfy time of delay of clock signal the requirement that data-signal is set up the retention time.
The present invention is by the receiving terminal with the direct peer end of the connection mac controller of the transmitting terminal of mac controller, communication at network device internal between the processor is finished at the MAC layer, the PHY chip that no longer needs two ends, simplified communicating to connect between processor, increase connection reliability, reduced the cost of the network equipment simultaneously.
Description of drawings
Fig. 1 is the schematic diagram that communicates to connect between the processor in the prior art;
Fig. 2 is the schematic diagram that communicates to connect between the processor among the present invention;
Fig. 3 is the structure chart of the communicator embodiment one between processor of the present invention;
Fig. 4 is a kind of transmission signal timing diagram of the communicator embodiment one between processor of the present invention;
Fig. 5 is a kind of received signal sequential chart of the communicator embodiment one between processor of the present invention;
Fig. 6 is the structure chart of the communicator embodiment two between processor of the present invention;
Fig. 7 is a kind of transmission and the received signal sequential chart of the communicator embodiment two between processor of the present invention;
Fig. 8 is the structure chart of the communicator embodiment three between processor of the present invention;
Fig. 9 is the structure chart of the communicator embodiment four between processor of the present invention;
Figure 10 is the structure chart of the communicator embodiment five between processor of the present invention;
Figure 11 is the structure chart of the communicator embodiment six between processor of the present invention.
Embodiment
The major function that one skilled in the art will appreciate that the PHY chip is that the MAC layer data is converted to standard compliant physical layer signal, makes it be fit to grow Distance Transmission.But the communication between processor is carried out at same device interior, and the PHY chip does not need light-emitting window or electricity mouth, but directly connects between direct AC coupled or the same level.Therefore for the communicating to connect of device interior, most physical layer function of PHY chip, in some cases even all physical layer function is that inter-processor communication institute is unwanted, and it is redundant that PHY chip role becomes.
Adopt the interconnection of mac controller to realize communication between processor among the present invention with media independent interface, its structural representation as shown in Figure 2, two processors connect mac controller separately respectively, can adopt various bus interface such as SPI4.2, PCI, PCI-X, PCI-E between each processor and the mac controller; Two mac controllers interconnect with the media independent interface; Processor and connected mac controller can be integrated in the chip.Under the certain applications situation, the sequential of PHY chip and level match function are that inter-processor communication is required in the prior art, and these functions can be realized by two mac controllers and connecting circuit therebetween in the present invention.
The media independent interface comprises RGMII (Reduced Gigabit Media Independent Interface, simplify gigabit media independent interface), RTBI (Reduced Ten Bit Interface, simplify 10 interfaces), GMII (Gigabit Media Independent Interface, gigabit media independent interface), TBI (Ten BitInterface, 10 interfaces) and SGMMII (Serial Gigabit Media Independent Interface, serial gigabit media independent interface), in each embodiment, describes the implementation of every kind of interface below in detail.For simplicity, in following embodiment of the present invention, only two mac controllers and syndeton are therebetween described.Need to prove that the mac controller among following each embodiment of the present invention also may be the functional module that is integral to the processor in a chip.
The structure of communicator embodiment one between processor of the present invention as shown in Figure 3, mac controller 31 is connected by the RGMII interface with mac controller 32, is specially: the data-signal transmitting terminal TXD[0:3 of mac controller 31], control signal transmitting terminal TX_CTL and clock signal transmitting terminal TXC respectively with the data-signal receiving terminal RXD[0:3 of mac controller 32], control signal receiving terminal RX_CTL is connected with clock signal receiving terminal RXC; The RXD[0:3 of mac controller 31], RX_CTL and RXC respectively with the TXD[0:3 of mac controller 32], TX_CTL is connected with TXC.
As IEEE (Institute of Electrical and Electronic Engineers, Institute of Electrical and Electric Engineers) a kind of replacement scheme of 802.3z GMII/TBI interface specification, RGMII can finish identical task with 12 pin pins keeping under the compatible fully situation of software view 28 pin pins with 24 pin pins of gmii interface, TBI interface only to taper to.The data width of RGMII is kept to 4 from 8, and all control signals are multiplexed in one the tunnel, and the upper and lower edge of clock signal all is used for sampled data simultaneously.
According to the RGMII interface specification, at the rising edge sampling TX_CTL of TXC, its logical value is represented to send among the GMII and is enabled the TXEN signal; At TXC trailing edge sampling TX_CTL, its logical value is represented the TXERR signal, is the XOR value of TXEN signal and TX_ER signal among the GMII.Similarly, at the rising edge sampling RX_CTL of RXC, its logical value is represented and is received the effective RXDV signal of data among the GMII; At RXC trailing edge sampling RX_CTL, its logical value is represented the RXERR signal, is the XOR value of RXDV signal and RX_ER signal among the GMII.
In the RGMII interface specification, according to the rising edge of RXC and trailing edge sampling RXD[0:3] and during RX_CTL, to RXD[0:3] on data-signal and the control signal on the RX_CTL requirement of setting up the retention time is arranged.In other words, when in the rising edge of RXC or trailing edge sampling, RXD[0:3] on data-signal and the control signal on the RX_CTL should keep the regular hour.But, the rising edge of TXC and trailing edge and TXD[0:3] last data-signal, the foundation of the last control signal of TX_CTL is basically identical constantly, according to the method for attachment among Fig. 3, if the connecting line between mac controller 31 and 32 each pins is at PCB (Printed Circuit Board, printed circuit board (PCB)) track lengths on is basic identical, the RXC that receives of opposite end mac controller then, the also basic and RXD[0:3 of its rising edge and trailing edge] last data-signal, the foundation of the last control signal of RX_CTL is consistent constantly, therefore need to postpone the RXC signal that the receiving terminal mac controller is used for sampling, should make its time of delay the rising edge of RXC signal and trailing edge meet setting up the retention time of stipulating in the RGMII standard.
At least one mac controller has the internal delay time function in the present embodiment, be that at least one mac controller comprises the clock signal delay module, the TXC that this module can generate inside postpones to export behind the certain hour, perhaps, perhaps finish above-mentioned two internal delay time functions simultaneously with being used for carrying out the sampling of data and control signal behind the RXC delay certain hour that receives again.Existing mac controller has has the clock signal delay module.
Can adopt the combination of following three kinds of mac controllers and delay function thereof in the present embodiment:
First kind: mac controller 31 and 32 includes the clock signal delay module, respectively with its TXC signal delay Tdelay time.The transmitting terminal signal sequence of two mac controllers as shown in Figure 4, rising, trailing edge and the TXD[0:3 of mac controller 31 and 32 transmitting terminal internal clock signal TXC], the foundation of TX_CTL signal basically identical constantly; Through the clock delay module internal clock signal TXC is being postponed Tdelay after the time, from the rising of the clock signal TXC of the clock signal transmitting terminal output of mac controller 31 and 32, trailing edge all corresponding to the TXD[0:3 that sets up the TsetupR time], the TX_CTL signal.As long as time of delay, the value of Tdelay can make TsetupR in the span of RGMII interface specification regulation, the mac controller of receiving terminal can correctly be sampled according to the clock signal that is received like this.
Second kind: mac controller 31 and 32 includes the clock signal delay module, respectively with its RXC signal delay Tdelay time.The receiving end signal sequential of two mac controllers as shown in Figure 5, clock signal rising, trailing edge and RXD[0:3 that mac controller 31 and 32 clock signal receiving terminal RXC receive], the foundation of RX_CTL signal basically identical constantly; Through the clock delay module clock signal RXC that is received is being postponed Tdelay after the time, inside in mac controller 31 and 32, the rising of the clock signal RXC that is used for sampling, trailing edge are all corresponding to the RXD[0:3 that sets up the TsetupR time], the RX_CTL signal.Equally, time of delay Tdelay value should be able to make TsetupR in the span of RGMII interface specification regulation, so that the mac controller of receiving terminal is correctly sampled.
The third: have at least one to comprise the clock signal delay module in two mac controllers,, and the clock signal RXC of its reception is postponed Tdelay2 be used further to sampling after the time the internal clocking TXC signal delay Tdelay1 time of this mac controller.Be understood that in conjunction with preceding dual mode, if time of delay Tdelay1 and Tdelay2 satisfy data-signal set up the retention time requirement, the mac controller of opposite end can not start or not have the clock signal delay function, can intercom mutually equally.
To syndeton shown in Figure 3, after the time-delay by clock signal realizes the coupling of signal sequence, mac controller 31 and 32 just can be realized two communications between processor as long as carry out the transmission and the reception of data, control and clock signal according to working method of the prior art.
The structure of communicator embodiment two between processor of the present invention as shown in Figure 6, mac controller 31 is connected by the RGMII interface with mac controller 32, the concrete connected mode of each pin is identical with embodiment one.
Embodiment two with the difference of embodiment one is: the mac controller 31 and 32 among the embodiment two does not start or does not have a clock signal delay module.For the clock signal that makes receiving terminal and the sequential of data-signal are complementary, prolong with the clock signal transmitting terminal TXC of mac controller 31 and 32 and to the connecting line between the side clock signal receiving terminal RXC.The connecting line same length of other signals of same transmission direction between two mac controllers generally, the transmission time of other signals is also basic identical, article two, the prolongation of clock signal connecting line can cause the increase in clock signal transmission time, satisfies the requirement that data-signal is set up the retention time time of delay of clock signal as long as the length of prolongation makes.
The transmission of any one mac controller and receive sequential as shown in Figure 7 among the embodiment two,, the rising of clock signal TXC, trailing edge and TXD[0:3 at transmitting terminal], the foundation of TX_CTL signal basically identical constantly; At receiving terminal, other signals than the identical traffic direction have transmitted the Tdelay time more in the connecting line that prolongs before the receiving terminal because clock signal arrives, and the rising of the clock signal RXC that is received, trailing edge are all corresponding to the RXD[0:3 that sets up the TsetupR time], the RX_CTL signal.Like this, transmitting terminal and receiving terminal all need not clock signal is postponed to handle, and also can carry out correct sampling.
The structure of communicator embodiment three between processor of the present invention as shown in Figure 8, mac controller 81 is connected by the RTBI interface with mac controller 82, is specially: the data-signal transmitting terminal TXD[0:3 of mac controller 81], data-signal transmitting terminal TXD4 and clock signal transmitting terminal TXC respectively with the data-signal receiving terminal RXD[0:3 of mac controller 82], data-signal receiving terminal RXD4 is connected with clock signal receiving terminal RXC; The RXD[0:3 of mac controller 81], RXD4 and RXC respectively with the TXD[0:3 of mac controller 82], TXD4 is connected with TXC.
Similar with the RGMII interface specification, the RTBI pin number is 12 pins equally, but the data bit width of RTBI is 10.The main distinction of RTBI and RGMII interface is that RTBI comprises the codec functions of 8B/10B (position).RTBI and RGMII interface have only the difference of two pins, and RTBI is used as data-signal TXD4 and RXD4 with TX_CTL and the RX_CTL of RGMII.
Identical with the RGMII interface specification, the RTBI interface also has the requirement of setting up the retention time to data-signal, except that not comprising control signal TX_CTL and RX_CTL, the sequential of its signal also with the RGMII basically identical.Therefore, the method that four kinds of delay clock signals among embodiment one and the embodiment two mate sequential relationship between each signal all is applicable to embodiment three, no longer repeats herein.
The structure of communicator embodiment four between processor of the present invention as shown in Figure 9, mac controller 91 and mac controller 92 are connected by gmii interface, are specially: the data-signal transmitting terminal TXD[0:7 of mac controller 91], send wrong indication TX_ER, send enable TX_EN and clock signal transmitting terminal GTX_CLK respectively with the data-signal receiving terminal RXD[0:7 of mac controller 92], receive wrong indication RX_ER, receive the effective RX_DV of data and be connected with clock signal receiving terminal RX_CLK; The RXD[0:7 of mac controller 91], RX_ER, RX_DV and RX_CLK respectively with the TXD[0:7 of mac controller 92], TX_ER, TX_EN be connected with GTX_CLK.Wherein, TX_ER and TX_EN belong to the control signal transmitting terminal, and RX_ER and RX_DV belong to the control signal receiving terminal.
The control signal of the mac controller of gmii interface comprises that also carrier wave detects CRS and collision detection COL, and these two signals are used for and being connected of PHY chip, and network state is detected.Owing to do not have the PHY chip between two mac controllers among the present invention, and monopolize the other side's bandwidth each other, therefore do not need to carry out carrier sense and collision detection, CRS and COL pin ground connection are got final product.
According to the gmii interface standard, the sequential of tranmitting data register GTX_CLK has satisfied the sampling request of receiving terminal to data-signal and control signal, so does not need to carry out the time-delay of clock signal among the embodiment four.After the connection of carrying out according to Fig. 9 between mac controller 91 and 92, send with receiving in existing mode and can carry out communicating by letter between processor.
The structure of communicator embodiment five between processor of the present invention as shown in figure 10, mac controller 101 is connected by the TBI interface with mac controller 102, is specially: the data-signal transmitting terminal TXD[0:9 of mac controller 101], clock signal transmitting terminal TBC respectively with the data-signal receiving terminal RXD[0:9 of mac controller 102], clock signal receiving terminal RBC0 is connected; The RXD[0:9 of mac controller 101], RBC0 respectively with the TXD[0:9 of mac controller 102], TBC is connected.
The TBI interface has increased the 8B/10B codec functions than gmii interface, and its bit wide is 10.Similar with gmii interface, the control signal of the mac controller of TBI interface comprises that carrier wave detects CRS and collision detection COL, these two signals are used for and being connected of PHY chip, and also do not need to carry out carrier sense and collision detection among the embodiment five, as long as with CRS and COL pin ground connection.In addition, the mac controller of TBI interface generally includes optional clock receiving terminal RBC1, and the clock signal receiving terminal can only use RBC0 in embodiment five, to RBC1 can according to the requirement of employing chip with it unsettled or ground connection.
Identical with gmii interface, the sequential of the tranmitting data register TBC of TBI interface has satisfied the sampling request of receiving terminal to data-signal, so does not need to carry out the time-delay of clock signal among the embodiment five.After the connection of carrying out according to Figure 10 between mac controller 101 and 102, send with receiving in existing mode and can carry out communicating by letter between processor.
The structure of communicator embodiment six between processor of the present invention as shown in figure 11, mac controller 111 is connected by the SGMII interface with mac controller 112, is specially: data-signal difference transmitting terminal TXD+, the TXD-of mac controller 111 is connected with data-signal differential received end RXD+, the RXD-of mac controller 112 respectively; The RXD+ of mac controller 111, RXD-are connected with TXD+, the TXD-of mac controller 112 respectively.
The SGMII interface has only data-signal transmitting terminal, receiving terminal and an optional receive clock, and all data and clock adopt differential signal.Because the mac controller of receiving terminal can extract clock from RXD+, RXD-signal, therefore do not use receive clock usually, and only use the transmitting terminal of data-signal just can realize communicating by letter between processor with receiving terminal.
In above-mentioned six embodiment, to adopting the mac controller of different chips, the level of its media independent interface may be different.In this case, need between two mac controllers, increase level conversion unit, the transmission signal of each mac controller, comprise data-signal, control signal and/or clock signal, after through level conversion unit the transmitting terminal level conversion of this mac controller being the receiving terminal level of the other side's mac controller, export the receiving terminal of the other side's mac controller to.
Level conversion unit can be realized in the following ways: one, with CPLD (ComplexProgrammable Logical Device, programmable logic device) realizes, utilize the characteristic of the configurable different voltages of CPLD different B lock (piece) to come switching levels, perhaps the output characteristic of CPLD is set to OC (Open Collector, open collector) or OD (Open Drain, open-drain) characteristic; Its two, on every signal connecting line, use triode or MOS (Metal Oxide Semiconductor, metal-oxide semiconductor (MOS)) pipe to carry out level conversion; Its three, use can tolerate that the chip of transmitting terminal level and receiving terminal level differences drives; Its four, utilize OC or OD output gate carry out level conversion.In addition, can also adopt special level transferring chip.
To the transmitting terminal signal, suitable source terminal impedance helps suppressing the secondary interference of signal.The mac controller that has is integrated active end string resistance in inside, its source terminal impedance can be adjusted to suitable value.To there not being the mac controller of integrated source end string resistance, can be at its signal sending end, comprise that data-signal, control signal and/or clock signal transmitting terminal increase terminal impedance unit, source, the source terminal impedance of its transmitting terminal is matched suitable value, to obtain better signal transmission effect.
Need to prove that among above-mentioned six embodiment, two mac controllers can be positioned on the same veneer, also can be positioned on the different veneers.When two mac controllers were on different veneers, connecting line therebetween need be by the connector on the veneer of place.
To using two mac controllers of the present invention with media independent interface, be without loss of generality, if first mac controller is connected with first processor, second mac controller is connected with second processor, and then first and second processor can be realized and the communicating by letter of the other side by the following method:
First processor is sent to the data of second processor, send from the data-signal receiving terminal of its data-signal transmitting terminal to second mac controller by first mac controller; Second processor is sent to the data of first processor, received from its data-signal receiving terminal by first mac controller, the data that received are from the data-signal transmitting terminal of second mac controller.The mutual method of data-signal that can adopt mac controller with SGMII interface realizes the communication between processor.
To the media independent interface except that SGMII, when transmitting and receive data, also need mutual tranmitting data register and receive clock between first and second mac controller.In other words, first mac controller is also from the clock signal receiving terminal tranmitting data register signal of its clock signal sending end to second mac controller, and receives clock signal from the second mac controller clock signal transmitting terminal from its clock signal receiving end.Mac controller with TBI interface can adopt the mutual method of data-signal and clock signal to realize communicating by letter between processor.
To having the mac controller of RTBI interface, except that carrying out data-signal and clock signal mutual, also need clock signal is delayed time to mate the signal sequence of this interface specification definition.To first mac controller, can adopt following four kinds of methods to come delay clock signals: the tranmitting data register signal to be delayed time, need this moment second mac controller also its tranmitting data register signal to be delayed time; The receive clock signal is delayed time, need this moment second mac controller also its receive clock signal to be delayed time; To send with the receive clock signal and all delay time; To sending and the receive clock signal is not delayed time, this moment, needs second mac controller was with its transmission with make the receive clock signal all delay time.Above-mentioned all delay times should make the regulation that the retention time meets interface specification of setting up of data-signal.
To having first and second mac controllers of RGMII or gmii interface, realize communication between processor except that needing data-signal and control signal mutual, also need to increase and transmit control signal and receive the mutual of control signal.First processor is sent to the control information of second processor, send from the control signal receiving terminal of its control signal transmitting terminal to second mac controller by first mac controller; Second processor is sent to the control information of first processor, received from its control signal receiving terminal by first mac controller, the control information that is received is from the control signal transmitting terminal of second mac controller.
The RGMII interface also needs clock signal is delayed time to mate the signal sequence of this interface specification definition, and the method that delay clock signals can adopt is identical with the RTBI interface.
In addition, the data-signal of various interface, control signal and clock signal are different and different because of interface standard, specifically can no longer repeat referring to six embodiment of aforementioned communication device herein.
Transmitting-receiving sequential characteristics by research media independent interface signal, electrical characteristic etc., to simplify by the scheme of PHY chip interconnect between two mac controllers of prior art among the present invention, realized between two mac controllers direct interconnection by the media independent interface, at OSI (Open SystemInterconnection, open system interconnection) connection of having saved physical layer in the seven layer network structures, two PHY chips have been saved, for the high-speed communication between two processors provides a kind of cost very cheap solution, also increased the reliability of circuit simultaneously.
Above-described embodiment of the present invention does not constitute the qualification to protection range of the present invention.Any modification of being done within the spirit and principles in the present invention, be equal to and replace and improvement etc., all should be included within the claim protection range of the present invention.
Claims (19)
1. the communicator between processor in the network equipment, it is characterized in that: comprise first medium access control system mac controller that is connected with first processor and second mac controller that is connected with second processor, first and second mac controllers have identical media independent interface; First mac controller and the data-signal transmitting terminal of second mac controller are connected the other side's data-signal receiving terminal respectively.
2. the communicator between processor in the network equipment according to claim 1 is characterized in that: described first mac controller and the clock signal transmitting terminal of second mac controller are connected the other side's clock signal receiving terminal respectively.
3. as the communicator between processor in the network equipment as described in the claim 2, it is characterized in that: described first mac controller connects the corresponding control signal receiving terminal of the other side respectively with the control signal transmitting terminal of second mac controller.
4. as the communicator between processor in the network equipment as described in the claim 3, it is characterized in that: described media independent interface is for simplifying gigabit media independent interface RGMII; Described control signal transmitting terminal comprises that transmission enables TXEN, and corresponding control signal receiving terminal is for receiving the effective RXDV of data.
5. as the communicator between processor in the network equipment as described in the claim 2, it is characterized in that: described media independent interface is for simplifying 10 interface RTBI.
6. as the communicator between processor in the network equipment as described in claim 4 or 5, it is characterized in that: the clock signal transmitting terminal of described first mac controller and second mac controller and the connecting line length between the side clock signal receiving terminal surpassed other signal connecting lines, satisfy the requirement that data-signal is set up the retention time time of delay of opposite end so that clock signal arrives.
7. as the communicator between processor in the network equipment as described in claim 4 or 5, it is characterized in that: at least one has the clock signal delay module in first and second mac controller, be used for postponing the clock signal of an end in interconnective clock signal transmitting terminal and the receiving terminal, satisfy the requirement that data-signal is set up the retention time its time of delay.
8. as the communicator between processor in the network equipment as described in the claim 3, it is characterized in that: described media independent interface is gigabit media independent interface GMII; Described control signal transmitting terminal comprises that transmission enables TX_EN and sends wrong indication TX_ER, and the control signal receiving terminal of correspondence is respectively and receives the effective RX_DV of data and receive the wrong RX_ER of indication.
9. as the communicator between processor in the network equipment as described in the claim 2, it is characterized in that: described media independent interface is 10 interface TBI; Described clock signal transmitting terminal is tranmitting data register TBC, and described clock signal receiving terminal is receive clock RBC0.
10. the communicator between processor in the network equipment according to claim 1, it is characterized in that: described media independent interface is serial gigabit media independent interface SGMII; Described data-signal transmitting terminal be data-signal difference transmitting terminal TXD+/-, described data-signal receiving terminal be data-signal receiving terminal RXD+/-.
11. as the communicator between processor in the network equipment as described in any one of the claim 1 to 3, it is characterized in that: described communicator also comprises the level conversion unit that is connected between first and second mac controller, is used for the transmitting terminal level conversion of first and second mac controller receiving terminal level for the other side.
12. as the communicator between processor in the network equipment as described in any one of the claim 1 to 3, it is characterized in that: described communicator also comprises the terminal impedance unit, source that is connected between first or second mac controller, the transmitting terminal source terminal impedance that is used for mating first or second mac controller.
13. as the communicator between processor in the network equipment as described in any one of the claim 1 to 3, it is characterized in that: described first mac controller is positioned on the different veneers with second mac controller, and connection therebetween is through the connector of described two mac controller place veneers.
14. as the communicator between network equipment processor as described in any one of the claim 1 to 3, it is characterized in that: the described first processor and first mac controller and/or second processor and second mac controller are integrated into processor chips.
15. the communication means in the network equipment between processor is characterized in that, first mac controller that connects with first processor has identical media independent interface with second mac controller that is connected with second processor, and described method comprises:
First mac controller sends communication data from its data-signal transmitting terminal to the data-signal receiving terminal of second mac controller;
First mac controller is from the communication data of its data-signal receiving terminal reception from the second mac controller data-signal transmitting terminal.
16. the communication means as in the network equipment as described in the claim 15 is characterized in that described method also comprises:
First mac controller is from the clock signal receiving terminal tranmitting data register signal of clock signal transmitting terminal to second mac controller;
First mac controller is from the clock signal of clock signal receiving terminal reception from the second mac controller clock signal transmitting terminal.
17. the communication means as in the network equipment as described in the claim 16 is characterized in that described method also comprises:
First mac controller transmits control signal from the control signal receiving terminal of control signal transmitting terminal to the second mac controller correspondence;
First mac controller is from the control signal of control signal receiving terminal reception from the second mac controller control signal receiving terminal.
18. the communication means as in the network equipment as described in claim 16 or 17 is characterized in that described method also comprises: the clock signal that first mac controller is sent and/or receives is delayed time, and meets the requirement that data-signal is set up the retention time time of delay.
19. as the communication means in the network equipment as described in claim 16 or 17, it is characterized in that, described method also comprises: prolong the connecting line length of clock signal transmitting terminal and the clock signal receiving terminal and second mac controller of first mac controller, make and satisfy time of delay of clock signal the requirement that data-signal is set up the retention time.
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| CNB200610156412XA CN100477586C (en) | 2006-12-29 | 2006-12-29 | Method and device for communication between processors in network device |
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| CNB200610156412XA CN100477586C (en) | 2006-12-29 | 2006-12-29 | Method and device for communication between processors in network device |
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| CN100477586C CN100477586C (en) | 2009-04-08 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105045744A (en) * | 2015-08-12 | 2015-11-11 | 上海斐讯数据通信技术有限公司 | High-speed interface |
| WO2017059822A1 (en) * | 2015-10-08 | 2017-04-13 | 深圳市中兴微电子技术有限公司 | Inter-chip communication method, system and computer storage medium |
| CN110188052A (en) * | 2019-05-15 | 2019-08-30 | 晶晨半导体(上海)股份有限公司 | It is a kind of for improving the method and device of RGMII interface stability |
| CN112291126A (en) * | 2020-10-23 | 2021-01-29 | 成都天锐星通科技有限公司 | Bus communication system, data transmission method and data reception method |
| CN114500408A (en) * | 2022-01-13 | 2022-05-13 | 中汽创智科技有限公司 | Ethernet switching device, data processing device and vehicle |
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2006
- 2006-12-29 CN CNB200610156412XA patent/CN100477586C/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105045744A (en) * | 2015-08-12 | 2015-11-11 | 上海斐讯数据通信技术有限公司 | High-speed interface |
| WO2017059822A1 (en) * | 2015-10-08 | 2017-04-13 | 深圳市中兴微电子技术有限公司 | Inter-chip communication method, system and computer storage medium |
| CN106571903A (en) * | 2015-10-08 | 2017-04-19 | 深圳市中兴微电子技术有限公司 | Communication method and system between chips |
| CN110188052A (en) * | 2019-05-15 | 2019-08-30 | 晶晨半导体(上海)股份有限公司 | It is a kind of for improving the method and device of RGMII interface stability |
| CN112291126A (en) * | 2020-10-23 | 2021-01-29 | 成都天锐星通科技有限公司 | Bus communication system, data transmission method and data reception method |
| CN114500408A (en) * | 2022-01-13 | 2022-05-13 | 中汽创智科技有限公司 | Ethernet switching device, data processing device and vehicle |
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| Publication number | Publication date |
|---|---|
| CN100477586C (en) | 2009-04-08 |
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