CN110187737B - Board card power-off time sequence control device - Google Patents
Board card power-off time sequence control device Download PDFInfo
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- CN110187737B CN110187737B CN201910401285.2A CN201910401285A CN110187737B CN 110187737 B CN110187737 B CN 110187737B CN 201910401285 A CN201910401285 A CN 201910401285A CN 110187737 B CN110187737 B CN 110187737B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
Abstract
The application provides a board power-off timing sequence control device, which comprises a power supply module, a power supply detection module, a CPLD module and a plurality of power supply chip modules, wherein the CPLD module is respectively connected with the power supply detection module and the plurality of power supply chip modules, and the power supply modules are respectively used for supplying power to the CPLD module and the plurality of power supply chip modules; the power supply detection module is used for detecting whether the voltage of the power supply module drops to a preset voltage threshold value or not, and sending a power supply module voltage abnormal signal to the CPLD module if the voltage of the power supply module drops to the preset voltage threshold value; the CPLD module is used for receiving the power supply module voltage abnormal signal sent by the power supply detection module, and sequentially powering down each power supply chip module according to a power down instruction stored locally under the condition of receiving the power supply module voltage abnormal signal sent by the power supply detection module.
Description
Technical Field
The application relates to the technical field of communication, in particular to a board card power-off time sequence control device.
Background
Currently, a board card designed according to a large-scale integrated circuit including a CPU generally includes a plurality of power chips. In the board card, not only are strict requirements on parameters such as voltage of the power supply chips, but also the power-up and power-down time sequence among the power supply chips is also strict requirements, namely, the power supply chips are controlled to be powered up and powered down according to a specific sequence.
When the board card in the network equipment needs to be debugged, the problem of hot plug is inevitably encountered. When the board card is inserted into a certain slot position of the network equipment, the power-on process among the power chips on the board card is controllable, and the power-on process can be responded through the existing hot plug technology; however, when the board card is pulled out from a certain slot of the network device, the power-down process between the power chips on the board card is uncontrollable.
Therefore, a time sequence control chip is newly added on the board card, and the power-on and power-off time sequences of each power supply chip on the board card are controlled by the enabling signals sent by the time sequence control chip, and the method specifically comprises the following steps: and receiving a power-up and power-down command sent by the main control board card, and sequentially powering up and down each power supply chip on the board card according to the power-up and power-down command. However, in practical applications the following two situations often occur: 1. hot plugging of the board card; 2. the external power supply is turned off. Under above-mentioned two kinds of circumstances, the time sequence control chip all can't normally work, can not realize going down the electricity to each power chip according to the preface execution, has increased the risk that the device damaged on the integrated circuit board.
Disclosure of Invention
In view of this, the present application provides a board power-down timing control apparatus.
Specifically, the method is realized through the following technical scheme:
a board card power-off time sequence control device is characterized by comprising a power supply module, a power supply detection module, a CPLD module and a plurality of power supply chip modules, wherein the CPLD module is respectively connected with the power supply detection module and the plurality of power supply chip modules, and the power supply modules are respectively used for supplying power to the CPLD module and the plurality of power supply chip modules;
the power supply detection module is used for detecting whether the voltage of the power supply module drops to a preset voltage threshold value or not, and sending a power supply module voltage abnormal signal to the CPLD module if the voltage of the power supply module drops to the preset voltage threshold value;
the CPLD module is used for receiving the power supply module voltage abnormal signal sent by the power supply detection module, and sequentially powering down each power supply chip module according to a power down instruction stored locally under the condition of receiving the power supply module voltage abnormal signal sent by the power supply detection module.
Further, the power module specifically includes: the circuit board comprises a board input power supply submodule and a board local power supply submodule, wherein the board local power supply submodule is connected with the board input power supply submodule through a hot plug controller, and the voltage of the board local power supply submodule is obtained by converting the voltage of the board input power supply submodule through the hot plug controller; the power supply detection module specifically comprises: and the board card input power supply detection submodule and the board card local power supply detection submodule.
Further, the power module is respectively configured to supply power to the CPLD module and the plurality of power chip modules, specifically:
the board card local power supply sub-module is respectively used for supplying power to the CPLD module and the plurality of power supply chip modules.
Further, the power supply sub-module of the board card local power supply is configured to supply power to the CPLD module, specifically:
the board card local power supply submodule is used for supplying power to the LDO module, the LDO module is used for supplying power to the CPLD module, and the LDO module is respectively connected with the board card local power supply submodule and the CPLD module.
Further, the power detection module is configured to detect whether the voltage of the power module drops to a preset voltage threshold, and if the voltage of the power module drops to the preset voltage threshold, sending a power module voltage abnormal signal to the CPLD module specifically includes:
the board input power supply detection submodule is used for detecting whether the voltage of the board input power supply submodule falls to a preset voltage threshold value or not, and if the voltage of the board input power supply submodule falls to the preset voltage threshold value, sending a power supply module voltage abnormal signal to the CPLD module;
the board card local power supply detection submodule is used for detecting whether the voltage of the board card local power supply submodule falls to a preset voltage threshold value or not, and if the voltage of the board card local power supply submodule falls to the preset voltage threshold value, a power supply module voltage abnormity signal is sent to the CPLD module.
Further, the CPLD module is configured to receive a power module voltage abnormality signal sent by the power detection module, and when receiving the power module voltage abnormality signal sent by the power detection module, sequentially powering down each power chip module according to a power-down instruction stored locally specifically includes:
the CPLD module is used for receiving a power module voltage abnormal signal sent by the board input power detection submodule, and sequentially powering down each power chip module according to a power down instruction stored locally under the condition of receiving the power module voltage abnormal signal sent by the board input power detection submodule;
or
The CPLD module is used for receiving a power module voltage abnormal signal sent by the board card local power supply detection submodule, and sequentially powering down each power chip module according to a power-down instruction stored locally under the condition of receiving the power module voltage abnormal signal sent by the board card local power supply detection submodule.
Further, the apparatus further comprises:
the board on-site signal detection module is connected with the backplane connector in a short pin mode;
the board on-position signal detection module is used for detecting whether the board on-position signal changes, and if the board on-position signal changes, the CPLD module is informed that the board on-position signal changes;
and the CPLD module sequentially powers down each power chip module according to the power-down instruction stored locally.
Further, the power-off instruction is a power-off instruction issued by the main control board card.
According to the board card power-off sequential control device provided by the embodiment of the application, the CPLD is used for controlling the power chip modules to be powered off sequentially, so that the board card can still keep powering off the power chips sequentially under the condition that a hot plug or an external power supply is turned off, and the risk of damage to devices on the board card is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the description of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art according to the drawings.
FIG. 1 is a schematic diagram illustrating a card internal hardware connection according to an exemplary embodiment of the present application;
fig. 2 is a schematic diagram of another internal hardware connection of a board card according to an exemplary embodiment of the present application;
fig. 3 is a schematic diagram of another internal hardware connection of a board card according to an exemplary embodiment of the present application.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
As shown IN fig. 1, which is a schematic diagram of an internal hardware structure of a conventional board, the board is powered by an external power supply (e.g., 12V-IN), and the external power supply (e.g., 12V-IN) is converted into an internal Main power supply (e.g., 12V-Main) of the board through a hot plug controller (e.g., a hot plug controller LTC 4215). The Main power supply 12V-Main is used for supplying power to each power supply chip and the time sequence control chip, the power-on and power-off time sequence of each power supply chip on the board card is controlled by an Enable signal (Enable) issued by the time sequence control chip, and the method specifically comprises the following steps: and receiving a power-up and power-down instruction sent by the main control board card, and sequentially powering up and down each power supply chip on the board card according to the power-up and power-down instruction.
The main control board card sends a power-up and power-down instruction, and the software controls each power supply chip to be powered up and down in sequence. However, in practical applications, the following two situations are often encountered: 1. hot plugging of the board card; 2. the external power supply is turned off. Under above-mentioned two kinds of circumstances, the time sequence control chip all can't normally work, can not realize going down the electricity to each power chip according to the preface execution, has increased the risk that the device damaged on the integrated circuit board.
In view of the above technical problems, in the embodiments of the present application, energy storage capacitors on board cards are measured, a large number of energy storage capacitors exist on a general board card, and when a board card is hot plugged or an external power supply is turned off, due to an energy storage effect of the energy storage capacitors on the board card, a Main power supply voltage (for example, 12V-Main) cannot instantly drop to 0V, but slowly drops to 0V following a voltage drop curve. The time that this process takes is on the order of tens of milliseconds, thus providing the possibility of controlling the power down of the individual power chips in sequence before the Main power supply voltage (e.g., 12V-Main) drops to 0V.
Based on this, an embodiment of the present application provides a device for controlling a power-down sequence of a board, as shown in fig. 2, which is a schematic diagram of an internal hardware structure of the board in the embodiment of the present application, and includes a power module 210, a power detection module 220, a CPLD module 230, and a plurality of power chip modules (240A, 240B, … …).
In the embodiment of the present application, a CPLD (Complex Programmable Logic Device) is used to replace the existing timing control chip, for example, a CPLD of LCMXO2 series, which is characterized by a low normal operating voltage of only 1.2V, can be used.
The power module 210 is used for supplying power to the CPLD module 230 and the plurality of power chip modules, and the CPLD module 230 is connected to the power detection module 220 and the plurality of power chip modules. For example, the CPLD module 230 and the plurality of power chip modules are connected by an Enable signal line.
The power detection module 220 is configured to detect whether the voltage of the power module 210 drops to a preset voltage threshold, and send a power module 210 voltage anomaly signal to the CPLD module 230 if the voltage of the power module 210 drops to the preset voltage threshold. For example, the normal voltage of the power module 210 is 12V, the preset voltage threshold may be 10V in the actual application process, and when the voltage 12V of the power module 210 drops to the preset voltage threshold of 10V, the power module 210 voltage abnormal signal is sent to the CPLD module 230.
The CPLD module 230 is configured to receive the power module 210 voltage abnormal signal sent by the power detection module 220, and sequentially power down each power chip module according to a power down instruction stored locally when receiving the power module 210 voltage abnormal signal sent by the power detection module 220.
As shown IN fig. 3, which is a schematic diagram of an internal hardware structure of another board IN the embodiment of the present disclosure, the power module 210 includes a board input power sub-module 210A (e.g., 12V-IN) and a board local power sub-module 210B (e.g., 12V-Main), the board local power sub-module 210B is connected to the board input power sub-module 210A through a hot plug controller (e.g., a hot plug controller LTC4215), and a voltage of the board local power sub-module 210B is obtained by converting a voltage of the board input power sub-module 210A through the hot plug controller. The power supply module 210 is respectively configured to supply power to the CPLD module 230 and the plurality of power supply chip modules, specifically, the board local power supply sub-module 210B is respectively configured to supply power to the CPLD module 230 and the plurality of power supply chip modules.
In order to better prolong the operating time of the CPLD module 230, in the embodiment of the present application, an LDO (Low-dropout regulator, also called a Low-dropout linear regulator or a Low-dropout regulator, which is one of linear dc regulators, and is used to provide a stable dc voltage, compared to a general linear dc regulator, a Low-dropout regulator can operate under a smaller input/output voltage difference) chip is further introduced, and the LDO chip is selected as a power supply of the CPLD, so that the board local power supply sub-module 210B is used to supply power to the CPLD module 230, specifically: the board local power supply sub-module 210B is configured to supply power to the LDO module 250, and the LDO module 250 is configured to supply power to the CPLD module 230, where the LDO module 250 is connected to the board local power supply sub-module 210B and the CPLD module 230, respectively, and the LDO module 250 is used as a connection medium between the board local power supply sub-module 210B and the CPLD module 230.
The reason for introducing the LDO chip is briefly introduced here: the LDO chip is used as a voltage reduction linear voltage-stabilized power supply and can work as long as the input voltage is about 0.2V higher than the output voltage. Therefore, in the process that the voltage of the board local power supply sub-module 210B (for example, 12V-Main) drops to 0V, the CPLD can normally operate as long as the voltage of the board local power supply sub-module 210B is greater than 1.4V. Therefore, the working time of the CPLD is greatly prolonged, and the CPLD can normally control the power-off sequence of each power supply chip under the condition that the board card is subjected to hot plug or the external power supply is turned off. In addition, the LDO chip has the other characteristic that the output voltage can be basically ensured to be stable and unchanged when the input voltage changes, and the normal and stable work of the CPLD is guaranteed. When the CPLD works, the CPLD is only used for power supply time sequence control, and the current is in the level of dozens of milliamperes, so that the power consumption consumed by the LDO is only hundreds of milliwatts, and large power consumption loss can not be caused.
The power supply module 210 includes a board input power supply sub-module 210A (e.g., 12V-IN) and a board local power supply sub-module 210B (e.g., 12V-Main), and similarly, the power supply detection module 220 includes a board input power supply detection sub-module 220A and a board local power supply detection sub-module 220B. The CPLD module 230 is connected to the power detection module 220, specifically to the board input power detection submodule 220A and the board local power detection submodule 220B, respectively.
The power detection module 220 is configured to detect whether the voltage of the power module 210 drops to a preset voltage threshold, and send a power module 210 voltage anomaly signal to the CPLD module 230 if the voltage of the power module 210 drops to the preset voltage threshold, specifically: the board input power detection submodule 220A (e.g., 12V-IN-Check) is configured to detect whether a voltage (e.g., 12V-IN) of the board input power submodule 210A falls below a preset voltage threshold (e.g., the voltage threshold may be set to 10V IN an actual use process), and send a power module 210 voltage abnormality signal to the CPLD module 230 if the voltage of the board input power submodule 210A falls below the preset voltage threshold; the board local power detection sub-module 220B (e.g., 12V-Main-Check) is configured to detect whether a voltage (e.g., 12V-Main) of the board local power sub-module 210B falls below a preset voltage threshold, and send a power module 210 voltage abnormality signal to the CPLD module 230 if the voltage of the board local power sub-module 210B falls below the preset voltage threshold.
The CPLD module 230 is configured to receive the power module 210 voltage abnormal signal sent by the power detection module 220, and sequentially power down each power chip module according to a power down instruction stored locally when receiving the power module 210 voltage abnormal signal sent by the power detection module 220, specifically: the CPLD module 230 is configured to receive a power module 210 voltage abnormal signal sent by the board input power detection submodule 220A (e.g., 12V-IN-Check), and sequentially power down each power chip module according to a power down instruction stored locally when receiving the power module 210 voltage abnormal signal sent by the board input power detection submodule 220A;
or
The CPLD module 230 is configured to receive a power module 210 voltage abnormality signal sent by the board local power detection submodule 220B (e.g., 12V-Main-Check), and sequentially power down each power chip module according to a power down instruction stored locally when receiving the power module 210 voltage abnormality signal sent by the board local power detection submodule 220B.
On the basis of the above device, the device for controlling the power-off timing of the board card in the embodiment of the present application may further include: and the board card on-site signal detection module 260 is connected with the backplane connector in a short pin mode by the board card on-site signal detection module 260. The board in-place signal detection module 260 is configured to detect whether a board in-place signal changes, where if the board is pulled out in an electrified manner, the short pin is firstly separated from the backplane connector, so that the board in-place signal changes; if the board on-position signal changes, the CPLD module 230 is notified that the board on-position signal changes; the CPLD module 230 powers down each power chip module in sequence according to the locally stored power down instruction.
In the embodiment of the present application, normally, software in the prior art is still used to control each power chip to power up and power down in sequence, where the power down instruction may be a power down instruction issued by the main control board.
According to the board card power-off sequential control device provided by the embodiment of the application, the CPLD is used for controlling the power chip modules to be powered off sequentially, so that the board card can still keep powering off the power chips sequentially under the condition that a hot plug or an external power supply is turned off, and the risk of damage to devices on the board card is reduced.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.
Claims (8)
1. A board card power-off time sequence control device is characterized by comprising a power supply module, a power supply detection module, a CPLD module and a plurality of power supply chip modules, wherein the CPLD module is respectively connected with the power supply detection module and the plurality of power supply chip modules, and the power supply modules are respectively used for supplying power to the CPLD module and the plurality of power supply chip modules;
the power supply detection module is used for detecting whether the voltage of the power supply module falls to a preset voltage threshold value or not, and sending a power supply module voltage abnormal signal to the CPLD module if the voltage of the power supply module falls to the preset voltage threshold value due to board card hot plugging or external power supply closing;
the energy storage capacitor is arranged on the board card, and under the condition that the board card is subjected to hot plugging or an external power supply is turned off, the voltage of the power supply module is reduced along a voltage reduction curve due to the energy storage effect of the energy storage capacitor on the board card, so that the power supply chip modules are sequentially powered off before the voltage of the power supply module is reduced to 0V;
the CPLD module is used for receiving the power supply module voltage abnormal signal sent by the power supply detection module, and sequentially powering down each power supply chip module according to a power down instruction stored locally under the condition of receiving the power supply module voltage abnormal signal sent by the power supply detection module.
2. The device of claim 1, wherein the power module comprises a board input power submodule and a board local power submodule, the board local power submodule and the board input power submodule are connected through a hot plug controller, and the board local power submodule voltage is obtained by converting the board input power submodule voltage through the hot plug controller;
the power supply detection module comprises a board card input power supply detection submodule and a board card local power supply detection submodule.
3. The apparatus according to claim 2, wherein the power module is configured to supply power to the CPLD module and the plurality of power chip modules, respectively, and includes:
the board card local power supply sub-module is respectively used for supplying power to the CPLD module and the plurality of power supply chip modules.
4. The apparatus of claim 3, wherein the board local power supply sub-module is configured to supply power to the CPLD module, and comprises:
the board card local power supply submodule is used for supplying power to the LDO module, the LDO module is used for supplying power to the CPLD module, and the LDO module is respectively connected with the board card local power supply submodule and the CPLD module.
5. The apparatus of claim 2, wherein the power detection module is configured to detect whether the voltage of the power module drops to a preset voltage threshold, and send a power module voltage anomaly signal to the CPLD module if the voltage of the power module drops to the preset voltage threshold, and the power detection module includes:
the board input power supply detection submodule is used for detecting whether the voltage of the board input power supply submodule falls to a preset voltage threshold value or not, and if the voltage of the board input power supply submodule falls to the preset voltage threshold value, sending a power supply module voltage abnormal signal to the CPLD module;
the board card local power supply detection submodule is used for detecting whether the voltage of the board card local power supply submodule falls to a preset voltage threshold value or not, and if the voltage of the board card local power supply submodule falls to the preset voltage threshold value, a power supply module voltage abnormity signal is sent to the CPLD module.
6. The apparatus according to claim 5, wherein the CPLD module is configured to receive a power module voltage anomaly signal sent by the power detection module, and sequentially power down each power chip module according to a locally stored power down command when receiving the power module voltage anomaly signal sent by the power detection module, and includes:
the CPLD module is used for receiving a power module voltage abnormal signal sent by the board input power detection submodule, and sequentially powering down each power chip module according to a power down instruction stored locally under the condition of receiving the power module voltage abnormal signal sent by the board input power detection submodule;
or
The CPLD module is used for receiving a power module voltage abnormal signal sent by the board card local power supply detection submodule, and sequentially powering down each power chip module according to a power-down instruction stored locally under the condition of receiving the power module voltage abnormal signal sent by the board card local power supply detection submodule.
7. The apparatus of any one of claims 1 to 6, further comprising:
the board on-site signal detection module is connected with the backplane connector in a short pin mode;
the board on-position signal detection module is used for detecting whether the board on-position signal changes, and if the board on-position signal changes, the CPLD module is informed that the board on-position signal changes;
and the CPLD module sequentially powers down each power chip module according to the power-down instruction stored locally.
8. The apparatus of claim 1, wherein the power-down command is a power-down command issued by the main control board.
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| CN110750378A (en) * | 2019-09-30 | 2020-02-04 | 山东信通电子股份有限公司 | Multi-power-supply power-off sequential circuit and power-off method |
| CN111443652B (en) * | 2020-03-24 | 2021-06-18 | 深圳市紫光同创电子有限公司 | Power supply structure of CPLD (complex programmable logic device) logic unit array |
| CN112731860A (en) * | 2020-12-11 | 2021-04-30 | 邦彦技术股份有限公司 | VPX blade power-on control method and circuit and VPX blade |
| CN113835510A (en) * | 2021-09-27 | 2021-12-24 | 新华三信息安全技术有限公司 | Power supply control method and system |
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| US6924486B2 (en) * | 2002-10-03 | 2005-08-02 | Schick Technologies, Inc. | Intraoral sensor having power conservation features |
| CN103209097B (en) * | 2013-04-03 | 2016-06-29 | 大唐移动通信设备有限公司 | A kind of communication equipment and power fail warning method thereof |
| CN105045366B (en) * | 2015-07-01 | 2019-01-15 | 湖南汽车工程职业学院 | A kind of more device for managing and controlling electrical source of processor, system and method |
| CN206515780U (en) * | 2017-02-15 | 2017-09-22 | 深圳市恒扬数据股份有限公司 | Control circuit and control device for the power-on and power-off sequential of hardware board |
| CN208157017U (en) * | 2018-06-06 | 2018-11-27 | 烽火通信科技股份有限公司 | The control circuit and device of electric timing under a kind of board |
| CN109582498A (en) * | 2018-11-22 | 2019-04-05 | 郑州云海信息技术有限公司 | Data protection circuit and guard method when a kind of CPLD powered-off fault |
| CN109710046B (en) * | 2018-12-12 | 2022-03-01 | 杭州迪普科技股份有限公司 | Frame type equipment service board power-on and power-off control system, method and device and main control board |
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