CN110166054A - A kind of sigma-delta modulator of not incoming clock signal - Google Patents
A kind of sigma-delta modulator of not incoming clock signal Download PDFInfo
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- CN110166054A CN110166054A CN201910377879.4A CN201910377879A CN110166054A CN 110166054 A CN110166054 A CN 110166054A CN 201910377879 A CN201910377879 A CN 201910377879A CN 110166054 A CN110166054 A CN 110166054A
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- quantizer
- sigma
- signal
- comparator
- output signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
- H03M3/462—Details relating to the decimation process
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
- H03M3/464—Details of the digital/analogue conversion in the feedback path
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
- H03M3/494—Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems
- H03M3/496—Details of sampling arrangements or methods
Abstract
The present invention relates to a kind of sigma-delta modulators of not incoming clock signal, belong to modulus circuit field.The sigma-delta modulator includes reverse phase adder, the quantizer of integrator and not incoming clock signal, the reverse phase adder, integrator and quantizer are sequentially connected composition forward path, digital analog converter (DAC) is connect with quantizer and reverse phase adder respectively, forms feedback channel；The sigma-delta modulator output pulse signal is a string of low data streams after being sent into microprocessor, carries out filtering extraction again after Homogenization Treatments, obtains the output of high position data stream.Use the modulator, sigma-delta ADC over-sampling rate can be improved using the high frequency clock of microprocessor, the limitation for making the raising of over-sampling rate be no longer influenced by analog circuit can obtain higher signal-to-noise ratio under quantizer digit and the identical situation of modulator order.
Description
Technical field
The invention belongs to modulus circuit field, in particular to a kind of sigma-delta modulator of not incoming clock signal.
Background technique
The signal of simulation field and digital field is needed through analog-digital converter (Analog to Digital
Converter, ADC) it is connected as medium.Sigma-delta ADC belongs to over-sampling type ADC, has high resolution, quantizing noise
Rejection ability is strong, hardware size is small and is easy to the advantages that integrating with digital display circuit, can improve quantization by increasing over-sampling rate
Precision.
The signal-to-noise ratio of sigma-delta ADC is mainly determined by sigma-delta modulator, is adopted with quantizer digit, modulator order and mistake
Sample rate is directly proportional.But the linearity of multiple position quantizer is bad, and will increase the complexity of circuit structure, it is general to use 1
Quantizer design (design [D] the Harbin Institute of Technology of .24 48KSPS multilevel quantization sigma-delta ADC of Hu Yaqin,
2016.).The increase of modulator order can bring the unstable or non-ideal of increase, the circuit itself of Analog Circuit Design difficulty
(Lin Jianpeng, Li Kaihang high-order cascade multidigit sigma-delta modulator Simulink design of Simulation [J] hyundai electronics for the influence of factor
Technology, 2012,35 (18): 142-145.).In contrast, over-sampling rate is improved to be easier to realize.Then, over-sampling
The raising of rate depends on the raising of clock signal frequency in modulator, due to being limited by analog circuit technique, is difficult
Reach very high degree.
Compare analog circuit, and Digital Electronic Technique is in the stage of high speed development, and high frequency microprocessor product is continuous
It emerges in large numbers, brings new power for the research of sigma-delta ADC.
Summary of the invention
The present invention mentions aiming at the problem that raising of over-sampling rate in sigma-delta ADC in the prior art is limited by analog circuit
The sigma-delta modulator for having gone out a kind of not incoming clock signal, counts in the pulse signal exported with microprocessor to modulator
It, then can be in quantizer digit and modulator order according to the high frequency clock for exceeding modulator circuit ability to bear when according to capture
Number under the same conditions, reaches higher ADC over-sampling rate, to improve signal-to-noise ratio.
In order to achieve the above objectives, present inventive concept is as follows:
The present invention modifies the structure of quantizer on the basis of original sigma-delta modulator, not using two reference voltages
With comparator and one not incoming clock signal d type flip flop realize quantization effect.The pulse signal of the modulator output
The high frequency clock that can use microprocessor is quantified as low data stream, the raising of over-sampling rate it is unrelated with analog circuit and with institute
It is directly related to state clock frequency.In addition, 1/0 difference integrated distribution in the data flow, is taken out again after can first homogenizing
Filtering is taken, high position data stream is obtained.
According to above-mentioned design, the present invention adopts the following technical scheme:
A kind of sigma-delta modulator of not incoming clock signal, including reverse phase adder, integrator and not incoming clock signal
Quantizer, the reverse phase adder, integrator and quantizer are sequentially connected composition forward path, digital analog converter (DAC) point
It is not connect with quantizer and reverse phase adder, forms feedback channel；The output pulse signal V of the sigma-delta modulatorOUTArteries and veins
Rush density and input signal VINVoltage swing it is directly proportional, and output pulse signal VOUTLow data is captured as by microprocessor
Stream, each pulse period corresponding data flow are to be constituted by continuous 1 plus continuous 0.
The quantizer includes two different first comparators of reference voltage in parallel and the second comparator and one
The not d type flip flop of incoming clock signal, the d type flip flop connection first comparator and the second comparator；The first comparator
Reference voltage VUPGreater than the reference voltage V of the second comparatorDOWN；The input signal V of quantizerINT, by first comparator
Output signal is VSD, the output signal by the second comparator is VRD, output signal VSDWith output signal VRDIt is separately input to D
TriggerWithEnd, directly controls d type flip flop in the state of ignoring external clockThe output signal V at endOUT,
Output signal VOUTThe output signal of namely entire quantizer.
There is no incoming clock signal, output signal V in sigma-delta modulator provided by the inventionOUTThe variation of middle low and high level
Speed is slower than the sigma-delta modulator of incoming clock signal, captures number in the microprocessor with same or higher clock frequency
According to rear, 1 and 0 difference is continuously distributed in each pulse period corresponding data flow, passes through homogenization to data stream within the period
Processor carries out Homogenization Treatments, avoids causing error using decimation filter of digital.
The course of work of the invention is as follows:
The input signal V of sigma-delta modulatorINWith feedback signal VDACAnd after reverse phase adder, into integrator
In, obtain integral output signal VINT, signal VINTIt is quantized device to be quantified, obtains the output signal V of quantizerOUT.Made with DAC
For feedback channel, quantizer output signal VOUTFeedback signal V is converted to by DACDAC.The reference voltage of the DAC is
VREF, sigma-delta modulator input signal VINVoltage swing necessarily be in (- VREF,+VREF) in the range of.Sigma-delta modulator
Input signal VINIn the V of feedback voltageDACUnder the action of, voltage swing and output pulse signal VOUTPulse signal density
Proportional relationship.The pulse signal V of outputOUTWhen carrying out data capture, when using the high frequency for exceeding modulator circuit ability to bear
Clock, can quantizer digit and modulator order under the same conditions, reach higher over-sampling rate, to improve noise
Than.
Compared with prior art, the present invention has the advantages that following protrusion:
First, the ADC that sigma-delta modulator of the present invention is constituted is no longer influenced by simulation electricity on improving over-sampling rate
The limitation on road can use high speed microprocessor and reached than existing Σ-using identical quantizer digit and modulator order
The higher signal-to-noise ratio of Δ ADC, realizes higher quantified precision；
Second, the ADC that sigma-delta modulator of the present invention is constituted is not limited on improving over-sampling rate by analog circuit
System, under the requirement of identical signal-to-noise ratio, quantizer digit and modulator order can be lower than existing sigma-delta ADC, accordingly
Analog circuit scale can be smaller, is conducive to the reduction of cost and the realization of digital product；
Third, in data flow corresponding to the pulse signal of sigma-delta modulator output of the present invention, each pulse week
1 and 0 in phase be all it is continuous, the switching frequency of low and high level is slower than existing sigma-delta ADC, can reduce ADC pairs
The requirement of I/O frequency in microprocessor.
Detailed description of the invention
Fig. 1 is the system structure diagram of sigma-delta modulator of the present invention.
Fig. 2 is the emulation experiment waveform diagram of single order sigma-delta modulator example.
Specific embodiment
Below in conjunction with attached drawing, specific embodiments of the present invention are further elaborated.
It is as shown in Figure 1 the system structure diagram of sigma-delta modulator of the present invention.One kind of the present embodiment does not access
The sigma-delta modulator of clock signal, including reverse phase adder 1, the quantizer 3 of integrator 2 and not incoming clock signal are described anti-
Be added musical instruments used in a Buddhist or Taoist mass 1, integrator 2 and quantizer 3 are sequentially connected composition forward path, digital analog converter 5 respectively with quantizer 3 and reverse phase
Adder 1 connects, and forms feedback channel；The output pulse signal V of the sigma-delta modulatorOUTImpulse density and input signal
VINVoltage swing it is directly proportional, and output pulse signal VOUTLow data stream, each pulse period are captured as by microprocessor 4
Corresponding data flow is all to be constituted by continuous 1 plus continuous 0.
The quantizer 3 includes the different first comparator 3.1 and the second comparator 3.2 of two reference voltages in parallel,
And the d type flip flop 3.3 of a not incoming clock signal, the d type flip flop 3.3 connect first comparator 3.1 and second and compare
Device 3.2；The reference voltage V of the first comparator 3.1UPGreater than the reference voltage V of the second comparator 3.2DOWN；Quantizer 3
Input signal VINT, the output signal by first comparator 3.1 is VSD, the output signal by the second comparator 3.2 is VRD,
Output signal VSDWith output signal VRDIt is separately input to d type flip flop 3.3WithEnd, in the state of ignoring external clock
Directly control d type flip flop 3.3The output signal V at endOUT, output signal VOUTThe output of namely entire quantizer 3 is believed
Number.
The microprocessor 4 includes sequentially connected Homogenization Treatments device 4.1 and decimation filter of digital 4.2, quantizer 3
Output pulse signal VOUTLow data stream is captured as by microprocessor 4, the data flow is passed through within each pulse period equal
It homogenizes processor 4.1 and carries out Homogenization Treatments, avoid causing error using decimation filter of digital 4.2.
The circuit parameter of the single order sigma-delta modulator of the present embodiment is provided that the integral constant of integrator 2 is
4.19x10-6S, 3.1 reference voltage V of first comparatorUPFor 1V, 3.2 reference voltage V of the second comparatorDOWNFor 0V, d type flip flop
3.3Hold output signal VOUTLow and high level corresponding voltage be respectively+5V and -5V, DAC5 reference voltage VREFFor 1V.
Using frequency be 2k Hz, amplitude for 0.7V sinusoidal signal as modulator input signal VIN, input signal VIN、
2 output signal V of integratorINTWith d type flip flop 3.3Hold output signal VOUTSimulation waveform it is as shown in Figure 2.When integrator 2
Output signal VINTMore than or equal to 3.1 reference voltage V of first comparatorUPWhen, 3.1 output signal V of first comparatorSDFor low electricity
It is flat, 3.2 output signal V of the second comparatorRDFor high level, so that d type flip flop 3.3The output signal V at endOUTFor low level；
As input signal VINTLess than or equal to 3.2 reference voltage V of the second comparatorDOWNWhen, 3.1 output signal V of first comparatorSDFor height
Level, 3.2 output signal V of the second comparatorRDFor low level, so that d type flip flop 3.3The output signal V at endOUTFor high electricity
It is flat；As input signal VINTGreater than 3.2 reference voltage V of the second comparatorDOWNAnd it is less than 3.1 reference voltage V of first comparatorUPWhen,
D type flip flop 3.3The output signal V at endOUTIt maintains the original state.So 2 output signal V of integratorINTAlways in two comparisons
It is overturn back and forth between the reference voltage of device.
Referring to fig. 2, as the input signal V of modulatorINVoltage swing close to 0V when, 2 response feedback voltages of integrator
VDAC, it is identical in the distribution of two integration direction upper integral times of positive and negative, d type flip flop 3.3The duty ratio of end output pulse
It is close to 50%；As the input signal V of modulatorINVoltage swing be not equal to 0V when, the output signal V of integrator 2INTBy
Input signal VINAnd feedback voltage VDACJoint effect, generate forward and reverse or negative direction inclination, d type flip flop 3.3End
The duty ratio of output is not equal to 50%.
Claims (3)
1. a kind of sigma-delta modulator of not incoming clock signal, which is characterized in that including reverse phase adder (1), integrator (2)
The not quantizer (3) of incoming clock signal, the reverse phase adder (1), integrator (2) and quantizer (3) are sequentially connected group
At forward path, digital analog converter (5) is connect with quantizer (3) and reverse phase adder (1) respectively, forms feedback channel；It is described
The output pulse signal V of sigma-delta modulatorOUTImpulse density and input signal VINVoltage swing it is directly proportional, and export pulse
Signal VOUTLow data stream is captured as by microprocessor (4), each pulse period corresponding data flow is by continuous 1 and even
Continuous 0 is constituted.
2. the sigma-delta modulator of not incoming clock signal according to claim 1, which is characterized in that the quantizer (3)
When not accessed including the different first comparator (3.1) of two reference voltages in parallel and the second comparator (3.2) and one
The d type flip flop (3.3) of clock signal, d type flip flop (3.3) connection first comparator (3.1) and the second comparator (3.2)；Institute
State the reference voltage V of first comparator (3.1)UPGreater than the reference voltage V of the second comparator (3.2)DOWN；Quantizer (3) it is defeated
Enter signal VINT, the output signal by first comparator (3.1) is VSD, the output signal by the second comparator (3.2) is
VRD, output signal VSDWith output signal VRDIt is separately input to d type flip flop (3.3)WithEnd, is ignoring external clock
D type flip flop (3.3) is directly controlled under stateThe output signal V at endOUT, output signal VOUTNamely entire quantizer
(3) output signal.
3. the sigma-delta modulator of not incoming clock signal according to claim 1, which is characterized in that the microprocessor
It (4) include sequentially connected Homogenization Treatments device (4.1) and decimation filter of digital (4.2), the output pulse letter of quantizer (3)
Number VOUTLow data stream is captured as by microprocessor (4), Homogenization Treatments device is passed through to the data flow within each pulse period
(4.1) Homogenization Treatments are carried out, avoid causing error using decimation filter of digital (4.2).
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1632471A (en) * | 2004-12-02 | 2005-06-29 | 上海大学 | Threshold adaptive processing method and device for vortex shedding flowmeter signal |
| CN104247272A (en) * | 2012-04-19 | 2014-12-24 | 丰田自动车株式会社 | [Delta][sigma] modulator and [delta][sigma] A/D converter |
| US20160308552A1 (en) * | 2007-03-14 | 2016-10-20 | Benjamin H. Ashmore, Jr. | Method, system and apparatus for dual mode operation of a converter |
| CN106568996B (en) * | 2016-11-17 | 2019-03-05 | 中国电子科技集团公司第四十一研究所 | A kind of efficient low distortion digital oscilloscope training signal generating circuit and method |
-
2019
- 2019-05-08 CN CN201910377879.4A patent/CN110166054A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1632471A (en) * | 2004-12-02 | 2005-06-29 | 上海大学 | Threshold adaptive processing method and device for vortex shedding flowmeter signal |
| US20160308552A1 (en) * | 2007-03-14 | 2016-10-20 | Benjamin H. Ashmore, Jr. | Method, system and apparatus for dual mode operation of a converter |
| CN104247272A (en) * | 2012-04-19 | 2014-12-24 | 丰田自动车株式会社 | [Delta][sigma] modulator and [delta][sigma] A/D converter |
| CN106568996B (en) * | 2016-11-17 | 2019-03-05 | 中国电子科技集团公司第四十一研究所 | A kind of efficient low distortion digital oscilloscope training signal generating circuit and method |
Non-Patent Citations (1)
| Title |
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| 夏罗容 等: "一种新型 Sigma－Delta ADC 调制器的设计及验证", 《工业控制计算机》 * |
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