CN110164503A - A kind of semiconductor component test fixture, test macro and test method - Google Patents
A kind of semiconductor component test fixture, test macro and test method Download PDFInfo
- Publication number
- CN110164503A CN110164503A CN201910469211.2A CN201910469211A CN110164503A CN 110164503 A CN110164503 A CN 110164503A CN 201910469211 A CN201910469211 A CN 201910469211A CN 110164503 A CN110164503 A CN 110164503A
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- Prior art keywords
- test
- fixture
- test fixture
- component
- semiconductor
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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- Tests Of Electronic Circuits (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The present invention provides a kind of semiconductor component test fixture, test macro and test method, the present invention is by designing a kind of novel test fixture, and in test, semiconductor subassembly can be automatically loaded into test fixture, and test is executed when component is in fixture.After all tests are completed, semiconductor subassembly can be unloaded from test fixture automatically.Since it can be loaded automatically and unload semiconductor subassembly, without permanent weld.And test fixture convenient can be mounted on using in mainboard, can quickly be designed and produced, development cost is in 5K dollars of ranges, suitable for the new product of small lot production, without the processor or testing tool as capital intensive in the prior art.True application is more really simulated using the test environment on mainboard, identical noise, load and speed when having with real work, to realize better product quality and lower production loss.
Description
Technical field
The present invention relates to semiconductor test technical field, especially a kind of semiconductor component test fixture, test macro and
Test method.
Background technique
DRAM technology has had the history of many years, and with time change, fundamental technology is held essentially constant, interface with when
Between variation and change, such as fast page mode (FPM), growth data export (EDO), synchronous dram (SDRAM), Double Data
Rate 1-4 (DDR1, DDR2, DDR3, DDR4) etc..In some applications, DRAM component, which is soldered in PCB substrate, forms one
Module, such as DIMM module are inserted into the mainboard of computer system.
Traditionally, several steps of test point and repeatedly insertion completion of memory subassembly are encapsulated.
In general, the DRAM component of encapsulation is submitted to burn-in test first.The test is held in ageing system with high concurrency
Row, the cost of each test macro are 500K-1M dollars.Since the number of components tested and contacted is more, the system is in 5-
It is run under the low frequency of 20MHz or so, this is far below the normal working frequency 1GHz of this semiconductor.In order to reduce the need to signal
It wants, all data-signals are compressed on single external data pin by most methods using chip interior test circuit, such as will
16DQ is compressed on single DQ, and modifies builtin voltage using other test patterns, to obtain more effective memory subassembly stress.
The purpose of burn-in test is to make semiconductor aging under several hours pressure, incipient failure occurs to avoid in customers' place.Phase
The pressure test of pass usually in raised voltage and up to 125 degrees Celsius at a temperature of carry out, usually in single burn-in test system
The thousands of components of concurrent testing in system.
After burn-in test success, component is submitted in weak cells or core test.These tests should identify weak DRAM
Memory cell, since memory cell retains bad or other defect, these memory cells may be out of order in customers' place.
Test is carried out in automatic test equipment, and typically cost is 1M-3M dollars, working frequency 200-500MHz, parallel to survey
Try 200-1000 component.Due to the provision of a large amount of signals, some signals such as address/command symbol will be total between multiple components
Enjoy, chip supplier provides the test pattern of data compression, it is therefore desirable to the DQ of continuous reduction amount, such as only 4 numbers it is believed that
Number rather than by data compression (readings) and replicate complete 16 signals of (write-in) method acquisition.This test can be not
It is carried out at a temperature of, some components can be tested, such as under 95 degrees Celsius, dismantle from system, later in different surveys
It is tested under subzero 40 degrees Celsius on test system.Disassembly is necessary, because test processor cannot not have other
So rapidly change temperature in the case where adverse effect.
After weak cells are successfully tested, component will be submitted to carry out velocity test.During testing herein, all electric signals of component
It requires to be connected to tester, to ensure that all signals and circuit work normally completely.DRAM with 16DQ is necessarily connected to
16 independent DQ signals are without compact model.Therefore, the concurrency of this test macro is in the lower of 50-200 component
In range.In addition, component must be run under the total system speed of 1GHz.Therefore, this system is very expensive, usually 3M-
5M dollars, and may also need to be tested at different temperature, such as 90 degrees Celsius and later subzero 40 degrees Celsius,
To ensure to meet specification requirement of the client to global function component.
In conclusion the testing process of sophisticated semiconductor is costly and complicated, such as DRAM package assembling, at least 3 are submitted to
A different test macro is used for aging, weak cells and velocity test.Some testing procedures may need at different temperature
It carries out, needs to submit up to 5 times tests.This means that if necessary to retest, component by 5 times processed or more, and
This will lead to the processing damage of electric shock, such as the contact ball of FBGA component, and be unavoidable in current test method.
Furthermore, it is necessary to which very expensive tool provides in test processor and handles DRAM component, and it is electrically coupled to test
Head.These tools are specific for product, it is necessary to provide for each DRAM, the FBGA of FPGA 78 packet and 7x10mm of 9x11mm
96 packets need entirely different tool and Hifix, and the kit of a product can be easily more than 250,000 dollars.
Summary of the invention
The object of the present invention is to provide a kind of semiconductor component test fixture, test macro and test methods, it is intended to solve
Semiconductor test process is complicated in the prior art and cost is high, realizes and completes semiconductor component test with low cost, and surveys
Examination is convenient.
To reach above-mentioned technical purpose, the present invention provides a kind of semiconductor component test fixture, the test fixture packet
It includes:
Slot, for being electrically connected at least X active electric signals of semiconductor subassembly；
Plane component connects machine at least one for PCB or the socket being mounted on the plane component at least two
The element of element；
At least X active electric signals of the semiconductor subassembly are connected to the plane component from the socket, and pass through
The plane component is routed to the connecting element.
Preferably, the test fixture is for executing aging, weak cells and velocity test.
The present invention also provides a kind of system for testing semi-conductor components tested using the test fixture, the surveys
Test system includes:
Semiconductor component test fixture, Application testing plate and the software for executing equipment under test test operation；
Load semiconductor subassembly of the semiconductor component test fixture for impermanency；
The Application testing plate has one or more test fixtures, these test fixtures with connector,
In at least one connector signal will be electrically connected to Application testing plate；
The software for executing equipment under test test operation is present in using the quilt on test board or on test fixture
On the semiconductor subassembly of test, wherein software executes the functional test of equipment under test on Application testing plate.
Preferably, the semiconductor subassembly is DRAM component, and the quantity of the test fixture of DRAM component is no more than 36.
Preferably, the test operation includes aging, weak cells and velocity test.
Preferably, the equipment under test of the test fixture does not have between the test not carried out at the same temperature at least twice
It is unloaded.
Preferably, the Application testing plate includes at least one processor or Application testing based on INTEL
Plate includes at least one processor based on AMD.
Preferably, the test fixture is closed in a temperature chamber, but the Application testing plate is not enclosed
This temperature chamber；
The temperature chamber can realize that caloric test temperature, low-temperature test refer to subzero 5 degrees Celsius or temperature below, high temperature
Test refers to that temperature is 80 degrees Celsius or more.
It is described the present invention also provides a kind of semi-conductor component test process based on the system for testing semi-conductor components
Method includes following operation:
The test fixture being loaded into semiconductor element by using automatic equipment in the system for testing semi-conductor components
On；
Functional test is carried out using the system for testing semi-conductor components；
Semiconductor subassembly is unloaded from the test fixture in the system for testing semi-conductor components by using automatic equipment
It carries.
Preferably, the equipment under test tested at a temperature of two or more is different only fills on test fixture
Carry primary, or the equipment under test tested at a temperature of two or more is different only unloads one from test fixture
It is secondary.
The effect provided in summary of the invention is only the effect of embodiment, rather than invents all whole effects, above-mentioned
A technical solution in technical solution have the following advantages that or the utility model has the advantages that
Compared with prior art, the present invention is by designing a kind of novel test fixture, and in test, semiconductor subassembly can
It is automatically loaded into test fixture, test is executed when component is in fixture.It, can be automatically from test after all tests are completed
Semiconductor subassembly is unloaded on fixture.Since it can be loaded automatically and unload semiconductor subassembly, without permanent weld.And it tests
Fixture convenient can be mounted on using in mainboard, can quickly be designed and produced, and development cost is suitable for small in 5K dollars of ranges
The new product of batch production, without the processor or testing tool as capital intensive in the prior art.Using on mainboard
Test environment more really simulate true application, identical noise, load and speed when having with real work, thus real
Now better product quality and lower production loss.
Detailed description of the invention
Fig. 1 is a kind of test fixture connection schematic diagram provided by the embodiment of the present invention.
Specific embodiment
In order to clearly illustrate the technical characterstic of this programme, below by specific embodiment, the present invention is carried out detailed
It illustrates.Following disclosure provides many different embodiments or example is used to realize different structure of the invention.For simplification
Disclosure of the invention is hereinafter described the component of specific examples and setting.In addition, the present invention can be in different examples
Repeat reference numerals and/or letter.This repetition is for purposes of simplicity and clarity, itself not indicate discussed various realities
Apply the relationship between example and/or setting.Present invention omits the descriptions to known assemblies and treatment technology and process to avoid not
The necessarily limitation present invention.
Be provided for the embodiments of the invention below a kind of semiconductor component test fixture, test macro and test method into
Row is described in detail.
The embodiment of the invention discloses a kind of semiconductor component test fixture, the test fixture includes:
Slot, for being electrically connected at least X active electric signals of semiconductor subassembly；
Plane component such as PCB or other have at least two sockets being mounted on the plane component and at least one connect machine
The element of device element；
At least X active electric signals of the semiconductor subassembly are connected to the plane component from the socket, and pass through
The plane component is routed to the connecting element.
The embodiment of the present invention is described in detail the method by taking DRAM as an example.
In the background technology, it has been described that state-of-the-art memory subassembly test method, in addition, some finished products and welding
Memory modules are tested on mainboard, referred to as application test or abbreviation APT test.When carrying out this test, there are two
Reason: because the performances of certain internal storage locations can be reduced in welding process, and the performance that executes in the application of DRAM with
It is different in the module testing environment of no signal noise or shared signal.
Therefore, the embodiment of the present invention executes all components test, including aging, weak cells and speed in the application
Test.For this reason, it may be necessary to which component is automatically loaded into test fixture, when component is in fixture, test will be executed.All tests
After completion, the unloading assembly from fixture easily it can load and unload due to being not necessarily to permanent weld automatically.
The semiconductor element test fixture is described partly to lead for temporarily holding and contacting more than one semiconductor element
Volume elements part is temporarily fixed in slot or other equipment, without welding or using other means of permanent attachment.
Slot is set in test fixture, for being electrically connected at least X active electric signals of semiconductor subassembly, is additionally provided with
Plane component as PCB or other there are at least two sockets being mounted on the plane component and at least one connects machine element
Element.At least X active electric signals of the semiconductor subassembly are connected to the plane component from the socket, and by described
Plane component is routed to the connecting element.
Most element test carried out to semiconductor element thereon by test fixture, including aging, weak cells with
And velocity test, at least 50% functional test are carried out in this test macro.
Preferably, only one connecting element of the test fixture, the connecting element follow any of DRAM module
JEDEC standard.
The embodiment of the invention also discloses a kind of system for testing semi-conductor components, the system comprises:
Semiconductor component test fixture, Application testing plate and the test for executing equipment under test described above
The software of operation.
Load semiconductor element of the semiconductor component test fixture for impermanency, these semiconductor elements become
Equipment under test (DUT)；
The Application testing plate has one or more test fixtures, these test fixtures with connector,
In at least one connector signal will be electrically connected to Application testing plate；
The software of the test operation for executing equipment under test is present in using on test board or in test fixture
Tested semiconductor subassembly on, wherein software executes the functional test of DUT on Application testing plate.
At least one DUT is DRAM component on the test fixture, and the quantity of the test fixture of the DRAM component is not
More than 36.
DUT on the test fixture is not unloaded between the test not carried out at the same temperature at least twice.
The Application testing plate includes at least one processor based on INTEL or the processor based on AMD.
During the test, the test fixture is closed in a temperature chamber, but the Application testing plate
This temperature chamber is not enclosed.The temperature chamber can realize that caloric test temperature, low-temperature test refer to subzero 5 degrees Celsius or temperature below
Degree, hot test refer to that temperature is 80 degrees Celsius or more.
In cycle tests, DUT keeps load on same fixture, and at least there are two different Application testing plates to come
For testing, without by DUT from fixture loading or unloading.
Identification for test fixture can carry out unique identification, example by printing or being attached to the label on the fixture
The form of bar code can be used such as to be identified；Or it is another on fixture using being mounted on by the reading of Application testing plate
One semiconductor subassembly, such as detected using SPD EPROM:SPD=serial presence, to uniquely identify.
The embodiment of the invention also discloses a kind of semi-conductor component test process, the method utilizes previously described one kind
Semiconductor semiconductor device test system is tested.
Before testing, semiconductor element is loaded on test fixture by using automatic equipment, such as aging loading machine
Or industrial robot；After a test, equally semiconductor subassembly is unloaded from test fixture by using automatic equipment, such as
Aging unloader or industrial robot.
In test process, using test fixture described previously, when DUT is still mounted on fixture, laser is carried out to DUT and is beaten
Mark.When carrying out burn-in test, the DUT tested at a temperature of two or more is different is only filled on test fixture
Carry it is primary, or the DUT that is tested at a temperature of two or more is different only unloaded from test fixture it is primary.
The embodiment of the present invention is by designing a kind of novel test fixture, and in test, semiconductor subassembly can load automatically
Into test fixture, test is executed when component is in fixture.After all tests are completed, it can be unloaded from test fixture automatically
Carry semiconductor subassembly.Since it can be loaded automatically and unload semiconductor subassembly, without permanent weld, as shown in Figure 1, and surveying
Examination fixture convenient can be mounted on using in mainboard, can quickly be designed and produced, development cost is suitable in 5K dollars of ranges
The new product of small lot production, without the processor or testing tool as capital intensive in the prior art.Using mainboard
On test environment more really simulate true application, identical noise, load and speed when having with real work, thus
Realize better product quality and lower production loss.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Made any modifications, equivalent replacements, and improvements etc., should all be included in the protection scope of the present invention within mind and principle.
Claims (10)
1. a kind of semiconductor component test fixture, which is characterized in that the test fixture includes:
Slot, for being electrically connected at least X active electric signals of semiconductor subassembly；
Plane component connects machine element at least one for PCB or the socket being mounted on the plane component at least two
Element；
At least X active electric signals of the semiconductor subassembly are connected to the plane component from the socket, and by described
Plane component is routed to the connecting element.
2. a kind of semiconductor component test fixture according to claim 1, which is characterized in that the test fixture is for holding
Row aging, weak cells and velocity test.
3. a kind of system for testing semi-conductor components tested using test fixture described in as claimed in claim 1 or 22, feature are existed
In the test macro includes:
Semiconductor component test fixture, Application testing plate and the software for executing equipment under test test operation；
Load semiconductor subassembly of the semiconductor component test fixture for impermanency；
The Application testing plate has one or more test fixtures, these test fixtures with connector, wherein extremely
A rare connector signal will be electrically connected to Application testing plate；
The software for executing equipment under test test operation is present in be tested using on test board or on test fixture
Semiconductor subassembly on, wherein software executes the functional test of equipment under test on Application testing plate.
4. a kind of system for testing semi-conductor components according to claim 3, which is characterized in that the semiconductor subassembly is
DRAM component, and the quantity of the test fixture of DRAM component is no more than 36.
5. a kind of system for testing semi-conductor components according to claim 3, which is characterized in that the test operation includes old
Change, weak cells and velocity test.
6. a kind of system for testing semi-conductor components according to claim 3, which is characterized in that the test fixture is tested
Equipment is not unloaded between the test not carried out at the same temperature at least twice.
7. a kind of system for testing semi-conductor components according to claim 3, which is characterized in that the Application testing plate
Processor or Application testing plate including at least one based on INTEL include at least one processor based on AMD.
8. according to a kind of system for testing semi-conductor components described in claim 3-7 any one, which is characterized in that the test
Fixture is closed in a temperature chamber, but the Application testing plate does not enclose this temperature chamber；
The temperature chamber can realize that caloric test temperature, low-temperature test refer to subzero 5 degrees Celsius or temperature below, hot test
Refer to that temperature is 80 degrees Celsius or more.
9. a kind of semi-conductor component test process based on system for testing semi-conductor components as claimed in claim 3, feature exist
In the method includes following operations:
Semiconductor element is loaded on the test fixture in the system for testing semi-conductor components by using automatic equipment；
Functional test is carried out using the system for testing semi-conductor components；
Semiconductor subassembly is unloaded from the test fixture in the system for testing semi-conductor components by using automatic equipment.
10. a kind of semi-conductor component test process according to claim 9, which is characterized in that at two or more
The equipment under test tested at a temperature of different only loads on test fixture primary or different at two or more
At a temperature of the equipment under test tested only unloaded from test fixture it is primary.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910469211.2A CN110164503A (en) | 2019-05-31 | 2019-05-31 | A kind of semiconductor component test fixture, test macro and test method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910469211.2A CN110164503A (en) | 2019-05-31 | 2019-05-31 | A kind of semiconductor component test fixture, test macro and test method |
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| Publication Number | Publication Date |
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| CN110164503A true CN110164503A (en) | 2019-08-23 |
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| CN201910469211.2A Pending CN110164503A (en) | 2019-05-31 | 2019-05-31 | A kind of semiconductor component test fixture, test macro and test method |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1416163A (en) * | 2002-10-24 | 2003-05-07 | 威盛电子股份有限公司 | System, equipment and method for automatic testing IC complete device |
| CN105845185A (en) * | 2016-03-24 | 2016-08-10 | 苏州普福斯信息科技有限公司 | Test fixture for testing ball grid array flash memory packaging, and method of screening flash memories therewith |
| US20180038905A1 (en) * | 2016-08-05 | 2018-02-08 | Samsung Electronics Co., Ltd. | Apparatus for testing semiconductor package |
| CN207443139U (en) * | 2017-08-17 | 2018-06-01 | 威刚科技股份有限公司 | thin heating device |
-
2019
- 2019-05-31 CN CN201910469211.2A patent/CN110164503A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1416163A (en) * | 2002-10-24 | 2003-05-07 | 威盛电子股份有限公司 | System, equipment and method for automatic testing IC complete device |
| CN105845185A (en) * | 2016-03-24 | 2016-08-10 | 苏州普福斯信息科技有限公司 | Test fixture for testing ball grid array flash memory packaging, and method of screening flash memories therewith |
| US20180038905A1 (en) * | 2016-08-05 | 2018-02-08 | Samsung Electronics Co., Ltd. | Apparatus for testing semiconductor package |
| CN207443139U (en) * | 2017-08-17 | 2018-06-01 | 威刚科技股份有限公司 | thin heating device |
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