CN110164355B - Control signal output circuit and method, array substrate and display device - Google Patents
Control signal output circuit and method, array substrate and display device Download PDFInfo
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The invention provides a control signal output circuit and method, an array substrate and a display device, belonging to the technical field of display, wherein the control signal output circuit comprises: the time sequence unit is used for respectively providing time sequence signals for the first grid driving circuit and the second grid driving circuit according to a preset scanning time sequence; wherein, the time sequence signal includes: a first control signal and a second control signal; the judging unit is used for judging which one of the first grid driving circuit and the second grid circuit is to work according to the time sequence signal provided by the time sequence unit and outputting a judging result; and the selection unit is used for outputting the first control signal or the second control signal according to the judgment result output by the judgment unit.
Description
Technical Field
The invention belongs to the technical field of display, and particularly relates to a control signal output circuit and method, an array substrate and a display device.
Background
With the continuous development of display technology, the comprehensive screen is more and more popularized, however, the top end of the screen needs to be provided with non-display devices such as a camera, a receiver and a facial recognition sensor, the area at the top end of the screen needs to be occupied, and the real comprehensive screen cannot be achieved at present. In view of the above, a more popular method is to provide a notch at the top of the screen for mounting the non-display device. In order to avoid the influence of the notch on the display picture, a specific icon picture, such as a clock, an application icon, electric quantity, operator information and the like, is basically and fixedly displayed in the display area at the top end of the screen. These fixed icons do not need to be refreshed at the regular 60 Hz frequency, but in practical applications, the top display area and the normal display area are generally refreshed in real time as one screen.
The inventor finds that at least the following problems exist in the prior art: the display area at the top of the screen and the normal display area are used as a screen and are refreshed in real time at the conventional frequency of 60 Hz, so that the processing capacity of the driving chip in unit time is overlarge, the power consumption is increased, and the writing time of single-row data voltage in the whole screen is too short, which easily causes abnormal screen display.
Disclosure of Invention
The present invention is directed to at least one of the technical problems in the prior art, and provides a control signal output circuit and method, an array substrate, and a display device.
The technical scheme adopted for solving the technical problem is a control signal output circuit which is used for outputting a first control signal for a first grid drive circuit and outputting a second control signal for a second grid drive circuit; the number of pixels in the pixel row connected with the first gate driving circuit is less than that of the pixels in the pixel row connected with the second gate driving circuit; the control signal output circuit includes:
the time sequence unit is used for respectively providing time sequence signals for the first grid driving circuit and the second grid driving circuit according to a preset scanning time sequence; wherein the timing signal includes: a first control signal and a second control signal;
the judging unit is used for judging which one of the first grid driving circuit and the second grid circuit is to work according to the time sequence signal provided by the time sequence unit and outputting a judging result;
and the selection unit is used for outputting the first control signal or the second control signal according to the judgment result output by the judgment unit.
Optionally, the selecting unit includes: a first transistor and a second transistor; the switching characteristics of the first transistor and the second transistor are opposite; wherein,
the first pole of the first transistor is connected with the time sequence unit, the second pole of the first transistor is connected with the first grid driving circuit, and the control pole of the first transistor is connected with the judging unit;
the first pole of the second transistor is connected with the time sequence unit, the second pole of the second transistor is connected with the second grid driving circuit, and the control pole of the second transistor is connected with the judging unit.
Optionally, the first control signal and the second control signal each include: a frame start signal; or,
the first control signal and the second control signal each include: a clock control signal.
Optionally, an output frequency of the first control signal is smaller than an output frequency of the second control signal.
The technical scheme adopted for solving the technical problem of the invention is an array substrate which comprises the control signal output circuit.
Optionally, the array substrate further includes: a first gate driving circuit and a second gate driving circuit, both connected with the selection unit.
Optionally, the array substrate has a first display area and a second display area; the array substrate comprises grid lines and data lines which are arranged in a crossed mode; the grid line in the first display area is connected with the output end of the first grid driving circuit; the grid line in the second display area is connected with the output end of the second grid driving circuit; the data line penetrates through the first display area and the second display area.
Optionally, the image refresh frequency of the first display area is lower than the image refresh frequency of the second display area.
The technical scheme adopted for solving the technical problem of the invention is a display device which comprises the array substrate provided as above.
The technical scheme adopted for solving the technical problem of the invention is a control signal output method, which is used for outputting a first control signal for a first grid drive circuit and outputting a second control signal for a second grid drive circuit; the number of pixels in the pixel row connected with the first gate driving circuit is less than that of pixels in the pixel row connected with the second gate driving circuit; the control signal output method includes:
respectively providing timing signals for the first gate driving circuit and the second gate driving circuit according to a preset scanning timing sequence; wherein the timing signal includes: a first control signal and a second control signal;
judging which one of the first grid electrode driving circuit and the second grid electrode circuit is to work according to the time sequence signal, and outputting a judgment result;
and outputting the first control signal or the second control signal according to the judgment result.
Drawings
Fig. 1 is a schematic diagram of a control signal output circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a selection unit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 4 is a flowchart of a control signal output method according to an embodiment of the present invention;
fig. 5 is a preset scan timing diagram according to an embodiment of the invention.
Description of reference numerals:
10-control signal output circuit, 101-timing unit, 102-judgment unit, 103-selection unit, 201-first gate driving circuit, 202-second gate driving circuit, 1031-first transistor, 1032-second transistor, 301-first display region, 302-second display region, 401-gate line, and 402-data line.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
At present, in order to achieve the display effect of a full-screen, a display terminal generally includes two display areas with different numbers of pixels in rows, which may be referred to as: a first display area and a second display area. The first display area basically and fixedly displays specific pictures, such as a clock, application icons, electric quantity, operator information and the like. The second display area is a normal display area and can display pictures required by a user. Since the notch is arranged in the first display area, the number of the pixels in the row of the first display area is different from that in the row of the second display area. In practical application, the first display area and the second display area are generally used as a screen to be refreshed in real time, so that the processing amount of the driving chip in unit time is easily overlarge, the power consumption is increased, and the writing time of single-row data voltage in the whole screen is too short, so that abnormal screen display is easily caused. In order to solve the problems in the prior art, embodiments of the present invention provide a control signal output circuit and method, an array substrate, and a display device. A first grid driving circuit in the array substrate is connected with a grid line of a first display area, and a second grid driving circuit is connected with a grid line of a second display area. The control signal provided by the control signal output circuit can be a frame start signal or a clock signal. Of course, the output control signal may be another signal for driving the first gate driving circuit and the second gate driving circuit, and the frame on signal will be described in the following embodiments.
Example one
The embodiment of the invention provides a control signal output circuit, which outputs a first control signal for a first grid drive circuit and outputs a second control signal for a second grid drive circuit; the number of pixels in the pixel row connected with the first gate driving circuit is less than that of pixels in the pixel row connected with the second gate driving circuit. Fig. 1 is a schematic diagram of a control signal output circuit according to an embodiment of the present invention, and as shown in fig. 1, the control signal output circuit 10 includes: a timing unit 101, a judging unit 102 and a selecting unit 103.
The timing unit 101 is configured to provide timing signals for the first gate driving circuit 201 and the second gate driving circuit 202 according to a preset scanning timing; wherein, the time sequence signal includes: a first control signal and a second control signal. The determining unit 102 is configured to determine which of the first gate driving circuit 201 and the second gate driving circuit 202 is to operate according to the timing signal provided by the timing unit 101, and output a determination result. The selecting unit 103 is configured to output the first control signal or the second control signal according to the determination result output by the determining unit 102.
It should be noted that the timing signal provided by the timing unit 101 may be a first control signal and a second control signal, or may be another signal for determining which of the first gate driving circuit 201 and the second gate driving circuit 202 is to start operating.
In the control signal output circuit provided by the embodiment of the present invention, the timing unit 101 may output different timing signals for the first gate driving circuit 201 and the second gate driving circuit 202. The determining unit 102 may determine which of the first gate driving circuit 201 and the second gate driving circuit 202 is to start to operate according to the timing signal. When the first gate driving circuit 201 is determined to be about to start operating, the selecting unit 103 outputs a first control signal to the first gate driving circuit 201, and a frame of a first display region in the display terminal starts to be refreshed. When the second gate driving circuit 202 is determined to be about to start operating, the selecting unit 103 outputs a second control signal to the second gate driving circuit, and the screen corresponding to the second display region in the display terminal starts to be refreshed. Therefore, different control signals can be independently input into the first gate driving circuit 201 and the second gate driving circuit 202, and pictures displayed in the first display area and the second display area in the display terminal are refreshed at different frequencies, so that the first display area image displaying the fixed icon picture at the top of the screen can be refreshed at a lower frequency, the processing amount of a driving chip in unit time is reduced, the energy consumption is reduced, the writing time of single-row data voltage in the screen is ensured, and the display effect is improved.
Based on the control signal output circuit provided in the above embodiment, the control signal output circuit will be further described in detail with reference to the accompanying drawings.
Example two
Fig. 2 is a schematic structural diagram of a selecting unit according to an embodiment of the present invention, and as shown in fig. 2, the selecting unit 103 includes: a first transistor 1031 and a second transistor 1032; the switching characteristics of the first transistor 1031 and the second transistor 1032 are opposite; a first pole of the first transistor 1031 is connected to the timing unit 101, a second pole is connected to the first gate driving circuit 201, and a control pole is connected to the determining unit 102; the second transistor 1032 has a first electrode connected to the timing unit 101, a second electrode connected to the second gate driving circuit 202, and a control electrode connected to the determining unit 102.
It should be noted that the switching characteristics of the first transistor 1031 and the second transistor 1032 are opposite, and in the embodiment of the present invention, the first transistor 1031 is a P-type transistor, and the second transistor 1032 is an N-type transistor. Since the operating level of the first transistor 1031 is at a low level, when the control level of the first transistor 1031 is a low level signal, the first pole and the second pole of the first transistor 1031 are turned on, and the first control signal is input from the first pole to the second pole and then output to the first gate driving circuit 201. Since the operating level of the second transistor 1032 is at a high level, when the control level of the second transistor 1032 is a high level signal, the first pole and the second pole of the second transistor 1032 are turned on, and the second control signal is input from the first pole to the second pole and then output to the second gate driving circuit 202. The selection unit 103 according to the embodiment of the present invention may determine to output a high level or a low level according to the determination result, so as to control whether the first transistor 1031 is turned on or the second transistor 1032 is turned on, thereby implementing individual control on the first gate circuit 201 and the second gate circuit 202, and ensuring that the pixel connected to the first gate circuit 201 and the pixel connected to the second gate circuit 202 are refreshed at different frequencies, so that the first display region image displaying the fixed icon picture at the top of the screen may be refreshed at a lower frequency, thereby reducing the processing amount of the driving chip per unit time to reduce energy consumption, ensuring the write-in time of the single row data voltage in the screen, and improving the display effect.
It is understood that the structure of the selection unit 103 shown in fig. 2 is only an example, and in the selection unit 103 provided in the embodiment of the present invention, the determination result may be a high-low level signal to determine that the first gate circuit 201 or the second gate circuit 202 is to start to operate, or may be an indication signal to indicate that the first gate circuit 201 or the second gate circuit is to start to operate by outputting an indication signal. Therefore, the selection structure 103 provided in the embodiment of the present invention may also be implemented by using other circuit structures that can implement the selection function, which are not listed here.
Optionally, the first control signal and the second control signal each include: a frame start signal; or, the first control signal and the second control signal each include: a clock control signal.
It should be noted that, a frame start signal or a clock control signal is separately input to the first gate driving circuit 201 or the second gate driving circuit 202 in a certain period according to a preset time sequence, so as to implement separate control of the first gate driving circuit 201 and the second gate driving circuit 202, and ensure that the pixels connected to the first gate driving circuit 201 and the pixels connected to the second gate driving circuit 202 are refreshed at different frequencies, so that a display area on the top of a screen displaying a fixed icon picture can be refreshed at a lower frequency, thereby reducing the processing amount of a driving chip per unit time to reduce energy consumption, ensuring the write-in time of a single row data voltage in the screen, and improving the display effect.
Optionally, the output frequency of the first control signal is less than the output frequency of the second control signal.
It should be noted that, since the number of pixels in the pixel row to which the first gate driving circuit to which the first control signal is input is connected is less than the number of pixels in the pixel row to which the second gate driving circuit to which the second control signal is input is connected, the first control signal does not have to be output at the same normal frequency as the second control signal, and the first control signal may be output at a lower frequency and the second control signal may be output at a normal frequency. Correspondingly, the first display area image for displaying the fixed icon picture is refreshed at a lower frequency, so that the energy consumption is saved, and the display effect is improved.
EXAMPLE III
Based on the same inventive concept, embodiments of the present invention provide an array substrate including the control signal output circuit provided in the above embodiments. Fig. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention, and as shown in fig. 3, the array substrate includes, in addition to the control signal output circuit 10 provided in the foregoing embodiment: the first gate driving circuit 201 and the second gate driving circuit 202, and the first gate driving circuit 201 and the second gate driving circuit 202 are both connected to the selection unit 103. The array substrate is provided with a first display area 301 and a second display area 302; the array substrate includes a gate line 401 and a data line 402 arranged in a crossing manner; wherein, the gate line 401 in the first display region 301 is connected to the output terminal of the first gate driving circuit 201; the gate line 401 located in the second display region 302 is connected to an output terminal of the second gate driving circuit 202; the data line 402 passes through the first display area 301 and the second display area 302.
According to the array substrate provided by the embodiment of the invention, the control signal output circuit 10 outputs the first control signal and the second control signal according to the preset time sequence, and the first gate driving circuit 201 and the second gate driving circuit 202 are respectively controlled, so that the first display area 301 for displaying a fixed icon picture and the second display area 302 for normally displaying the fixed icon picture can be independently controlled, and the first display area 301 and the second display area 302 can share the data line 402, thereby reducing wiring, reducing the process difficulty and saving the manufacturing cost.
Optionally, the image refresh frequency of the first display area 301 is lower than the image refresh frequency of the second display area 302.
According to the array substrate provided by the embodiment of the invention, the control signal output circuit 10 can provide timing signals for the first gate circuit 201 and the second gate circuit 202 according to a preset timing sequence, judge which of the first gate circuit 201 and the second gate circuit 202 will work, and correspondingly output the first control signal or the second control signal, so that the first gate circuit 201 and the second gate circuit 202 can be independently controlled, and the pixels connected with the first gate circuit and the pixels connected with the second gate circuit are refreshed at different frequencies, therefore, the first display area 301 displaying a fixed icon picture at the top of the screen can be refreshed at a lower frequency than the second display area 302 displaying a fixed icon picture normally, so that the processing amount of a driving chip in unit time is reduced to reduce energy consumption, the writing time of single-row data voltage in the screen is ensured, and the display effect is improved.
Example four
Based on the same inventive concept, embodiments of the present invention provide a display device including the array substrate provided in the above embodiments. It can be understood that the display device provided by the embodiment of the invention can be a smart phone, a notebook computer and the like. The display device provided by the embodiment of the invention is similar to the implementation principle of the control signal output circuit provided by the above embodiment, and is not described herein again.
EXAMPLE five
Based on the same inventive concept, embodiments of the present invention provide a control signal output method, which can be applied to the control signal output circuit provided in the above embodiments, for outputting a first control signal for a first gate driving circuit and outputting a second control signal for a second gate driving circuit; the number of pixels in the pixel row connected with the first gate driving circuit is less than that of pixels in the pixel row connected with the second gate driving circuit. Fig. 4 is a flowchart of a control signal output method according to an embodiment of the present invention, and as shown in fig. 4, the control signal output method includes:
s401, respectively providing timing signals for a first gate driving circuit and a second gate driving circuit according to a preset scanning timing; wherein the timing signal includes: a first control signal and a second control signal.
S402, according to the timing signal, determining which one of the first gate driving circuit and the second gate driving circuit is to operate, and outputting the determination result.
And S403, outputting the first control signal or the second control signal according to the judgment result.
The timing signals include, but are not limited to, the first control signal and the second control signal, and may be other signals for determining which of the first gate driving circuit and the second gate driving circuit is to start operating.
In a specific example, fig. 5 is a preset scan timing diagram provided by the embodiment of the invention, and the timing unit may provide a timing signal according to the preset scan timing diagram shown in fig. 5, and input the first control signal and the second control signal into the first gate driving circuit and the second gate driving circuit, so as to turn on the scan signals of the first display area and the second display area. Specifically, in two periods, the determining unit may determine that the second gate driving circuit is about to start to operate according to the timing signal output by the timing unit. The selection unit outputs a second control signal to the second gate driving circuit according to an input high level signal, wherein the control signal comprises a frame start signal and a clock control signal. At this time, in the two periods, the picture of the second display area connected with the second gate driving circuit is refreshed, and the picture of the first display area connected with the first gate driving circuit is in a normal light-emitting state. In a subsequent period, the determining unit may determine that the first gate driving circuit is about to start to operate according to the timing signal output by the timing unit. The selection unit outputs a first control signal to the first gate driving circuit according to an input low level signal, wherein the control signal comprises a frame start signal and a clock control signal. At this time, in this period, the picture of the first display region connected to the first gate driving circuit is refreshed, and the picture of the second display region connected to the second gate driving circuit is in a normal light-emitting state.
Taking the pixels in the first display area as 200 lines and the screen resolution as 2880 × 1440 as an example, by the control signal output method provided by the embodiment of the invention, the data processing amount is reduced by 200 × 1000 × 2 bits per frame, and the charging time of each line can be increased from 5.7 microseconds (μ s) to 6.2 μ s. It can be seen from the above specific example that, after the picture in the second display region is refreshed twice, the picture in the first display region is refreshed once, and therefore, the picture refresh frequency in the first display region is lower than that in the second display region, so that the processing amount of the driving chip per unit time is reduced to reduce energy consumption, the write-in time of the single row data voltage in the screen is ensured, and the display effect is improved.
It will be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principles of the present invention, and the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and scope of the invention, and such modifications and improvements are also considered to be within the scope of the invention.
Claims (9)
1. A control signal output circuit is used for outputting a first control signal for a first grid drive circuit and outputting a second control signal for a second grid drive circuit; the number of pixels in the pixel row connected with the first gate driving circuit is less than that of the pixels in the pixel row connected with the second gate driving circuit; wherein the control signal output circuit comprises:
the time sequence unit is used for respectively providing time sequence signals for the first grid driving circuit and the second grid driving circuit according to a preset scanning time sequence; wherein the timing signal includes: a first control signal and a second control signal; the preset scanning time sequence is the output sequence of the first control signal and the second control signal; the output frequency of the first control signal is less than the output frequency of the second control signal;
the judging unit is used for judging which one of the first grid driving circuit and the second grid circuit is to work according to the time sequence signal provided by the time sequence unit and outputting a judging result;
and the selection unit is used for outputting the first control signal or the second control signal according to the judgment result output by the judgment unit.
2. The control signal output circuit according to claim 1, wherein the selection unit includes: a first transistor and a second transistor; the switching characteristics of the first transistor and the second transistor are opposite; wherein,
the first pole of the first transistor is connected with the time sequence unit, the second pole of the first transistor is connected with the first grid driving circuit, and the control pole of the first transistor is connected with the judging unit;
the first pole of the second transistor is connected with the time sequence unit, the second pole of the second transistor is connected with the second grid drive circuit, and the control pole of the second transistor is connected with the judgment unit.
3. The control signal output circuit of claim 1,
the first control signal and the second control signal each include: a frame start signal; or,
the first control signal and the second control signal each include: a clock control signal.
4. An array substrate, comprising: the control signal output circuit of any one of claims 1-3.
5. The array substrate of claim 4, further comprising: and the first gate driving circuit and the second gate driving circuit are connected with the selection unit.
6. The array substrate of claim 5, having a first display area and a second display area; the array substrate comprises grid lines and data lines which are arranged in a crossed mode; the grid line in the first display area is connected with the output end of the first grid driving circuit; the grid line in the second display area is connected with the output end of the second grid driving circuit; the data line penetrates through the first display area and the second display area.
7. The array substrate of claim 6, wherein the image refresh rate of the first display region is lower than the image refresh rate of the second display region.
8. A display device comprising the array substrate according to any one of claims 4 to 7.
9. A control signal output method is used for outputting a first control signal for a first grid drive circuit and outputting a second control signal for a second grid drive circuit; the number of pixels in the pixel row connected with the first gate driving circuit is less than that of the pixels in the pixel row connected with the second gate driving circuit; the control signal output method is characterized by comprising the following steps:
according to a preset scanning time sequence, time sequence signals are respectively provided for the first grid driving circuit and the second grid driving circuit; wherein the timing signal includes: a first control signal and a second control signal; the preset scanning time sequence is the output sequence of the first control signal and the second control signal; the output frequency of the first control signal is less than the output frequency of the second control signal;
judging which one of the first grid electrode driving circuit and the second grid electrode circuit is to work according to the time sequence signal, and outputting a judgment result;
and outputting the first control signal or the second control signal according to the judgment result.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106504722A (en) * | 2017-01-12 | 2017-03-15 | 京东方科技集团股份有限公司 | A kind of GOA subregions driving method and device, GOA unit |
| CN107293264A (en) * | 2016-04-04 | 2017-10-24 | 株式会社半导体能源研究所 | Display device, display module and electronic equipment |
| CN107507556A (en) * | 2017-09-30 | 2017-12-22 | 京东方科技集团股份有限公司 | Shift register cell and driving method, gate driving circuit and display device |
| CN108630162A (en) * | 2018-05-10 | 2018-10-09 | 昆山国显光电有限公司 | Display panel and display device |
| CN108648711A (en) * | 2018-06-08 | 2018-10-12 | 厦门天马微电子有限公司 | A kind of array substrate, display panel and display device |
| CN108986749A (en) * | 2017-06-05 | 2018-12-11 | 京东方科技集团股份有限公司 | Pixel unit and driving method, display panel and display methods, display device |
| CN109036246A (en) * | 2018-08-10 | 2018-12-18 | 京东方科技集团股份有限公司 | A kind of display panel, its display methods and display device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101332484B1 (en) * | 2010-12-13 | 2013-11-26 | 엘지디스플레이 주식회사 | Timing controller and display device using the same, and driving method of the timing controller |
| KR20150142708A (en) * | 2014-06-10 | 2015-12-23 | 삼성디스플레이 주식회사 | A gate driving circuit and a display device having the same |
| US9653029B2 (en) * | 2014-08-05 | 2017-05-16 | Apple Inc. | Concurrently refreshing multiple areas of a display device using multiple different refresh rates |
| KR20160045215A (en) * | 2014-10-16 | 2016-04-27 | 삼성디스플레이 주식회사 | Display apparatus having the same, method of driving display panel using the data driver |
| CN109032409B (en) * | 2018-07-26 | 2021-11-02 | 京东方科技集团股份有限公司 | Display panel driving method, display panel and display device |
-
2019
- 2019-06-05 CN CN201910486803.5A patent/CN110164355B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107293264A (en) * | 2016-04-04 | 2017-10-24 | 株式会社半导体能源研究所 | Display device, display module and electronic equipment |
| CN106504722A (en) * | 2017-01-12 | 2017-03-15 | 京东方科技集团股份有限公司 | A kind of GOA subregions driving method and device, GOA unit |
| CN108986749A (en) * | 2017-06-05 | 2018-12-11 | 京东方科技集团股份有限公司 | Pixel unit and driving method, display panel and display methods, display device |
| CN107507556A (en) * | 2017-09-30 | 2017-12-22 | 京东方科技集团股份有限公司 | Shift register cell and driving method, gate driving circuit and display device |
| CN108630162A (en) * | 2018-05-10 | 2018-10-09 | 昆山国显光电有限公司 | Display panel and display device |
| CN108648711A (en) * | 2018-06-08 | 2018-10-12 | 厦门天马微电子有限公司 | A kind of array substrate, display panel and display device |
| CN109036246A (en) * | 2018-08-10 | 2018-12-18 | 京东方科技集团股份有限公司 | A kind of display panel, its display methods and display device |
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